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Lecture 23: DRAM + Driving large capacitances

EECS 312

Reading: 10.3.3, 8.2.3, 8.5 (text)

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Lecture Overview

• Midterm 2 review

• Finish discussion of memories

• Chip packaging overview

• Driving large loads

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Midterm 2

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Packaging

Requirements

• Electrical: Low parasitics

• Mechanical: Reliable and Robust

• Thermal: Efficient Heat Removal

• Economical: Cheap

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Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

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Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers

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Package Types

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Package Parameters

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Driving Large Capacitances

VDD

Vin Vout

CL

tpHL = CL Vswing/2

Iav

Transistor

Sizing

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Using Cascaded Buffers

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = eThis ignores self-loading (junction capacitance of driving stage): derivation on page 450 of text

X = CL/Cin

u = tapering factor

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tp as a function of u and x

1.0 3.0 5.0 7.0u

0.0

20.0

40.0

60.0

u/l

n(u

)

x=10

x=100

x=1000

x=10,000

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Impact of Cascading Buffers

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Output Driver Design

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How to Design Large Transistors

G(ate)

S(ource)

D(rain)

Multiple

Contacts

S

S

G

D

(a) small transistors in parallel(b) circular transistors

We don’t want a long poly run – resistive and large parasitics

Place multiple narrower devices in parallel (with same gate signal)

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Tristate Buffers

In

VDD

En

EnOut

VDD

Out

In

En

En

Useful for signals with multiple drivers

2nd implementation is better in some cases b/c no series connected devices in output stage

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Lecture Summary

• Chips must be put in a package to interface with other devices

• Sending signals off-chip requires a lot of driving capability

• Driving large loads is best done using cascaded buffers with tapering factor of e