VAX

AgendaVAX and its HistoryVAX ISAVAX Virtual AddressMicrocode

What is VAX?Developed by Digital Equipment Corporation (DEC) in the mid-1970sA 32-bit CISC orthogonal instruction setA commercial pioneer in using virtual addressReplace 16-bit PDP-11 ISA15 20 year architecture life spanCompatible with PDP-11 softwareVirtual Address eXtension

VAX HistoryA single ISA with diversified and evolved hardware implementations1977 VAX 11/780 TTL1980 VAX 11/750 TTL1980 VAX 11/730 TTL1984 VAX 8600 ECL1985 MicroVAX II MicroVAX chip 1986 VAX 8800 ECL1987 MicroVAX 3600 CVAX chip VAX station 2000 1989 VAX6600 NVAX chip1989 VAX9000 ECL

First VAX 11/780, installed in CMUVAX 8800MicroVAX IIVAX station 2000

VAX ISA Summary32-bit CISC Architecture16 32-bit registers (r0, r1, .., r15)r12, r13, r14, r15 reserved for AP, FP, SP, PC300+ variable length instructions22 addressing modesISA Designed for Compiler Simplicity and Reduced Code Size

Though VAX is a 32-bitArchitecture, theinstructions can operate on multipleother data formats.

Most familiarly: Integers/Floats of varying sizes Character StringData TypesRich hardware data types to simplify compiler

Sample Instructions (1/3)

Sample Instructions (2/3)

Sample Instructions (3/3)

Instruction VariantsInstruction VariantsOperation + Data type + # of OperandsOperation add, sub Data type byte, word, dword,# of operands 1 ~ 3 register and 1~3 memory (depends on operations)One Sample ADDThe total combination of instructions is 304+, not including address mode variances!

Addressing ModesGeneral Register AddressingLiteral (3 types)RegisterRegister deferredAutodecrement and AutoincrementAutoincrement deferredByte, Word, Longword displacementByte, Longword displacement deferredIndexedProgram Counter AddressingImmediateAbsoluteByte relativeByte relative deferredWord relativeWord relative deferredLongword relativeLongword relative deferred

Register RegisterRegisterMemoryMemory MemoryTotal 22 Addressing Modes

Address mode syntax examplesFigure E.2 From Appendix E

Instruction EncodingA one to two byte OPCODE specifies the operation, number of operands, and data typeAfter the OPCODE has indicated the number of operands, each operand is represented by an Operand Specifier.The Operand Specifier indicates the addressing mode for the operand and the first parameter. Any further parameters must then be read in following their designated Operand Specifier.

Instruction EncodingEach Operand Specifier is also a variable length field with an Address Mode Specifier followed by any of the mode specific required information.VA X

Instruction

Byte

0..1..........NVAX is variable length encoding

Instruction Encoding - LOADMIPS: lw r5, 6(r1)LW OPCODEMOVL OPCODE(r1)6r51 byte 1 byte 1 byte 1 byte = 32 bitsr5r166 bits 5 bits 5 bits 16 bits = 32 bitsVAX: movl 6(r1), r5

Call/Ret Instructionscalls VAX InstructionMulti-cycle instructionIntended to automate and regulate the methods for preserving state before a callUses user-defined bitmask to determine which registers to saveUpdates AP and FP to point to current frames parametersUpdates PC to exec new procedureret VAX InstructionMulti-cycle instructionIntended to automate and regulate the restoration of saved state after the return of a callDoes the opposite of the calls VAX Instruction

These instructions can be highly inefficient.

Total Code Size: MIPS = 15*4 = 60 bytes VAX = 2+4+4+4+5+5+4 = 27 bytesCode DensityHeavy code density due to CALL/RET inst and Addressing modeMIPS:int v[] = $4int k = $5

VAX:int v[] = 4(ap)int k = 8(ap)

Procedure Body Memory Access: MIPS = 4 VAX = 7

Virtual Address Layout4GB Virtual Address Space (2GB Shared), 512Bytes Page Size

Virtual Address Extension SpaceUsing mem. management with page tables, protection, and page faults VAX maps physical memory to a 32-bit (4GB) address spaceIt is divided as shown in the figure to the right:

System Space

Virtual Address TranslationEach Region (S, P0, P1) has One-Level Page Table. System Page Table (S) is stored in physical memory directly. User Page Tables (P0, P1) are stored in S Region virtual address space.PTEPTE Address

Microcode - How to Control Circuit?Find a generic & simple way to control circuit?Each instruction will be translated to a sequence of control signals.Combination LogicAn Accumulator Example 0073422146567

Microcode - ConceptTransform control signals sequence to data01234567

Horizontal & Vertical MicrocodeHorizontal MicrocodeControl field for each control point in the machine

Vertical Microcode (two-level)Compact & simple microinstructionsLocal decoded to generate all control pointsseq addr A-mux B-mux bus enables register enables Load Operand 1 Load Operand nOpcode OperationISA InstructionLocal Control SignalsSame ISA can have different microcode designs

Microcode - ProgrammingSample microcode for MicroVAX: Use microcode routines to implement ISA instructions

Microprogrammed PipelineMicrocode optimization, no hardware cost, horizontal microcode only.

MicropipelineTranslate every CISC instruction to RISC-like microinstructions. Pipeline microinstructions like MIPSADDL2 byte-disp(R1), R2 FIRST OPERAND: VA R1+disp, READ to MD0, New DecodeSECOND OPERAND: Rptr 2, MD1 R[Rptr], New Decode ADDL2: R[Rptr] MD0 + MD1, New DecodeStart of next Instruction:

MacropipelineFirst, pipeline at VAX instruction level Second, pipeline at microcode instruction level in some macro stages.Instruction FlowExecution Macro StagesMicrocode & Micropipeline Stage

SummaryVAX and its historyVirtual Address eXtension, classic VAX 11-780VAX ISA32-bit Variable length CISC ISAVAX Virtual Address4GB VA, 1GB PA, 512bytes page sizeMicrocodeA generic way to control circuitMicrocode PipelineMicroprogrammed pipeline, Micropipeline, Macropipeline

Thank you.

Project ReferencesHennessy, John L., and David A. Patterson. Computer Architecture A Quantitative Approach. 3. San Francisco: Morgan Kaufmann Publishers, 2003.VAX Architecture Handbook. Digital Equipment Corporation, 1981.

***VAX-11 architecture was designed to alleviate the PDP-11's most severe limitation: an address space that was too small for many applications. The Virtual Address eXtension (VAX) increased the address from 16 to 32 bits. The number of general registers also doubled from 8 to 16. The instruction set had both two and three operand formats for many common operations with either a register or memory operand allowable. *Diversified: meet for different markets and different budgetsEvolved: hardware technology development, microarchitecture development.Today our presentation will focused on to things: The first is VAX ISA. As a classic CISC ISA, we will explore its detailsAfter that I will briefly introduce microcode. Microcode is a fundamental technology to implement CISC processor. So we will talk about its concept and several variants.***These are examples of instructions found in VAX for Data transfers and Arithmetic/logic.****Even these modes have sub cases, for instance Indexed indexes differently given the base addressing mode of the command. (Index by byte, word, longword, etc..)

Because PC is a valid register for any addressing mode, 4 of the 22 address modes are synthesized:

***You can have 3 register-register, 3 memory memory, or any combo of those for Operand Specifiers**Parameters stored in memory***512 Byte Pages*********