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2.1Elec 326 Gates and Logic Networks

2. Gates and Logic Networks

ObjectivesThis section is a review and expansion of the followingmaterial covered in Elec 220:

The nature of digital signals

Behavioral models of gates: Truth Table & Logical

Expressions The definition of gate networks.

Analysis of gate networks.

Simple synthesis of gate networks.

A synthesis technique that uses only NAND or NOR gates.

An introduction to Verilog and its use in specifying gatenetwork behavior.




Reading Assignment Most of the concepts covered in this chapter were

introduced in Elec 220.

Most of the material in this chapter is covered in a littlemore depth in Chapter 2: Introduction To Logic Circuits of the Brown & Vranesic book. A few of the topics are

covered in chapters 3 and 4.The negative logic system is covered in section 3.4 (pages 82-83)

of Chapter 3 in Brown & Vranesic.

The analysis of multi-level logic networks is covered in section 4.7(pages 184-189) of Chapter 4 in Brown & Vranesic.

A technique for synthesizing simple, two-level NAND and NOR

networks is given in Chapter 2 of Brown & Vranesic. The notespresent the more general technique (for multi-level networks) givenin section 4.6.3 (pages 181-184) of the text.




2.1. Binary Valued Signals

Signal Values

In any physical system, the voltages can, in theory, take onan unlimited number of different values.

A physical measuring device can only detect a finitenumber of voltages on a wire. The actual number isdetermined by:Noise (in the circuit and/or the measuring device).The complexity (cost) of the measuring device.

In a digital system the possible voltages on a wire aregrouped into a small number (usually two) of ranges and aunique discrete value assigned to each range.

Now we only need to detect which range the voltage is in.More noise can be tolerated.

This is much easier to do, if the signal is not too near a boundary(i.e., less expensive circuits).




If a finite number of ranges is good, using only two rangesshould be best.

There is only one boundary.

Pick a value th called, the threshold , in the middle of all voltagespossible on a wire.

If the observed voltage is > th, we say the signal has one of the two values.

If the observed voltage is < th, we say it has the other.

Binary-valued signals don’t really have only two values, we justtreat them as if they did.

Many models are based on this two-valued assumption.

The actual symbol we use for the two values is not very important,what matters is that there are only two.

Common examples: 0 and 1, Low (L) and High (H),True (T)




How do we represent a large number of values with onlytwo values and what is the tradeoff involved?Use several signals: n signals can represent 2n values.

This can increase the cost and complexity enormously.

VLSI to the rescue.

It is easier to deal with binary-valued signals if we keep thevoltage away from the single threshold.

If the observed voltage is > VH, call it a 1, High or True. If the observed voltage is < VL call it a 0, Low or False.

For TTL, a 1 is anything over 2v and a 0 is anything under 0.8v.

Vmax

Vmin

VH

VL

1

0

Unstable




Logic Conventions The use of 0 (F) and 1(T) must be associated with the H

and L voltages. It does not matter which way it is done.

If 1(T) is assigned to H and 0(F) to L we say we are using the positive logic convention.

If 0(F) is assigned to H and 1(T) to L we say we are using thenegative logic convention.

In this course we will use the positive logic convention unlessexplicitly indicated otherwise.




Exercise:The signal on a wire can vary between 0 and 10 volts.Circuits that use this signal can only determine voltagevalues to one digit of accuracy. That is, it will round theactual voltage to the nearest integer, so that any actualvoltage between 2.5v and 3.5v will be perceived as 3v.

Noise can alter the voltage on the wire by ±0.05v.Determine the number of possible discrete signal valuesand determine the voltage range associated with each of them.




2.2. Gates

Gate: A simple electronic circuit (a system) thatrealizes a logical operation.

The direction of information flow is from the inputterminals to the output terminal.

The number of input and output terminals is finite and they

carry binary-valued signals (i.e, 0 and 1). The transformation of input signals to output signals can be

modeled as a logical operation.

X

Y Z = f(X,Y)Gate




Truth Tables Since there is a finite number of input signal combinations,

we can represent the behavior of a gate by simply listing allof it possible input configurations and the correspondingoutput signal. Such a list is called a truth table.

For example, the following gate could have the behaviorgiven by the following truth tables.

The use of the symbols L and H usually correlates with thehigh and low voltages.

GATEX

Y

Z

X Y Z

L L L

L H H

H L H

H H H

X Y Z

0 0 0

0 1 1

1 0 1

1 1 1

X Y Z

1 1 1

1 0 0

0 1 0

0 0 0




Some standard gates and their symbols and truthtables:

X Z

0 01 1

X Z

a. Buffer

X Z

0 11 0

X Z

b. Inverter

X

YZ

X Y Z

0 0 00 1 01 0 01 1 1

c. AND Gate

X

YZ

X Y Z

0 0 00 1 11 0 11 1 1

d. OR Gate

X Y Z

0 0 10 1 1

1 0 11 1 0

or

e. NAND Gate

X

YZ

X

YZ

or

X Y Z

0 0 10 1 0

1 0 01 1 0

f. NOR Gate

X

YZ

X

YZ

X Y Z

0 0 00 1 11 0 11 1 0

g. Exclusive OR Gate

X

YZ

X Y Z0 0 10 1 01 0 0

1 1 1h. Equivalence Gate

X

YZ




Gates with more than 3 inputs:

AND gates: The output is 1 if and only if … ?

OR gates: The output is 1 if and only if … ?

NAND gates: The output is 0 if and only if … ?

NOR gates: The output is 0 if and only if … ?

EXCLUSIVE OR gates: The output is 1 if and only if … ?EQUIVALENCE gates: The output is 1 if and only if … ?




Logical Expressions We can also represent the behavior of gates with a logical

expressions constructed from variables and logicaloperations symbols.

The following table gives the most common ones.

C is 1 iff Both A and B are 1 or both A and B are 0.C = A≡BEQUIVALENCE

C is 1 iff It is not the case that either A or B is 1.C = A↓BNOR

C is 1 iff It is not the case that A and B are both 1.C = A↑BNAND

C is 1 iff A or B is 1, both not both.C = A⊕BEXCLUSIVE OR

C is 1 iff A is 1 or B is 1.C = A+BOR

C is 1 iff A is 1 and B is 1.C = A•BAND

C is 1 iff A is 0.C = A'NEGATION

MeaningExampleConnective




Comments on the logical symbols

The NAND and NOR symbols are not very useful. There are several different symbols that have been used for the logical

connectives.

Exercise:Determine how many different two-input gates there can be?

How many three-input gates?

N 2n

2 16

3 2564 65,536

5 4, 294,967,396

6 1.84 x 1019




2.3. Gate Networks

A gate network is a finite collection of interconnectedgates, network input terminals, and network outputterminals with the following restrictions: No gate output terminal or network input terminal is

connected to another gate output terminal or network inputterminal.

Every network output terminal or gate input terminal iswired (via one or more wires) to a constant value, anetwork input terminal, or a gate output terminal.

Example

NetworkInput

Terminals

NetworkOutputTerminals

A

B

C

X

Y




Types of networks

A combinational gate network is one in which the values of the signals

present on its input terminals uniquely determine the signal values at itsoutput terminals.

A gate network that is not combinational is called a sequential gatenetwork .

A loop in a gate network is a path that starts at a gate terminal, passesalong wires and through gates, does not pass any wire or gate morethan once, and terminates back at the starting gate terminal.

Networks without loops are combinational. We call a gate network without loops a logic network, since we can describe

its behavior with a logical expression.

Sequential networks have loops.

Combinational networks may have loops.

Loop




Exercise:Which of the following networks are combinational and

which are sequential?

Net 1Net 2

Net 3 Net 4




2.4. Analysis & Synthesis of Logic Networks

Overview

LogicNetwork

Truth

Table

Logical

Expression

1 2

3

4

5

67

AnalysisSynthesis

1. For a given logic network, find a truth table that describes its behavior.

2. For a given logic network, find a set of logical expressions that describes its behavior.

3. Transform a logical expression into the equivalent truth table representation.

4. Transform a truth table into an equivalent logical expression representation.

5. Transform a logical expression into an equivalent (and possibly simpler) logicalexpression.

6. Design a logic network to have the behavior specified by a given set of logical

expressions.

7. Design a logic network to have the behavior specified by a given truth table.




Analysis of Logic Networks Logic Network

Truth Table Behavioral DescriptionA B C Z1 Z2 Z3 Z4 X Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

6A

B

C

1 Z1

Z2

Z3

Z4

2

3

4

5

X

Y

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

1

0

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

0




Logical Expression Behavioral Description

6

A

B

C

1Z1

Z2

Z3

Z4

2

3

4

5

X

Y

X = Z4'

X = (Z1+Z2)'

X = ((A•B)'+(A⊕B))'

Y = Z2•Z3•Z4

Y = (A ⊕B)•(A•C)•(Z1+Z2)

Y = (A ⊕B)•(A•C)•((A•B)'+(A⊕B))




Example

X = A•B

Y = A•B'•C

The networks in these two examples are equivalent because they have the sametruth table. The logical expressions for X and Y are also equivalent, but verydifferent structurally.

A B C X Y

0 0 0 0 0

0 0 1 0 0

0 1 0 0 0

0 1 1 0 0

1 0 0 0 0

1 0 1 0 1

1 1 0 1 0

1 1 1 1 0

A

B

C

X

Y




Notation: We can represent a truth table by simply listingthe indices of the rows that have value 1 or listing thosethat have value 0.Example

List of 1’s:

X = Σ A,B,C (6, 7) Y = Σ A,B,C (5)

List of 0’s:

X = ΠA, B, C (0, 1, 2, 3, 4, 5) Y = Π A,B,C (0, 1, 2, 3, 4, 6, 7)

The value of this notation is that it is a more compact way of specifying a logical function than writing the truth table. It is usefulfor specifying a function to be designed (e.g., in homeworkproblems).

A B C X Y

0 0 0 0 0

0 0 1 0 0

0 1 0 0 0

0 1 1 0 0

1 0 0 0 0

1 0 1 0 1

1 1 0 1 0

1 1 1 1 0




Synthesis of Logic Networks Example

Z = (A ⊕ B) + ((C + D)•B')

+

⊕ •

+'

A B

C D B

(A⊕B) + ((C+D)•B')

ABC

D

Z

A⊕B

(C+D)•B'

AB

BCD

Z

A

B

C

D

B

Z

A

B

C+D

B'

C

D

B

Z




Example

X = ((Α ⊕ B) + C)'

Y = (B•C + D)'•EZ = (A + D) + (B•C)

ABC

DE

X

Y

Z

Original Network

AB

C

DE

X

Y

Z

First Simplification Second Simplification

AB

C

DE

X

Y

Z




Two level gate networks and logical expressions

Sum-of-Products (SOP) logical expressions

A•B + A•C’ + B•C’•A + C

Two level AND-OR Networks

Product-of-Sums (POS) logical expressions

(A+B’)•(B+C’)•A

Two level OR-AND Networks

A

B

CY

Y

A

B

C




2.5. NAND/NOR Networks

This topic deals with designing combinational logicnetworks using only NAND or NOR gates. Approach: First design the network with AND, OR and

NOT gates. Then Transform it to an equivalent network of NAND or NOR gates.

The following alternative NAND and NOR symbols are useful for

this.A

B(A•B)'

AB

A' + B'

A

B

A

B(A + B)' A' • B'




One approach is to replace AND and OR gates by thefollowing equivalent NAND or NOR circuits:

NAND Network Example:

A'

C'

B

D

A

D

Z

4

5

AND-OR Network

2

3

1

A

BA•B

A

BA+BNAND:

A

BA•B

A

BA+B

A

BA•BNOR:

A

BA+B

NAND Network

A'

C'

B

D

A

D

Z

4

5

2

3

1




NOR Network Example

Z

A

B

C

D

E'

AND-OR Network

A

B

CD

E'

Z

NOR Network




Algorithm 1: (Converts network N1 of inverters, AND gates,

OR gates, NAND gates, and NOR gates into network N2containing only NAND Gates)

Step 1.

a) Replace each AND gate symbol in the diagram of N1 by the symbolfor a NAND gate.

b) Replace each OR gate or NOR gate symbol in the diagram of N1 by the symbol for a NAND gate.

c) Replace all INVERTERS in the diagram of N1 by a direct connection.

Step 2.

a) Consider each connection (1) from a gate output to a gate input, (2) froma network input terminal to a gate input, or (3) from a gate outputterminal to a network output terminal, in the network produced by Step 1.

b) Insert enough INVERTERS in each of these connecting paths so that thenumber of inversion bubbles on gate inputs or outputs has the sameparity (i.e., odd or even) as the corresponding path in the originalnetwork N1.




Algorithm 2: (Converts network N1 of inverters,AND gates, OR gates, NAND gates, and NOR gates

into network N2 containing only NOR Gates)Step 1.

a) Replace each OR gate symbol in the diagram of N1 by the symbol fora NOR gate.

b) Replace each AND gate or NAND gate symbol in the diagram of N1 by the symbol for a NOR gate.

c) Replace all INVERTERS in the diagram of N1 by a direct connection.

Step 2.Same as for Algorithm 1.

Networks with NANDs and NORs The first steps of these previous two algorithms can be

easily combined to get an algorithm that produces anetwork containing both NAND and NOR gates.




Example of Transformation to a NAND Network:

A

B

C

Z

Original Network N1

6

1

2

3 4

5

A

B

C

Z

Intermediate Network After Step 1

1

2 3 4

56

NAND Network N2

A

B

C

Z6

1

2

34

5




Example of Transformation to a NAND and a NOR Network:

Z

A

C

B

D

Original Network N1

NAND Network N2

Z

A

C

B

D

NOR Network N2

Z

A

C

B

D




Exercise: Derive logical expressions, using only the logical

operations • , + and ', for the following two networks.

A B C D E

X

Net 1

A B C D E

X

Net 2




2.6. An Introduction to Verilog

Verilog is a programming language that was

developed for describing the behavior and structureof digital systems. Languages such as this are calledHardware Description Languages or HDL’s.

Verilog is an IEEE standard and widely used today.

Verilog is probably most useful for describing systems at ahigh-level of abstraction, before the implementation detailsof the systems are developed.

While HDL’s have been around for 30 years, it has only been withthe advent of large integrated circuits that they have becomepopular with digital designers.

Why?




Verilog Uses Verilog can be viewed as a simulation modeling language

Enables digital designers to simulate and verify the behavior of their systems before they design a detailed implementation.

Verification of functional behavior

Timing analysis

Verilog can also be used to specify test patterns for testing Verilogsimulation models. Verilog programs used for generating testpatterns are called test benches or test fixtures.

Verilog is also used to specify the input to synthesis toolsthat produce implementations automatically.

When this is possible, the designer need not use the classical design

techniques.




Verilog Modules An elementary Verilog program is called a module.

A module corresponds to a digital circuit.

Modules have input and output ports that correspond to the inputand output terminals of a digital circuit.

The ports and variables used to represent internal signals aredeclared at the beginning of the program.

Modules have other statements used to define how it transforms theinput signals to output signals.

Verilog modules can be used to specify the structure or thebehavior of a digital circuit.

Structural modules consist of a list of component modules (definedelsewhere) and a list of wires used to interconnect the modules.

Behavior modules specify the output signals as functions of theinput signals. They need not give any indication of the structure of the circuit.




Example of a behavioral Verilog module Circuit:

Verilog module:

module circuit1b (A, B, C, D, E, X, Y, Z);

input A, B, C, D, E;

output X, Y, Z;

assign X = ~((A ^ B) | C);

assign Y = ~((B & C) | D) & E;

assign Z = A | D | (B & C);

endmodule

ABC

X

D

Y

Z

E




Comments on the module

Case matters in Verilog statements.

The symbol string “Out”, “out”, and “OUT” represent three different variables.

Individual signals (e.g., A, B, … in the previous example) can takeany of the following four values:

0 = logic value 0

1 = logic value 1

z = tri-state (high impedance)

x = unknown value

The unknown value is used by simulators to indicate that they donot know how to determine a signals value (e.g., the user has notspecified a value for an input signal). The tri-state value means thatno signal is assigned to the variable.

Note that ports must be listed in the module statement (first line)and their direction (input or output) declared in the following

statements.




The three assign statements are independent and can execute in any

order or concurrently. The right side of an assign statement is evaluated and its resulting value

assigned to the signal on the left side whenever one of the signals used in theright side changes value.

This type of assignment is also called a continuous assignment .

This method of interpreting the execution of assign statements is quite differentfrom that use in conventional programming languages in the following ways:

Two or more assignments can execute simultaneously. This is necessary to representtiming characteristics of hardware systems.

An assignment executes whenever it is ready (i.e., has new data for the variables onits right side)

There is no concept of "locus of control" or “program counter” that determines thenext instruction to execute. Therefore, the order the assignments are written does notmatter

This method of assignment statement execution is sometimes callednon-procedural or data-driven execution, where conventionalprogramming languages are said to be procedural .




Behavioral vs. Structural Verilog Descriptions The previous example is a behavioral descriptions because

it specifies the logical values of the circuit's outputs aslogical equations with no reference to how the gates in apossible implementation might be interconnected.

It is also possible to specify a structural description inVerilog that specifies explicitly how a set of smallercomponents (e.g., gates) are interconnected to form a largersystem as shown on the following slide.Note that the internal connections from gate outputs to gate inputs

are declared to be of type wire.

These wire declarations could be omitted as long as the component modulesare simple gates. Verilog will assume that any gate output signal that is notdeclared is of type wire.

Each gate is specified by its name (e.g., and, or, …) and a list of ports or wires connected to its terminals. All gates have a singleoutput and it is always listed first in this list.




module circuit1s (A, B, C, D, E, X, Y, Z);input A, B, C, D, E;

output X, Y, Z;

wire T1, T2, T3, T4, T5, T6, T7;

xor(T1, A, B);

or(T2, T1, C);

not(X, T2);

and(T3, B, C);

or(T4, T3, D);

not(T5, T4);

and(Y, T5, E);

or(T6, A, D);

and(T7, B, C);

or(Z, T6, T7);

endmodule

ABC

X

D

Y

Z

E

T1 T2

T3 T4 T5

T6

T7




Always Blocks A procedural block is a construct that contains statements

that are executed procedurally (i.e., in the order they arewritten).

The sensitivity list is a list of signals separated by or.

When any one of the signals in the sensitivity list changes value,the always block wakes up, executes its procedural statements, andthe goes back to sleep.

The always block acts like a generalized assign statementwhere the action that takes place can be specified bysequential code.

always @(sensitivity_list )

begin

procedural statements

end




Example

module always_example(x, y, z);

input x, y;

output z;

reg z, s;

always @(x or y)

begin

s = x ^ y;

z = x & s;

end

endmodule




Variables declared as type reg hold their value until theyare assigned a new value. It is said that the assigned value

is registered in the variable Whenever x or y changes value, the always block is

executed as follows:

First, the statement s = x^y executes and registers a new value in s

Next, the statement z = x & s executes using the new value of s thatit received when the first statement was executed.

Then the blocks stops executing and waits for either x or y tochange again.

Variables on the left side of a procedural statement must bedeclared as type reg.

The main advantage of using always blocks to represent

combinational circuits is that you can use controlstatements such as “if then else” as illustrated by thefollowing example




Modules mux1 and mux2 do exactly the same thing. The control statements used in always blocks will be covered in

more detail in later chapters.

module mux1 (x1, x2, s, y);

input x1, x2, s;

output y;reg y;

always @(x1 or x2 or s)

if (s == 1)

y = x1;

elsey = x2;

endmodule

module mux2 (x1, x2, s, y);

input x1, x2, s;

output y;

assign y = (s & x1) | (~s & x2);

endmodule




Exercise: Explain how the behaviors of the following twomodules differ.

How would the behavior of each of these modules change if the order of the two assignment statements is reversed?

module always_example(x, y, z, f);

input x, y, z;

output f;

reg f, s;

always @(x or y or z)begin

s = x ^ y;

f = z & s;

end

endmodule

module assign_example (x, y, z, f);

input x, y, z;

output f;

wire s;

assign s = x ^ y;assign f = z & s;

endmodule




Conditions for combinational behavior of always blocks

The following conditions are necessary for an always block torepresent combinational logic (as opposed to sequential logic)

All reg, wire and input signals that appear on the right side of an assignmentstatement within the always block must appear in the sensitivity list

We call a sensitivity list that satisfies this condition a complete sensitivity list .

All signals in the sensitivity list must appear without edge specifiers

Edge specifiers indicate that a signal is asserted by a change in value as opposed to its level (e.g.,a rising edge or falling edge). They are introduced and utilized in later chapters on sequentialcircuits.

All output signals must be assigned a value every time the always blockexecutes

These conditions guarantee that the input signals uniquelydetermine the output signals, which is the very definition of acombinational circuit.

Some Verilog synthesizers (Including the one in the Xilinx ISE)assume that if you omit one or more of the signals in the sensitivity

list, that you really meant to put them in, so it does it for you.However, it will issue a warning message in this case.

A sensitivity list of the form @(*) is shorthand for a complete list.

It is recommended that you use this notation for combinational always blocks.




Example (Incomplete sensitivity list)module example1(a, b, c, f);

inputa, b, c;output f;

reg f;

always @(a, b)

if (a==1)

f = b;else

f = c;

endmodule

The input c is missing from the sensitivity list

According to the semantics of Verilog, this represents a sequential circuit.Why?

Xilinx ISE will assume you meant to put c in the sensitivity list and add it foryou, so a circuit it synthesizes from this module will be combinational.

It is better to always use complete sensitivity lists. The easiest way to do this isto replace @(a,b) by @(*).




Example (Missing output signal in a control path)

A control path is a sequence of operations (possibly null) that canbe performed by an always block. It corresponds to a path from the

input node to the output node of a flow chart of the block.

module example2(a, b, c, f);

input a, b, c;

output f;

reg f;

always @(*)

if (a==1)

f = b&c;

endmodule

If a is 0 and b or c changes value, the always block executes butdoes not execute an assignment to f, so f is not uniquely determinedby the static values of a, b, and c.

Xilinx ISE will synthesize this module as a sequential circuit.




2.9. Tips and Tricks

Think of the bubbles on gates as inverters

Thus is equivalent to Think of Exclusive Or and Equivalence as a parity circuits that

produce a 1 out if the number of 1's in is odd or evenrespectively.

Be aware that you can make an inverter from an Exclusive OR

Use the alternative NAND/NOR symbols to emphasize thelogical functions of the gates.

A two-level NAND-NAND network is equivalent to a two-level AND-OR network and both realize Sum-of-Productlogical expressions.

A two-level NOR-NOR network is equivalent to a two-levelOR-AND network and both realize Product-of-Sums logicalexpressions.




2.10. Pitfalls

Not realizing that is a NAND gate or is a

NOR gate and not using them where appropriate. Not using them is not logically incorrect, but it can

make logic diagram more difficult to read and lead toerrors.

Using the ↑ and ↓ for NAND and NOR

Again, they are not wrong, just not very useful.

Forgetting that case matters in Verilog names.

Forgetting that “assign” statements in Verilogare executed in parallel and are “data-driven.”

Forgetting to use complete sensitivity lists ormissing output signals in control paths.




2.11. Review

The nature of binary-valued signals and how theyrelate to continuous measured signal values (the 3ranges of 0, 1, and unstable). What are the advantage of binary-valued signals?

The relationship between logical networks, logical

expressions and truth tables. The relationship between combination networks,

sequential networks and loops in networks.

The alternative NAND and NOR symbols.

The use of Verilog to specify the behavior orstructure of simple combination logic networks

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