02 Whole

Chapter One Introduction -----------------------------------------------------------------------------

1.1 Underwater Acoustic Communications

Digital communication in an underwater channel differs from communications

through other media such as radio channels where data is transmitted by means of

electromagnetic waves. Acoustic waves have superior propagation characteristics in

water and are most commonly used for wireless transmission of signals under water.

The reason for not using radio waves in the underwater channel is that only extra low

frequency radio waves (30 Hz - 300 Hz) can be propagated at any significant

distances through conductive sea water. These extra low frequencies also require large

antennae and high transmission power [1]. Though optical waves do not suffer from

such high attenuation, they are affected by scattering, which severely limits their link

distance in turbid waters [2]. Moreover, for accurate transmission, they require high

precision in pointing the narrow laser beams. Hence, underwater networks are based

on acoustic wireless communications.

The growing interest of researchers in underwater acoustic communications broadens

the application domain from military to commercial purposes such as remote control

in the off-shore oil industry, collection of scientific data recorded at ocean-bottom

stations and pollution monitoring in environmental systems. To make these

applications viable, there is a need for a communication system at the submerged ends

of the underwater communication link to achieve reliable communication in both

point-to-point and network scenarios. Underwater acoustic links are adversely

Chapter One: Introduction

affected by physical phenomena such as ambient noise, frequency-dependent

attenuation, refraction due to temperature and pressure variations, and multipath [3]

which may result in Intersymbol Interference (ISI) and large Doppler shifts and

Doppler spreads relative to radio channels. These effects must be taken into account

in any successful communication system design.

Over the last few years, significant advances have been made in the development of

underwater acoustic communication systems in terms of their operational range and

the data throughput. With the development of efficient communication systems, the

scope of their applications continues to grow. This in turn implies that the system

throughput and performance need to grow. Both commercial and military applications

are now calling for real-time communication with submarines and autonomous

underwater vehicles (AUVs) in point-to-point as well as in network scenarios. This

demand moves current researchers towards the development of an efficient

communication technique, signal processing algorithm, modulation/demodulation

method, sophisticated coding schemes, multiple access protocols and other physical

layer techniques for underwater communication.

1.2 Motivation

The basic component needed to transmit and receive information via any

communication channel is a modem which means modulator and demodulator. The

modulator modulates an analog carrier signal to encode digital information. The

demodulator on the other hand, does the reverse work by extracting the original

digital transmitted information from the modulated carrier signal. Contemporary

underwater acoustic networks use low frequency modems and support long range

communication on each link. But the low operating frequency limits the available

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channel bandwidth and hence the symbol rate. So, only low data rate communication

can be achieved with these modems.

Underwater communications are mostly characterized by low frequency signals to

minimize absorption. The low data rate can be improved by increasing signal

bandwidth, but requires a higher carrier frequency. Although higher frequencies result

in a higher absorption rate, this can be countered by keeping the link distance short

and forwarding data over numerous relatively short paths using a multi-hop technique.

The total power lost due to absorption is also minimized using short hops/links which

in turn provides relatively high data rate communications with modest power

consumption [4]. Thus, for short range communications, high frequency channels can

provide a larger channel bandwidth and offer high signal quality [5]. Short link ranges

are suitable for certain tasks [6, 7], or can be used as the last link in a cellular access

system with backhaul [8]. Moreover, long range communication can be achieved by

using multiple short range links via multi-hop [9].

To support high data rate transmission, sophisticated digital modulation methods have

been adopted for radio communication. Accomplishing the same data rate for

underwater communication is impractical, however, due to channel properties and

bandwidth limitations. So far, underwater communication systems have mostly relied

on non-coherent modulation and signalling techniques to deal with the time-varying

multipath problem. But these techniques provide low data rates. More recently,

coherent modulation techniques, namely Phase Shift Keying (PSK) [10], have been

shown to provide a feasible means for achieving increased throughput by using the

underwater acoustic bandwidth more efficiently.

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Reconfigurability [11] is another issue in system design. It provides the advantage of

allowing system changes with little or no hardware modification. Reconfigurable

computing has been driven largely by the development of Field Programmable Gate

Array (FPGA). Designing digital signal processing algorithms in FPGA avoids high

production cost, provides flexibility, adaptability with optimal power consumption.

Existing underwater modems are mostly Digital Signal Processor (DSP) based, but

recent development of FPGA opens the door to take the advantage of

reconfigurability in digital system applications and directs researchers towards

reconfigurable computing. The reconfigurable FPGA can eliminate some of the

dedicated hardware in a modem, as well as provide faster processing than is available

in a DSP.

Most of the existing underwater modems are developed with custom hardware, which

is expensive. It increases the cost of deploying the network. But designing modulation

and demodulation, as well as supporting functions, in software provides the flexibility

to change the system design using only software at low cost by leaving the hardware

unchanged. Since designing a high frequency, software defined and reconfigurable

modem is still an open research area, this dissertation mainly focuses on this issue and

proposes a method to deal with it.

1.3 Aims and Objectives

The high frequency channels are suitable for high data-rate, short-range

communications under water. But most existing works in underwater communications

concentrate on longer path and low frequency communications and hence the high

frequency channel is poorly documented. Many of the channel effects that degrade

signal quality in low frequency, long range channels may not be as severe [5] in the

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high frequency, short range channel, potentially simplifying the equalisation task.

This moves our research towards the use of simple Binary Phase Shift Keying

(BPSK) modulation scheme which achieves better performance in presence of error

for communications under water.

The main goal of this thesis is to document the design of a “High Frequency FPGA

Acoustic BPSK Modem” which takes advantage of the reconfigurability of FPGAs.

Our work is targeted to operate at high frequency with the proper utilization of

available underwater bandwidth. The high frequency feature also implies that our

modem is suitable for high data rate applications. This software defined modem

avoids expensive hardware cost and makes reprogramming easier. Our secondary

objective is to design the modem so that it optimizes FPGA resource consumption.

1.4 Overview

This thesis proposes a “High Data-Rate, Software-Defined FPGA Modem” for

underwater acoustic communications. The main attractions of the modem are that it

supports high frequency, offers high data-rate and is implemented entirely in FPGA.

This differs from most existing modems which are based on DSP processors and

support relatively low data rates. Being software defined, the modem provides

flexibility since the parameters can be reconfigured with relatively less effort,

minimising the modification cost as the design evolves.

The modulator and demodulator have been implemented in the FPGA. The modulator

uses a root raised cosine pulse shaping filter [12] to reduce Intersymbol Interference.

The filters are implemented in FPGA as a 101 tap symmetric Finite Impulse Response

(FIR) filters, with filter weights implemented by a series of right shift and addition

operations. This avoids the use of multipliers and substantially reduces FPGA

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resource consumption. The modem uses three such root raised cosine filters (one at

the transmitter and two at the receiver), all of which are implemented by the right shift

and addition techniques to avoid expensive multiplication operations in the FPGA.

The demodulator is implemented using a Costas loop [13] which is a method of

carrier acquisition and synchronous data demodulations within the loop. Our modem

is designed to operate at frequency of 800 kHz and to support a raw data rate of 80

kbps. Testing of the modem is carried out in the laboratory, tank and open water and

results are matched with the Matlab model.

1.5 Outline of the Thesis

This thesis report covers the design and implementation of a high frequency FPGA

modem for underwater acoustic sensor networks. This introductory chapter presents

the motivation behind the research program. It also states the goals, and provides a

brief overview of the thesis. It also considers some general topics that provide the

context for the rest of the chapters in this dissertation. Chapter 2 provides the basics of

communication and some definitions related to the work described in the thesis.

Chapter 3 outlines some properties of underwater acoustic networks and discusses the

challenges of communications in underwater channel. Some popular existing modems

currently used under water are also discussed in this chapter. Chapter 4 gives the

detailed description of the proposed design of our “High Frequency FPGA Acoustic

Modem” for underwater communication. The detailed design of the modulator and

the demodulator is discussed in this chapter. Chapter 5 introduces the FPGA design

tool used - Altium Winter 09 and all the other necessary tools to implement the

proposed modem in FPGA. Chapter 5 also analyzes the performance of the modem

both in laboratory and in open water. Finally, Chapter 6 concludes the thesis with a

capsule summary and describes plans for future work.

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Chapter Two Fundamentals of Digital Communication -----------------------------------------------------------------------------

2.1 Introduction

This chapter describes fundamentals of digital communications that are relied upon in

later chapters. The first part of the chapter describes some common digital modulation

and demodulation techniques. The need for synchronization in digital

communications will then be discussed in detail in the second part. Finally, a short

description about some communication terms related to this thesis work concludes the

chapter.

2.2 Digital Communication

The main purpose of any communication system is to transfer information. Digital

communication is the process of transferring digital data physically over a

communication channel [14]. This type of communication is becoming increasingly

attractive because it offers data processing options and supports features such as data

integrity, capacity utilization, security, privacy etc. The digital communication system

conveys discrete messages through a communication channel such as copper wires,

optical fibers, wireless communication channels etc. The data transmitted by a digital

communication system is either digital data originating from a source such as a

computer or it can be an analog signal such as a phone call or video signal, that is

digitized into a bit stream before transmission. Figure 2.1 shows the general structure

of a digital communication system.

Chapter Two: Fundamentals of Digital Communication

Figure 2.1: Block Diagram of a Digital Communication System

The source encoder converts the output of a digital or analog source into a sequence

of binary digits. The sequence of binary digits from the source encoder is passed to

the channel encoder which is used to add redundancy to the transmitted signal so that

errors caused by noise and interference during transmission can be corrected at the

receiver. The added redundancy in the binary information sequence increases the

reliability of the received data and helps the receiver to decode the desired

information sequence. A well designed channel encoder uses a code which transmits

quickly, contains many valid code words and involves the removal of redundancy and

the correction (or detection) of errors in the transmitted data. For example, channel

encoding is performed by inserting constant bits (code word) into the bit stream at

particular positions with a value known to both the sender and the receiver. The

channel decoder recovers the original information by removing the known code word.

A simple encoding technique is to repeat each binary digit k times, where k is a

positive integer. For example, the encoder sends ‘000’ instead of sending only one ‘0’

to the communication channel. Due to noise or interference, the received bits can be

‘001’ or ‘010’. By majority logic of decoding, the decoder detects it as ‘000’ and

decodes it as ‘0’ having been sent.

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The digital modulator maps the digital bit sequence into signal waveforms for

transmission. The communication channel is the physical medium used to send the

signal from the transmitter to the receiver. The transmitted signal can be impaired by

noise, interference, and distortions before it reaches the receiver.

The receiver/demodulator processes the channel affected transmitted waveform and

estimates the transmitted data symbols. The channel decoder at the receiving end then

reconstructs the original information sequence from knowledge of the code used by

the channel encoder. The source decoder receives the output sequence from the

channel decoder and attempts to reconstruct the original signal from the source using

knowledge of the source-encoding method used.

Not all of the functions in the Figure 2.1 are required in every digital communication

system. The primary components of any digital communication system are the

Modulator, Demodulator and Synchronizer. This work focuses on these three

components. The following sections will discuss these components as well as some

related metrics used to analyze the performance of digital communication.

2.3 Modulation and Demodulation

Modulation is the process of changing one or more properties of a high frequency

periodic waveform with a modulating signal which typically contains information to

be transmitted. The high frequency periodic waveform is called the carrier signal.

Demodulation does the inverse operation by extracting the original information from

the modulated carrier wave [15]. Digital modulation transfers a digital bit stream over

an analog communication channel. Figure 2.2 shows the block diagram of a typical

digital modem. The digital signal, m(t) is called the modulating signal or baseband

signal. The modulator modulates the carrier signal to encode the digital information.

9


The result coming out of the modulator after modulating the carrier is the modulated

signal, s(t). As shown in Figure 2.2, s(t) is a band limited (bandpass) signal which is

fed to the demodulator. The demodulator decodes the signal to recover the original

information.

Figure 2.2: Block Diagram of a Digital Modem [14]

Modulation involves operation on one or more of the three characteristics of a carrier

signal: amplitude, frequency and phase. Any digital modulation scheme uses a finite

number of distinct signals to represent digital data. The basic modulation techniques

used to transform digital data into analog signals are [10, 15, 16]:

Amplitude Shift Keying (ASK)

Frequency Shift Keying (FSK)

Phase Shift Keying (PSK)

2.3.1 Amplitude Shift Keying (ASK)

In ASK, digital data bits are transmitted by changing the amplitude of a carrier wave.

The simplest ASK is On-Off Keying (OOK) where two different amplitude of the

carrier frequency are used to represent two binary values. Generally, one binary digit

is represented by the presence of the carrier whereas the other by the absence of the

carrier. If the carrier signal is ),2cos( tfA cπ the resulting OOK modulated signal is:

⎩⎨⎧

=0Binary 01Binary )2cos(

)(tfA

tx cπ

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Both ASK modulation and demodulation are very inexpensive to implement. ASK is,

however, susceptible to sudden gain changes and demonstrates poor performance as it

is sensitive to atmospheric noise, distortions, propagation conditions. Hence, this

modulation scheme is inefficient in wireless channels. Also the transmitter duty cycle

is 50%, therefore the amplifier needs twice the power in this modulation technique to

get the same energy per bit as other methods. But ASK is commonly used for

transmitting digital data over an optical fiber. Optical fiber systems are not affected by

external electromagnetic fields and thus the system is not vulnerable to interference,

impulse noise, or cross talk [15]. This is the reason why ASK is used in optical fiber

communication. For an LED transmitter, one signal element is represented by the

presence of light pulse while the other signal element is represented by the absence of

light. Laser transmitters normally have a fixed "bias" current that causes the device to

emit a low light level. This low level represents one signal element, while a higher-

amplitude light wave represents another signal element.

2.3.2 Frequency Shift Keying (FSK)

In FSK, different frequencies of a carrier wave are used to represent distinct binary

values. The simplest FSK is binary FSK (BFSK) where the frequencies are equally

offset from the carrier frequency by opposite amounts. The resulting FSK modulated

signal is:

⎩⎨⎧

=0Binary )2cos(1Binary )2cos(

)(2

1

tfAtfA

txππ

Here, 21 fff c ∆+= and 22 fff c ∆−= are two offsets from the carrier

frequency . cf

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FSK is less prone to error than ASK because it avoids noise interference by looking at

frequencies (change of signal) and ignoring amplitude. The peak amplitude and phase

of the carrier signal remain constant in this system. FSK is commonly used for high

frequency (3 to 30 MHz) radio transmission. It is almost universally used for low-

speed modems. This system is relatively easy to implement. FSK can be expanded to

an M-ary scheme called Multiple FSK (MFSK), a variation of FSK that uses more

than two frequencies. FSK systems use more bandwidth because more frequencies are

needed to carry more bits.

2.3.3 Phase Shift Keying (PSK)

In PSK, the phase of the carrier is shifted to represent digital data. Each pattern of the

binary digits (called a symbol) is represented by a particular phase. The demodulator

on the other hand recovers the original data by determining the phase of the received

signal and maps it back to the symbol it represents. This requires the receiver to use

coherent PSK (CPSK) which compares the phase of the received signal to the

reference one.

Binary Phase Shift Keying (BPSK) [17, 18] is the simplest form of PSK where two

phases separated by 180o are needed to represent two binary data states. The resulting

modulated BPSK signal is:

⎩⎨⎧ +

=0Binary )2cos(1Binary )2cos(

)(tfAtfA

txc

c

πππ

Here is the frequency of the carrier signal. cf

Differential Phase Shift Keying (DPSK) [15] is one variation of PSK where the

phase of the carrier is changed by a specific amount to represent distinct bit patterns.

The demodulator then determines the changes in the phase of the received signal

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rather than the phase itself. It is termed DPSK since it depends on the difference

between successive phases.

In Quadrature Phase Shift Keying (QPSK) [17, 18], the amount of phase distance

between adjacent symbols is 2π (90o). Each signal element is represented by two bits

in this scheme.

There are also other forms of PSK where multiple bits can be transmitted in a signal

element - 3 bits for 8-PSK and 4 bits for 16-PSK. Within a given bandwidth, the

higher order forms of modulation allow higher data rates to be carried. However, the

higher data rates require a better signal-to-noise ratio to maintain acceptable error

rates, which makes such modulation techniques energy inefficient. The choice of

appropriate modulation scheme depends on the exact requirements of the particular

scenario under consideration.

2.4 Channel Capacity

There are various effects that corrupt or distort the signal during transmission through

the channel. Channel capacity is the maximum rate at which information can be

reliably transmitted over a given communication channel [15, 19]. In noisy channels,

the channel capacity is the maximum information throughput achieved after

accounting for errors.

The following four related factors need to be considered for successful digital

communication:

Data Rate: This is the rate at which data can be transmitted over a

communication channel [15, 18]. This is also known as bit rate. The data rate

is expressed in bits per second (bps). The bit rate can be calculated as

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0tnR = , where n is the number of bits sent in seconds. 0t

This is the raw rate at which data is modulated on the channel. The throughput

will be lower than this in any practical communication system.

Bandwidth: In digital communication, bandwidth is the difference between

the highest and lowest frequency signal components, and is expressed in

cycles per second or hertz [14]. The bandwidth of the received signal is

constrained by the transmitter and the nature of the transmission medium.

Noise: Signals transmitted along the communication path are corrupted by

several impairments, such as noise, distortion etc. Noise can be defined as an

unwanted signal that degrades the quality of transmitted signals [15]. Noise

interferes with the communication, measurement or processing of an

information-bearing signal. An example of noise in underwater domain is the

broadband noise generated by snapping shrimp. Signal distortion on the other

hand, is the alteration of the original shape (or other characteristic) of a signal

waveform, due to non-ideal characteristics of the transmission channel,

reverberations, echo and missing samples [20]. On propagation through a

channel, signals can be distorted by the frequency response and the attenuating

characteristics of the channel. One of the causes of signal distortion is the

multipath effect (discussed further in Section 2.7), in which the transmitted

signal takes several different routes to reach the receiver. Each signal

component has its own propagation speed through the medium and reaches the

final destination with its own delay and attenuation. Noise and distortion are

the main limiting factors in communication and measurement systems. Noise

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reduction and distortion removal are thus important factors in modern

telecommunications and signal processing applications.

Error Rate: Transmitting information to the receiver with as little

deterioration as possible is one of the major goals of designing digital

communication systems. The error rate is the rate at which errors occur in the

decoded data [15, 18]. This is normally expressed as bit error rate, being the

probability of each bit being in error.

The main target of any digital communication is to achieve as high a data rate as

possible for a given limited bandwidth considering the error rate. But noise and

distortion are the main limitation for achieving this efficiency.

2.5 Signal-to-Noise Ratio (SNR)

For determining digital data rates and error rate, Eb/N0 is an important parameter in

digital communication, which is the ratio of signal energy per bit to noise power

density per hertz. Energy per bit (Eb) is defined as the ratio of signal power to bit rate,

RSEb = , where is the signal power (watts = joules/sec) andS R is the data rate

(bits/sec).

The bit rate can be expressed in terms of the bandwidth efficiency b ((bits / sec) / Hz)

and bandwidth W (Hz) required for the signal as

WbR *= [bits/sec]

The ratio of data rate R , to transmission bandwidth W , is referred to as the bandwidth

efficiency b .

Therefore, if the signal power is S,

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( ) *WbSEb = [joules/bit]

If the noise power density is [watts/Hz = joules], then noise power in a signal with

bandwidth W [Hz = 1/sec] is,

0N

WNN *0= [joules/sec = watts]

Thus, 0NEb can be defined as,

( ) ( ) ( )RWNSbSNRNWbSNE b */ ** 00 ===

Thus, Signal-to-Noise Ratio (SNR) is related to 0NEb as,

( )WRNESNR b *0=

As the bit rate R increases, the transmitted signal power, relative to noise, must

increase to maintain the required .0NEb

SNR [15] is thus a measure of signal strength relative to the background noise in

digital communications. If the signal power is denoted by and the noise power

by , the signal-to-noise ratio is

signalP

noiseP

noisesignal PPSNR =

SNRs are often expressed using the logarithmic decibel scale since many signals have

a very wide dynamic range. In decibels, the SNR is defined as

( )noisesignaldBPPSNR log 10

10=

Signal-to-noise ratio is one of the important factors to decide how successful the

receiver will be in decoding the original signal. The estimated SNR can be employed

in soft decoding procedures; transmit power control, and handover. In a phase-

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modulated communication link, a signal must prevail against such environmental

noise as weather interference, source-receiver misalignment, and transmission power

loss to achieve the clearest digital signal. An accurate assessment of the signal-to-

noise ratio (SNR) enables the sender to adjust the transmission power to ensure that

the communication can be completed successfully without using excess energy.

2.6 Synchronization

One of the basic requirements of all digital communication systems is to use some

form of synchronization at the receiver for correct decoding of the incoming signal.

Most receivers require synchronization to carrier frequency and phase, and symbol

timing of the received signal. The demodulation is also done after phase lock is

achieved.

2.6.1 Phase Synchronization using PLL

Phase estimation of the communication channel is a mandatory requirement for

correctly receiving a coherent modulation scheme. The receiver needs to generate a

set of reference signals whose phases are almost identical to the phases of the

oscillator used to create the incoming signal. In other words, there has to be phase

synchronization between the carrier of the incoming signal and the local oscillator at

the receiver [14]. Phase lock is defined as a condition when the receiver’s phase is

close enough to that of the carrier of the incoming signal for accurate

demodulation/decoding at the receiver. The process of estimating the carrier phase is

known as carrier phase synchronization and can be accomplished by a phase-locked

loop (PLL) circuit. The aim of frequency synchronization is to recover the carrier

frequency of the received signal. There is a mandatory requirement for phase

synchronization.

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A PLL [14, 19, 21] is a closed-loop feedback control system which generates a signal

synchronized to the phase of an input reference signal. The PLL responds to the phase

of the incoming input signals by raising or lowering the frequency of a controlled

oscillator until it is closely matched to the reference one in phase. The phase

synchronization is achieved by generating a reference carrier with phase closely

matched with that of the incoming signal. The receiver uses this carrier to perform a

coherent demodulation. Figure 2.3 shows a basic schematic diagram of a PLL. It has

three basic components: phase detector, a loop filter and a controlled oscillator (CO).

Figure 2.3: Schematic of the Basic PLL [13]

The main component of a PLL is phase detector which measures the phase difference

between the incoming signal and the reference signal generated in the PLL [21]. The

output of the phase detector is proportional to the phase difference between the two

input signals. This output, the phase error, is time varying as the incoming signal and

the local carrier estimate at the receiver change with respect to each other. If the two

input signals differ in frequency, the output of the phase detector is a periodic wave

with frequency of the difference in frequency of the two signals. If the incoming

signal is not equal to the output signal of CO, the phase error signal causes the CO

phase to deviate towards the phase of incoming signal.

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The PLL is a feedback control system which controls the phase of the CO. The CO is

a sinusoidal oscillator which produces the local reference carrier [22]. The filtered

version of the phase error is fed back to the input of the CO and phase lock is

achieved. The loop filter is designed to match the characteristics required by the

application of the PLL.

The PLL is used to facilitate the signal synchronization between a transmitter and a

receiver, which ensures that the local oscillator and the remote oscillator have the

same or a related phase. The CO produces the output signal of the PLL. The various

components of the PLL cooperate with each other to cause this output signal to tend

toward and eventually lock on to a desired output phase/frequency, which are based

on a reference signal applied as an input to the phase detector. The loop filter used in

the PLL often is a low-pass filter (LPF) which is arranged to provide a smoothed or

averaged control signal in response to the raw control signal. The CO is arranged to

receive the control signal from the loop filter.

Phase-locked loop circuits are used for a variety of purposes, including signal

demodulation, frequency synthesis, pulse synchronization of signals from mass

storage devices, and regeneration of signals. In the locked condition, any slight

change in the input signal first appears as a change in phase between the input signal

and the oscillator frequency. This phase shift acts as an error signal to change the

frequency of the local PLL oscillator to match the change in the input signal. A PLL

compares the phase difference between a reference clock signal and a feedback clock

signal and adjusts the frequency of the feedback clock signal to synchronize the clock

signals. The frequency of the feedback clock signal locks to the frequency of the

reference clock signal.

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PLLs are being implemented more and more in the digital domain and all the

components of the PLL need to be converted to discrete-time systems for

implementing a digital PLL. The digital version of a CO is called Numerically

Controlled Oscillator (NCO) [23, 24]. The most common technique for implementing

an NCO is based on the look-up table (LUT) [25]. The LUT is used to store the

sample values of a sinusoid signal, which are read out at appropriate time intervals to

produce the sinusoid signal.

Figure 2.4 shows the basic structure of an NCO based on LUT. A NCO generally

consists of two parts:

A Phase Accumulator (PA): consists of N-bit binary adder and a phase

register. At every clock pulse, a new output (N-bit) is generated consisting of

the previous output obtained from the register summed with the current phase

increment which is a constant for a given output frequency. Only the L most

significant bits (MSB) out of the N-bit accumulator output represent the phase

and are used to address the LUT, which converts the phase into the

corresponding sine amplitude. The phase increment determines the amount of

phase change in the output signal during each clock period.

Sine LUT: This is a phase to amplitude converter which uses the phase

accumulator output as an index into LUT to provide a corresponding

amplitude sample.

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Figure 2.4: Block Diagram of LUT based NCO (Dotted Rectangle is the PA)

The carrier recovery circuit is used to estimate and compensate the phase difference

between the received signal’s carrier and local oscillator at the receiver for the

purpose of coherent demodulation. The most common carrier recovery PLL circuits

are the Squaring loop and the Costas loop [14]. The Squaring loop is a feed-forward

method, whereas the Costas loop relies on feedback technique related to the PLL [26].

The design of the Costas loop eliminates the square-law device used in the Squaring

loop, which can be difficult to implement at carrier frequencies and replaces it with a

multiplier and relatively simple low-pass filters [14]. A demodulator extracts the

original information bearing signal from the modulated carrier wave. In addition to

carrier recovery, the Costas loop demodulates the incoming BPSK signal. A detailed

discussion about the Costas loop is presented in Chapter 4.

2.6.2 Symbol Synchronization

Symbol synchronization is required in every communication system that transmits

information synchronously. This is also known as timing recovery. To perform

demodulation, the receiver has to know the start and stop time of each individual

signal. The output of the demodulator must be sampled periodically at the symbol

rate. In order to achieve optimal demodulation, all receivers need to have their

21


demodulators synchronized to the incoming digital symbol transitions. This concept is

similar to phase synchronization in the sense that the receivers involve producing the

replica of the transmitted signal. A receiver which is able to produce a square wave

that makes transition through zero simultaneously with the incoming signal’s

transitions between two consecutive symbols is said to have symbol synchronization

or to be symbol locked with the transmitter [14].

2.7 Doppler Effect, ISI and Multipath

The Doppler Effect [27] can be explained as an effect caused by moving a source of

the waves in which there is an apparent upward shift in frequency for observers

towards whom the source is approaching and an apparent downward shift in

frequency for observers from whom the source is receding. There is not an actual

change in the frequency of the source; the effect is observed because the distance

between the observer and the source is increasing or decreasing. For example, when a

police car or emergency vehicle travels towards the observer on the highway, the

pitch of the siren sound (a measure of the siren's frequency) is heard at high pitch by

the observer as the car approaches with its siren blasting, and as the car moves away,

the sound of its siren is heard at low pitch by the observer. This is the Doppler effect -

an apparent shift in frequency for a sound wave produced by a moving source. The

Doppler effect can be observed for any type of wave including water waves, sound

waves, light waves.

Intersymbol Interference (ISI) [10, 19] is one type of signal distortion in which one

symbol interferes with subsequent symbols. It introduces errors in the decision logic

at the receiver and makes the communication less reliable. The ISI is caused by

multipath propagation and by transmitting a signal through a band limited channel.

22


Multipath [19] is a propagation characteristic in which the transmitting signal reaches

the receiver by multiple paths. This is due to the reflection - a signal may bounce off

buildings or the water surface, refraction – through atmospheric effects and variation

in the water column, atmospheric ducting and ionospheric reflection. All of these

paths have different lengths and some of these effects also slow down the signal

transmission. This results in different versions of the same transmitter signal arriving

at the receiver at different times. The multipath problem can introduce errors and

affects the quality of the digital communications.

Transmission of a signal at high modulation rate through a band limited channel -

where the frequency is zero above the cut off frequency, also causes ISI to be

introduced. When a signal is transmitted through a band limited channel, the

frequency components outside the channel limits are removed from the signal, so the

shape of the transmitted signals are also affected at the receiver. For each symbol, it

changes the shape of one symbol and also spreads it out over the subsequent symbol

periods. At the receiver, the spread pulse of one symbol interferes with the following

symbols.

2.8 Pulse Shaping

In wireless communication channel, two important requirements - transmit data over

band limited channels to avoid interference caused by the bandwidth limitation and

reducing Intersymbol Interference from multipath signal reflection, demand the need

for pulse shaping. These requirements can be fulfilled by applying a pulse shaping

filter to each symbol [10, 28]. The transmitted symbols are represented as a time

sequence of dirac delta pulses and are then filtered using a pulse shaping filter to

23


produce transmitted signals. The pulse shaping filter at the transmitter determines the

signal’s spectrum.

In addition to the pulse shaping filter, it is common to apply a matched filter on the

receiver side to maximize SNR. The pulse shaping filter generates signals such that

each symbol has no effect at other symbols and the matched filter filters out the signal

reflections presented in the transmission process. The signal transmitted through the

direct path arrives at the receiver before the reflected signals and this causes reflected

signals to overlap with subsequent symbol periods. This effect can be reduced by

using a matched filter at the receiver which attenuates the starting and ending portions

of the symbol period and hence reduces ISI. These portions are much susceptible to

create ISI.

Raised Cosine Filter [29] is a commonly used pulse shaping filter in digital

communications for minimizing ISI. This filter is typically split evenly between the

transmitter and receiver. This achieves the dual purpose of pulse shaping and matched

filtering. The Root Raised Cosine Filter (RRC) [30], also known as Square Root

Raised Cosine Filter (SRRC), is commonly used in communications systems in pairs

- where the transmitter first applies a root raised cosine filter, and the receiver then

applies it as a matched filter.

2.9 Performance Measurement of Communication System

To facilitate the design and evaluation of communication systems, we need to

establish a measure of performance. For a digital communication system, a common

performance measure is the probability that an error occurs at the receiver for each bit.

24


The Bit Error Rate or Bit Error Ratio (BER) [15] is the number of bit errors (bits

altered due to noise, interference, distortion etc.) divided by the total number of bits

transferred over a communication channel during a studied time interval.

BER can be used at the output of the demodulator for measuring the performance of a

digital communication system. For example, assume that the total number of bits

transmitted over a communication channel is 10 and the number of bit errors is 3, then

the BER is 3/10 or 0.3 or 30%. BER is inversely related to SNR. An increase in SNR

decreases the BER for any given modulation scheme. For digital communication,

BER is an important parameter. BER can be reduced by increasing the value of Eb/N0.

2.10 Summary

This chapter has introduced digital communication and has also explained the role of

the modulator and demodulator in digital communication systems. Some common

modulation schemes used in digital communication have been listed in this chapter.

The need for synchronization and the fundamentals of various levels of receiver

synchronizations are also summarized here. This chapter also presented some general

terms required to estimate the efficiency of digital data transmission. The following

chapter will introduce underwater acoustic network along with some modulation

schemes used for data transmission in the underwater environment. The next chapter

also gives the categorization of some existing modems and their suitability for use

under water.

25

Chapter Three Underwater Acoustic Communications -----------------------------------------------------------------------------

3.1 Introduction

This chapter introduces different categories of ad-hoc networks along with their

properties followed by some modulation schemes used in underwater networks. This

is important because an underwater acoustic network is a special type of wireless ad-

hoc network and designing a new modem for underwater communication requires

knowing more about the existing modulation techniques used in this type of network.

A general discussion about some existing approaches towards underwater modem

design is covered in this chapter. The rest of the chapter is organized as follows. The

next three sections will discuss the definition and characteristics of ad-hoc networks,

wireless sensor networks and underwater acoustic networks. The requirements for

modulation systems in underwater communication will then be listed and compared

with the potential solutions. The chapter reviews some existing modems and their

suitability for high data rate underwater applications. The chapter will be concluded

with a discussion of the requirement for design of a high frequency underwater

acoustic modem.

3.2 Mobile Ad-hoc Networks

Ad-hoc networks are a recently developed field in wireless communications. This

type of temporary network is formed by a collection of wireless mobile hosts without

the need for any stand-alone infrastructure or centralized administration and hence in

the category of infrastructure-less wireless network. The difference to traditional

Chapter Three: Underwater Acoustic Communications

infrastructure wireless networks is that there is no need for established infrastructure

in an ad-hoc network. Since there is no such infrastructure and therefore no

preinstalled routers available to forward packets from one host to another, the routing

task has to be taken over by participants, also called nodes of the network. All nodes

in the network are equal in role, as no client or server relationship exists among them.

All nodes can operate both as a host and as a router.

Mobile Ad-hoc Networks (MANETs) are self-organizing and self-configuring multi-

hop wireless networks where the structure of the network changes dynamically, for

example due to the node mobility [31, 32]. Nodes in these networks utilize the same

random access wireless channel, cooperating with each other to forward messages in a

multi-hop fashion. In contrast to a fixed wireless infrastructure network, a mobile ad-

hoc network can be deployed in remote geographical locations and requires minimal

setup and administration costs. In addition, the coverage area and application domain

of the ad-hoc network can be increased by integrating an ad-hoc network with a

bigger network, such as the Internet or a wireless infrastructure network. The major

application areas of ad-hoc networks are: Battlefield, Conferencing, Home

Networking, Emergency Services, Personal Area Networks and Bluetooth [32].

As an example of a small ad-hoc network, consider Figure 3.1 (redrawn from [33])

illustrating a collection of 8 nodes, along with the links among them. Nodes are able

to move relative to each other and some links among the nodes are broken and other

links are established. The node MH1 moves away from MH2 and establishes new links

with MH7 and MH8.

27


Figure 3.1: An Ad-hoc Network of Mobile Nodes

A mobile ad-hoc network has similar pros and cons to wireless network. The

advantages of wireless multi-hop networks are given below:

• The wireless network is easy and fast to set up and it eliminates the need for

cables.

• This network can be extended to places where it is difficult to provide wired

connections.

• Wireless networks are more flexible and can adapt easily to changes of

network configuration.

• The network can be extended to any node within its communication range of

any node in the network.

The disadvantages of these networks are given below:

• This network is sensitive to the interference occurred due to weather, other

radio frequency devices, or obstacles like walls, or the acoustic equivalent in

the underwater domain.

• When multiple connections exist; total throughput of the network is affected.

• The power of the devices in wireless network is limited compared to those of

wired networks.

• Communication in wireless networks face problems like multipath

propagation, path loss [34, 35], interference, and limited frequency spectrum.

3.3 Wireless Sensor Networks

Computing devices have become cheaper, more mobile, more distributed and more

pervasive in daily life with the popularity of laptops, PDAs, cell phones, GPS devices

28


and intelligent electronics. Using commercial off-the-shelf (COTS) components, it is

now possible to construct a wallet size embedded system with the equivalent

capability of a 1990's PC. These embedded systems can be supported with scaled

down Windows or Linux operating systems. This leads to the emergence of wireless

sensor networks, which is essentially the latest trend towards the miniaturization and

ubiquity of computing devices.

A Wireless Sensor Network (WSN) consists of spatially distributed autonomous low-

cost, low-power, multifunctional sensor nodes that are small in size and communicate

only over short distances. These tiny sensor nodes, which consist of sensing, data

processing, and communicating components, make the idea of sensor networks

practical, to cooperatively monitor physical or environmental conditions, such as

temperature, sound, vibration, pressure, motion or pollutants [36]. The position of

sensor nodes in the network need not be engineered or pre-determined.

In WSN, sensor nodes are capable of monitoring their neighbours in the network and

reporting observations to the node (called a sink) where sensed data is finally gathered

and processed. Sensor nodes are able to carry out simple computations locally using

their processing abilities and transmit only the required and partially processed data to

the sink node. This may reduce communication requirements as well as eliminating

the requirement for a central processing node. Wireless sensor nodes can

communicate directly with the sink in an infrastructure based WSN. Due to the

limited wireless coverage of sensor nodes, direct communication with the sensor node

is not always feasible for every node in the network, leading to the concept of ad-hoc

mode. In ad-hoc mode, nodes communicate with the sink via intermediate peers.

29


Each host in a mobile ad-hoc sensor network may be equipped with a variety of

sensors that can be organized to detect different local events. Each sensor is capable

of mobile communication and has some capability to process signals and to transmit

data. In an ad-hoc mode, each sensor node in the network works in a collaborative

manner and the whole network is used to provide the coverage of a large geographical

region. Sensor nodes in ad-hoc mode are not only employed to send information to

the sink but also to relay data to other nodes in the network [37]. Wireless sensors are

miniature, low power and low cost devices as distinct from laptops or PDAs in

conventional ad-hoc networks. In contrast to wireless LANs, where a similar amount

of data flows in each direction between any pair of nodes, WSNs require more data to

be sent to the sink (where data will typically be processed) and little data to be sent

from sink to the whole network. An example of a WSN is shown in Figure 3.2

(redrawn from [38]).

Figure 3.2: A Wireless Sensor Network

Mobile ad-hoc sensor networks are very beneficial in some scenarios, and improve the

operational efficiency of certain applications. For example, in a military operation, it

can be used to gather information about an enemy location and movement. This

network acts as a mobile traffic sensor network by monitoring vehicle traffic on

30


motorways, and as a mobile surveillance sensor network by providing security in

various places such as shopping malls and hotels. To locate free and occupied spots in

a parking area and to monitor the environmental changes in places like forests and

oceans, mobile ad-hoc sensor networks can also be used.

3.4 Underwater Acoustic Networks

In the past few years, interest in ad-hoc wireless sensor networks has been growing

fast and a lot of research has been done in the areas of communications, power

consumption, routing algorithms and protocols. Most of the research has focused on

terrestrial sensor networks with little attention given to underwater sensor networks.

With an increasing interest in the ocean, the demand for exploration of natural sea

resources and gathering of scientific data also increases. The traditional approach for

ocean-bottom or water-column monitoring is to deploy oceanographic sensors, record

the data on submerged instruments, and at the end of the data collection period, to

recover the instruments. In comparison, underwater acoustic networks can be formed

by establishing two-way acoustic links between various instruments, unmanned or

autonomous underwater vehicles (AUV) and mobile or fixed sensors. An Underwater

Acoustic Sensor Network (UASN) is one type of sensor network formed by a group

of wireless sensors operating on acoustic links. Often a sink node is involved to gather

the readings of certain physical phenomena from all the nodes in the network, or a

gateway node may be used to connect to an external, non-acoustic network. Some of

the many potential applications using underwater acoustic networking concepts

include oceanographic data collection, pollution monitoring, seafloor exploration,

ocean disaster prevention, and tactical surveillance applications for the national

defence [39 – 42].

31


Despite the many applications where an underwater acoustic network can be used,

underwater networking is still an immature area. Only a few experimental

implementations of underwater acoustic network have been reported in the last few

years because deploying a network under water is more difficult than deploying a

terrestrial network [43]. A key issue is communications at the physical layer. Acoustic

waves are normally used for underwater communications. The propagation

characteristics of the acoustic waves differ from radio waves and create a challenging

environment for reliable communication [44]. Current terrestrial sensor networks

operate at radio frequencies on electromagnetic waves. Radio communications is of

limited utility under water since radio waves are strongly attenuated in salty water

[42]. Light is strongly scattered and absorbed under water, though in extremely clear

(often very deep) water, blue-green wavelengths may be used for short-range, high-

bandwidth connections. In very clear water, optical modems are expected to achieve

data rates up to several Mbits/sec at very short range (up to 100 m) [45]. Underwater

optical communication using light waves require either high pointing precision or

high power if the distance between two nodes is large [46]. As a result, underwater

networks normally use acoustic communications since sound waves propagate well

through water and require much less power for the same communication range.

Acoustic waves can propagate in the sea water where salinity shows strong

conductivity, making radio communications especially difficult.

Underwater acoustic communication has been investigated by many researchers and

the major focus in this area is transmission range, bandwidth utilization and reliability

in handling multipath propagation and other channel effects [47]. The diversity in the

potential application space for underwater sensor networks has led to different

32


projects with a wide range of design requirements. Figure 3.3 shows a simple

underwater sensor network.

Figure 3.3: An Underwater Acoustic Sensor Network [48]

There are some challenges for transmission of acoustic waves in underwater. The

most important of which are discussed below.

Low Propagation Speed: The propagation speed in the underwater acoustic (UWA)

channel is low relative to potential source receiver velocities, leading to time-scale

changes (Doppler shifts) which, in relative terms, are significantly greater than those

encountered at radio frequencies. Doppler effects are therefore more severe than are

normally seen in terrestrial radio links. Acoustic waves travel much more slowly

(approximately 1500 m/s) than radio waves. It therefore takes a longer time to transfer

packets due to high propagation delay and this causes a drop in system performance.

Path Loss and Limited Bandwidth: The acoustic signal faces three types of losses

during its propagation: geometric, scattering and absorption loss. Path Loss (Path

Attenuation) is the reduction in power density (attenuation) of an acoustic wave as it

propagates through the underwater channel due to these three effects [49]. Geometric

33


Path Loss may be due to many effects, such as free-space loss, refraction and

diffraction. Scattering loss is due to scattering from suspended particles in the

medium. This is low in underwater acoustic communication because such particles are

much smaller than the wavelength. The absorption depends on the transmission

frequency and the salinity of the medium.

Most contemporary underwater acoustic systems operate at frequencies below

30 kHz, because at higher frequencies there is stronger absorption. At higher

frequencies, absorption over the distance between the communicating nodes would be

too great. So, only low frequencies can be used for links of the order of several

kilometres. In an underwater acoustic link, the operating frequency is inversely

proportional to link range [50, 51]. The available bandwidth of UWA channels is also

very limited compared with that offered by RF radios. The available bandwidth is

directly proportional to operating frequency, hence link distance [1].

Multipath and Doppler Effect: Underwater acoustic signals are subject to time-

varying multipath [52], which may result in Intersymbol Interference and large

Doppler shifts and Doppler spreads that are large relative to those seen on radio

channels. Multipath problem occurs when a given signal propagates from a source to

a destination along multiple distinct paths, each path having different path length and

hence a different propagation delay. As shown in Figure 3.4 (redrawn from [53]), the

direct path arrives at the receiver along with a series of alternate paths due to surface

and bottom reflections. The number of alternate paths is variable depending on the

medium and topographic factors but can be large [53]. The length of each path, and

hence its propagation delay is time-varying. This means that, not only it is necessary

to track the multi-path delays in an equalizer, but each arrival will exhibit a different,

34


and time varying, Doppler shift. At the receiver, it is necessary to estimate time,

Doppler (frequency) and amplitude, channel parameters in order to compensate for

their effects on the received signal.

Figure 3.4: Multipath Effect in Underwater

Energy Consumption: Underwater acoustic communication requires much more

energy than radio communications. Both onshore and underwater sensors are powered

by batteries. Terrestrial sensors equipped with RF radios transmit at only tens of milli-

watts whereas the transmission power required by underwater sensors is in the order

of watts. Wireless sensors are very miniature devices powered by batteries of limited

energy [54, 55]. Terrestrial sensors require only low-grade weather resistance whereas

underwater sensors need high levels of waterproofing. To support long range

communications, heavy-duty batteries are required which are generally larger and

more expensive than those used in terrestrial networks. As a result, deploying

underwater sensor network is much more difficult and expensive than terrestrial

sensor networks. One approach is developed in order to reduce energy consumption

by using two modes of network nodes: active mode and sleep mode to reduce energy

consumption [52].

35


Acoustic Noise: The received signal in an underwater channel is impaired by ocean

noise related to hydrodynamics (movement of water, the flood of waves, water

currents, storms, wind, rain), seismic, biological and machinery noise. The physical

layer at the transmitter end is responsible for converting the logical information (bits 0

and 1) into signals which are transmitted over the communication channel. The

receiver detects the signal corrupted by noise and other channel distortions and

converts it back into logical bits. Each source of noise has a characteristic that varies

with frequency. Different sources are dominant in different frequency bands [56]. At

very low frequencies less than 10 Hz, the noise is mainly due to earthquakes,

underwater volcanic eruptions, storms, water turbulence and wave motion. For the

frequency band 10-100 Hz, this noise is caused by vessel traffic, while for frequencies

between 100 Hz and 50 kHz, the main noise source is wind and air bubbles. At very

high frequencies, above 100 kHz, thermal noise dominates.

Underwater communication systems use signals for carrying data. The performance of

an underwater communication link depends on the use of signals that perform well in

all environmental conditions and the use of good processing techniques in the receiver

that take into account the characteristics of the signal and characteristics of the

medium. The choice must trade optimal performance against complexity and cost.

Because all of the above mentioned limitations of the underwater channel, the

selection of the type of modulation and error correction techniques has to be carefully

analyzed for successful transmission of information through water.

3.5 Modulation Techniques for Underwater Communication

Sophisticated digital modulation methods have been adopted for radio communication

systems to support high data transmission rates. Due to channel properties and

36


bandwidth limitations, accomplishing the same data rate for underwater

communication is impractical.

Early underwater acoustic telemetry used Amplitude Shift Keying (ASK) and

Frequency Shift Keying (FSK) for data transmission. ASK performs well when the

path is straight and reverberation is low e.g. vertical transmission. In a noisy channel

its performance can be improved by an error correction scheme [57] but this decreases

the data rate. Most underwater communications use some form of FSK or PSK due to

the difficulties with ASK in reverberant environment. FSK is a simple modulation

technique that has been used widely over the past two decades in underwater

communications due to its resistance to time and frequency spreading of the

underwater acoustic channel [58, 59]. FSK is immune to multipath problem and

performs well in reverberant environment. The robustness and simplicity of FSK

makes it suitable for low data rate applications and, furthermore, FSK is considered

appropriate for shallow water long - medium range channels that exhibit rapid phase

variation [57]. Although the carrier phase tracking problem can be eliminated by

noncoherent detection, this technique is still prone to reverberation problems which

causes a drop in system performance. In PSK, digital data is represented by phase

changes, so coherent detection is required at the receiver to recover the phase

information of input signal. PSK is typically used to achieve higher data rates. But

PSK is sensitive to multipath propagation, which causes phase and amplitude changes

to the signal. Equalizing PSK works much better with the spatial diversity provided

by an array of receivers [45].

Orthogonal Frequency Division Multiplexing (OFDM), a wideband modulation

scheme has recently gained attention for underwater acoustic communications due to

37


its ability to overcome long channel delay spreads through the use of a guard interval,

to transform a frequency selective channel into multiple frequency non-selective

channels, and to offer relatively easy implementation of modulation and demodulation

through the use of the Fast Fourier Transform (FFT) and its inverse [60]. In an

underwater channel, OFDM is a very efficient modulation technique when the noise is

spread across the bandwidth [53]. Instead of a single modulated carrier, OFDM

transmits several carriers and is referred to as a multicarrier modulation technique.

Moreover, in multipath fading channels, OFDM systems offer more spectral

efficiency and perform robustly.

OFDM is very sensitive to Doppler shift and introduces motion-induced Doppler

distortion which creates non-uniform frequency offset in a wideband acoustic signal

[61]. The advantages of OFDM systems can thus disappear in a time-variable channel,

when channels begin to interfere due to Doppler frequency spread. OFDM is

extremely sensitive to any frequency offset that can result from a mismatch between

the frequencies of the local oscillators, or from Doppler distortion caused either by the

transmitter/receiver motion or by a mismatch between their sampling rates. Although

OFDM offers ease of channel equalization in the frequency domain; it can only

tolerate a frequency offset that is much smaller than the carrier spacing and for this

reason frequency synchronization and time-base (Doppler) correction are a critical

part of the system [62]. Direct Sequence Spread Spectrum (DSSS) [63, 64] based

Code Division Multiple Access (CDMA) can perform well in multipath environments

[45] and offers communication at lower SNR, but at the expense of a decreased data

rate. Existing descriptions of the underwater acoustic channel tend to describe

relatively long paths at relatively low frequencies. The aforementioned channel

characteristics are common, and have led to substantial investigation of exotic

38


modulation schemes, such as OFDM. Studies in [57] also show that Phase Shift

keying (PSK) achieves a better SNR and thus it is a frequently applied technique for

underwater communications.

3.6 Underwater Modems

There is a substantial interest in the design and deployment of underwater acoustic

communication networks, even though a number of acoustic modems are currently

available to support commercial and academic projects. Underwater acoustic modems

consist of two main components:

• The analog front end consisting of an underwater transducer, hydrophone and

matching pre-amp and amplifier for acoustic communication.

• A hardware platform (microcontroller, DSP, or FPGA) for control, signal

processing and interfacing.

The next three sections will discuss different types of underwater modems.

3.6.1 Low vs High Frequency Modems

Mostly low frequency modems are used in contemporary underwater acoustic

networks. Although long communication range can be achieved with these modems,

their low operating frequencies mean that only low channel bandwidth is available,

which results in slow data rates [65]. Moreover, the signal quality at the receiver is

constrained as the low frequency acoustic channel suffers from substantial multipath

and Doppler effects in the underwater environment. Hence only 1 or 2 bits per symbol

are achieved using low frequency signals, with the effective data rate further reduced

by error control coding. High frequency acoustic signals are heavily attenuated in

water which severely constrains the range of high frequency links. However high

39


frequency signals offer substantially greater signal bandwidth, and improved channel

quality [5]. These characteristics mean that high frequency channels should allow

high data rates. There is also a range-frequency trade-off because higher frequencies

result in a higher absorption rate [4]. But the high frequency channel is poorly

documented, because most existing work in underwater communications applies to

longer paths, utilising low-frequency acoustic signals to minimise absorption [50].

3.6.2 DSP vs FPGA Modems

Digital signal processing applications are commonly implemented on two types of

programmable platforms: DSPs and FPGAs. DSPs are a specialized form of

microprocessor, while FPGAs are a form of highly configurable hardware [66].

Generally, digital signal processing algorithms are implemented using DSP chips but

advancements in field programmable gate array technology provide new options for

DSP design engineers due to its ability to handle computationally intensive signal

processing algorithms in real time.

System performance is a major concern for complicated applications. To achieve the

maximum performance, the whole system has to be redesigned, reoptimized and

rebuilt with minor changes as new problems arise. Reconfigurable computing

addresses this issue by allowing a dedicated device to be built using an FPGA. The

behaviour of the circuit can be modified by reprogramming the chip [67]. The

availability of FPGAs enables the designer to create high speed design with

flexibility, low latency and high throughput. The main attraction of FPGA is that it

avoids the high development costs and the inability to make design modifications

after production. The FPGA also adds design flexibility and adaptability with optimal

device utilization while conserving both board space and system power, which is

40


often not the case with DSP chips [68]. FPGAs may offer a better solution when a

design demands the use of a DSP, or time-to-market is critical, or design adaptability

is crucial. So, FPGAs have become a competitive alternative for high performance

DSP applications, previously dominated by general purpose DSP devices.

So, reconfigurable computing [68] based FPGAs are used to accelerate product

development and support evolution of fielded systems. Given the immaturity of the

field of underwater communication, a reconfigurable modem is a valuable tool for

development and testing modem techniques. FPGAs offer an opportunity to accelerate

digital signal processing applications up to 1000 times over traditional DSP

processors [69]. Like microprocessors, many FPGAs can be infinitely reprogrammed

in-circuit in only a fraction of a second. Design revisions, even for a fielded product,

can be implemented quickly and with minimal effort. Hardware can also be reduced

by taking advantage of reconfiguration. Despite all of these inherent benefits, due to

lack of knowledge, most of the existing modems are implemented based on DSP

processors. There is little published work on FPGA modems.

3.6.3 Hardware vs Software Modems

To transmit, receive, modulate and demodulate acoustic signals, most of the existing

underwater acoustic sensor networks rely on specialized hardware. The specialized

hardware used for modulation ranges from commercially available expensive acoustic

modems [70] to dedicated integrated circuits [46] and dedicated DSP boards [63]. The

specialized hardware used for communication ranges from underwater acoustic

transducers and hydrophones [47] to off-the-shelf speakers and microphones [46].

Most of the existing underwater applications either use commercial acoustic modems

or build custom transceivers for each application - both of which lack flexibility and

41


may require prohibitive monetary or time-investment for many applications. The cost

of a single commercial underwater acoustic modem is at least several thousand US

dollars. The prohibitive monetary cost and high power consumption of existing

underwater hardware represent an obstacle for the deployment of underwater sensor

networks. Establishing acoustic underwater communication using specialized

hardware increases the network cost, design time and effort spent in interfacing node

hardware components, and the size and weight of the individual network nodes.

Most of the existing modems were implemented in hardware due to low processing

power which did not allow the modulation and demodulation in software. Recent

improvements of processing power enable us to run the modulation and demodulation

in software and thus the software modem becomes a viable alternative which

overcomes the drawbacks of a hardware modem. Recent approaches to software

modem design eliminate the need for specialized hardware for acoustic

communications and thus reduce the cost of network deployment and make acoustic

communication faster. A very widespread approach is the Software Defined Radio

(SDR) [71], whose modulation and demodulation techniques exist as programs either

in software in a dedicated processor (DSP) or logic in a programmable logic device

(FPGA). This provides a high degree of versatility in the equipment because different

modulations and demodulation schemes can be implemented using the same physical

hardware.

42


3.7 Existing Underwater Modems

Commercially available acoustic modems produce data rates from 100 bps to about

40 kbps and have an operating range of up to a few km and an operating depth of

thousands of metres. Jurdak et al. in the California Institute for Telecommunications

and Information Technology [72] have proposed a FSK software acoustic modem

running on generic microphones and speakers to establish acoustic communications

for underwater sensor networks. Their observation found that in general, lower

frequency signals have higher signal quality than higher frequencies, and SNR is too

low to distinguish the signals from noise for frequencies above 3 kHz. Their modem

was intended to operate at a frequency below 3 kHz. Their experiments have explored

the frequency profile of the medium as a means for designing a software modem for

distances up to 10 m. Their experiments with generic acoustic hardware also explored

the system’s data transfer capability and confirmed the system’s capability of

transferring information in the order of tens of bits per second for a communication

range of up to 10 metres. They have conducted two sets of experiments in their work:

A) Experiments to profile the medium’s frequency response and B) Experiments to

evaluate data transmission capability. For their experiments they used two laptops,

with one laptop attached to the speakers acting as a sender and another attached to the

microphone acting as a receiver. The microphone and speakers were placed at a depth

of about 50 cm and were placed inside a controlled water environment. The

communication system in their work advocates the use of short multi-hop links for

deploying dense sensor networks. The main advantage of their system is that it was

implemented in software and the cost of their system was limited to the relatively

cheap sensor module. The capability of running their software modem on generic

hardware reduced the hardware cost, thereby potentially promoting their wide

43


deployment. The other advantage of their system is that it mitigates against the

adverse effects of marine biology (environmental preservation) by using multi-hop,

short-range, low-power links between sensor nodes.

Iltis et al. at UC, Santa Barbara developed a hardware acoustic underwater telemetry

modem for ecological research applications [63] using the fixed point DSP board with

custom amplifiers, matching networks, and transducers. In an underwater ad-hoc

network, their modem is intended for interfacing to nodes, and achieves a 133 bps

data rate. In the transmitter, the digital signal generated by the DSP is applied to a pair

of DACs, one of which is dedicated to scale the transmitted signal (for power control).

In the receiver, the signal from the 25 kHz center frequency transducer is amplified

and filtered, with a large gain-adjust range in the amplifier. The filtered signal is

applied to the 12-bit ADC, which is a module on the DSP chip. Their future intention

was to implement the modem in reconfigurable hardware for supporting lower power

and large acoustic bandwidth and data rates.

Work discussed by Martos and Bonadero [71] shows the digital demodulation of

RBDS (Radio Broadcast Data System) information transmitted along with

commercial FM broadcast (88 MHz -108 MHz) using a FPGA device that can be

reprogrammed to support different modulations without changing the existing

hardware. In their demodulation method, they generated two base-band sinusoidal

signals (I and Q) from a ROM LUT and then multiplied each sample from the ADC

with a position of the table in a synchronized way. The products were passed by FIR

(Finite Impulse Response) low pass filters to eliminate the images from mixing. Then

the phase and frequency of the incoming signal is calculated using a ROM LUT. The

broadcast FM demodulated signal passes through a band pass filter of 4 kHz

44


bandwidth with a center frequency of 57 kHz to extract the RBDS signal with SC-AM

sub-carrier. The same FM demodulated signal is passed through another band pass

filter to regenerate the sub-carrier. Once the RBDS signal with standard AM

modulation is generated, it is demodulated with a digital envelope detector. Their

FPGA based implementation allows its reconfiguration to be utilized in other digital

modulations without modifying the hardware. Although they have shown that it is

possible to add the digital demodulation functionality to commercial receivers easily

at low cost, the carrier recovery technique in the demodulator was not discussed in

detail in their work, nor was the filter implementation technique.

Most recent works in underwater communications development have relied on using

the WHOI micro-modem [58], which is a compact, low power underwater acoustic

communications and navigation subsystem. The micro-modem has a main electronics

board enhanced by different electronic modules. The modem is capable of performing

low-rate frequency-hopping FSK (FH-FSK), variable rate PSK and two different

types of long base-line navigations: narrow band and base band. The system can

transmit in four different bands from 3 to 30 kHz, with a larger board required for

lowest frequency. The main board of the modem is based around a Texas Instruments

fixed point DSP, the c5416, providing up to 160 MIPS. The micro-modem has a

power amplifier to drive the ceramic projector, to act as a single channel receiver and

to act as a power conditioning system. The efficient design of the amplifier makes it

easily modifiable for use under various vehicle power systems, signal

frequency/bandwidth and projectors. The floating-point co-processor board of the

modem supports computationally complex PSK equalization algorithms. The co-

processor board consumes as much as 2 watts due to its high speed-floating point DSP

and fast SDRAMs. That’s why the micro-modem switches the coprocessor off

45


completely and powers it on after a PSK packet is detected. The micro-modem also

uses a RF-acoustic gateway buoy to support telemetry of underwater acoustic network

traffic to a remote location. To manage the signal processing on the micro-modem,

WHOI uses a low overhead real time operating system. The micro-modem supports

frequency-shift keying combined with frequency hopping [73], allowing operation in

a shallow water multipath environment. The system operates at approximately 10, 15

or 25 kHz with 80 bps data rate. In 2005, the micro-modem started to support multi-

rate PSK capability with data rates from 300-5000 bps. The modem was tested both in

shallow and deep water in different ocean scenarios. Though this modem is a very

capable signal processing platform for underwater acoustic communications, it

operates only at low frequencies (<30 kHz).

The BPSK modulation and demodulation technique described by Ruque et al. [74]

uses a multiplexer that selects the carrier either in phase or 180o out of phase

depending on the condition of binary input data. The simulation was done using

Simulink and the components of a system generator. In their work, they used the

system generator to create and verify a hardware design for Xilinx FPGAs, which

works together with Simulink and Matlab. They implemented the modulation and

demodulation in Xilinx Spartan3 which is intended for low cost and high volume

applications. The results obtained by the actual implementation in development board

are practically the same as those obtained from the simulation. Since the results

obtained from hardware are dependent on the simulation of software, it is much easier

to change the design by changing the software even after finishing the

implementation. Although their software simulations and FPGA implementation

provide many advantages, the carrier recovery technique and filter implementations

46


are not discussed in their work. The operating frequency of their modem has also not

been discussed.

A theoretical analysis has been discussed by Bernal et al. [75] along with the design

guideline of a digital I&Q demodulator for a general antenna array receiver. FPGA

implementation issues were also discussed in their work. They compared the digital

I&Q demodulation with conventional I&Q demodulation and concluded that digital

I&Q demodulation reduces the number of inputs to a digital signal processing device.

No carrier recovery scheme and filter implementation are discussed in their work. The

bit detection part of the demodulator is also not covered here.

Nataraj et al. [76] have discussed the novel architecture for the Quadrature Phase

Shift Keying (QPSK) demodulator suitable for processing satellite data

communications. In their demodulator, the receiver algorithm is divided into two

parts: one is based on a FPGA and the other on a DSP processor. The entire modem

was coded in Matlab to validate the hardware results. They only discussed the FPGA

implementation details in their work, the DSP implementation was out of their scope.

Most existing commercial modems are designed for sparse long range applications

rather than dense short range communications. Benson et al. [77] presents the design

of a low cost short-range underwater acoustic modem which substitutes the expensive

commercial transducer with a home made underwater transducer using cheap piezo-

ceramic material and builds the rest of the modem’s components according to the

properties of the transducer to get as much performance as possible. Their analog

transmitter was designed to support signals in the range of 0-100 kHz. They chose

FSK as the prototype of their low-cost, low-power, low data-rate applications due to

its simplicity and robustness. The carrier frequency was chosen as 35 kHz based on

47


the properties of transducer. They tested their modem with 50 metre distance and their

digital hardware was able to demodulate the data bits with 30% bit error rate at 10 dB

SNR in a strong multipath environment. Given the results, it is reasonable to predict

the modem would perform well in less severe multipath environment. Although their

modem stands as low-cost, comparable power alternative to existing modem designs,

the modem is suitable only for low data rate applications.

P.-P. J. Beaujean at Florida Atlantic University [78], developed a one-way, high-

speed, high-frequency acoustic modem (HS-HFAM) operating between 260 kHz and

380 kHz to transmit compressed underwater images and status information in real-

time. They achieved high data rate using a high-resolution decision feedback

equalizer with parallel algorithm for tracking and compensating large Doppler. A

series of field experiments were conducted to test their modem in Port Everglades,

Florida, in very shallow water acoustic channels causing significant fading. The

experimentation took place in water depths of up to 3 metres and ranges of 15 to

118 metres. They used BPSK and QPSK as modulation techniques and achieved

maximum data rate of 87.7 kHz. Experimental results were obtained using a very

compact source with output power of 6.6 W, indicating that their HS-HFAM is

remarkably power efficient and ideal for small UUVs and divers.

Demodulators require filters to eliminate unwanted noise from the incoming received

signal. S. S and S. Y. Kulkarni [79] have discussed the high speed and low power

FPGA implementation of FIR filter for DSP applications. The major challenge of

higher order filter implementation is the large number of multiplications. The authors

generated the HDL code from FDA tool of Matlab and gave instructions to optimize

the HDL by using a variety of techniques like pipelining and distributed arithmetic.

48


Arroyuelo et al. [80] present an efficient method for implementing digital filters in

FPGAs. The advantages of using FPGA approaches towards filter implementation

include higher sampling rate than those obtained from traditional DSP chips. A

filtering function is usually carried out by a number of multiplications which are

expensive in terms of time and space. In their work, to reduce the hardware

requirement, they avoided the traditional approach of general purpose multipliers

which are not economic in FPGA architecture and multipliers were replaced by look-

up tables and adder-subtractors, which use Bit-Serial Arithmetic as an alternative to

Bit-Parallel Structure. Bit Parallel Structure processes all the bits simultaneously with

the expense of significant hardware cost whereas Bit-Serial Structure processes one

bit of the input at a time and all the bits pass through the same logic, resulting in a

huge reduction in hardware requirement. This approach reduces the logic cell

utilization in an FPGA but degrades the filter performance since the serial hardware

takes n clock cycles to execute while the parallel structure executes in one clock

cycle. Another approach towards multiplier-free FPGA filter design can be seen in

[81], which are expensive since they are implemented in hardware.

Both of the works reported in [63] and [82] focus on developing underwater acoustic

modems with low cost and specialized affordable hardware, our work aims to reduce

the cost and make a completely software based acoustic modem with minimal

hardware support that can operate in a high frequency (100 kHz to 1 MHz)

underwater environment.

3.8 Summary

This chapter has discussed different categories of ad-hoc networks along with their

characteristics. Typical modulation schemes and their suitability in underwater

49


applications have also been summarized. The chapter has also surveyed the types of

modems used in underwater communication and discussed some proposed approaches

for designing an underwater modem. The potential benefits to be derived from a high

frequency FPGA modem in underwater communication are also discussed in this

chapter. The rationale for using high frequency, software defined FPGA modem in

underwater networks has also been discussed. The next chapter will discuss the design

of our high frequency FPGA acoustic modem in detail.

50

Chapter Four High Frequency FPGA Acoustic Modem -----------------------------------------------------------------------------

4.1 Introduction

This chapter describes the novel design concept of a software defined FPGA acoustic

modem developed to demonstrate a reliable platform for high data rate underwater

acoustic communication. The FPGA modem is targeted to support Binary Phase Shift

Keying (BPSK) modulation which is less sensitive to noise than other modulation

schemes of similar complexity. The next section gives a brief description of the BPSK

modulator. Section 4.3 describes the BPSK demodulator which uses a Costas loop

[13] at the receiver due to its ability to perform both suppressed carrier reconstruction

and synchronous data detection within the loop. The BPSK demodulator along with

each individual component is also discussed in this chapter.

4.2 BPSK Modulator

In the BPSK modulation scheme, the phase of the sinusoidal carrier is changed to one

of two values to represent the data bit stream. In our BPSK modulator, the

information bit ‘0’ is transmitted by shifting the phase of the sinusoid by 180o and

information bit ‘1’ is transmitted without any phase change in sinusoid i.e. with a 0o

phase shift. So the BPSK modulator generates a BPSK modulated signal based on the

incoming binary data. Figure 4.1 shows a simplified block diagram of the BPSK

modulator. The initial sampling rate of the modulator is chosen as 4 MHz and the

symbol generation rate is 80 ksymbol/s, giving 5 samples per carrier cycle and 50

Chapter Four: High Frequency FPGA Acoustic Modem

samples per symbol. The parameters were chosen to provide a high frequency signal

with wider bandwidth than the low frequency acoustic channel.

Figure 4.1: Block Diagram of BPSK Modulator

The modulator operates by up-sampling (50 samples per bit) the input binary data

stream to produce a train of positive or negative impulses. The up-sampling is done

by inserting 49 zeros between consecutive symbols. The dirac-delta pulse generated

after up-sampling is sent to a 101 tap root raised cosine filter [12] to produce a raised

cosine pulse.

In signal processing, a Root Raised Cosine filter (RRC) [83], (also known as Square

Root Raised Cosine filter (SRRC), is frequently used as both the transmit and receive

filter in a digital communication system to do matched filtering. The combined

response of two such filters is that of the Raised Cosine Filter [84, 85] which is a low

pass filter commonly used for pulse shaping in data transmission systems. In our

modulator, a root raised cosine filter is used for pulse shaping and to reduce the

Intersymbol Interference (ISI) at the transmitter. Our receiver uses an identical root

raised cosine filter as a matched filter. Together, the two root raised cosine filters (one

at transmitter and one at receiver) provide a raised cosine filter response over the

channel for ISI removal.

52


The number of taps in the filter is determined by the sampling frequency and the bit

rate of the modulator – the filter being at least two symbols in length with one tap per

sample. The detailed design of this root raised cosine filter will be discussed in

Section 4.3.2, as this filter also acts as a matched filter in the receiver.

The filtered signal is then multiplied with the locally generated carrier stored in a

look-up table (LUT). The LUT is a set of memory locations containing pre-calculated

values representing a sine-wave. The clock for the LUT is obtained from the master

oscillator on the FPGA board. Because the code (data) and carrier signal rates are

derived from the same reference oscillator they are guaranteed to be synchronized. In

fact the entire modulator circuit is synchronous which allows unique oscillator and

timing recovery at the demodulator.

The up-sampling process shown in Figure 4.1 changes the magnitude level of binary

input data before inserting zeros between sample values. For this particular design, a

binary data bit ‘0’ is represented by the magnitude level of -8000 and binary ‘1’ is

represented by the magnitude level of +8000. The sinusoidal generator is a simple

LUT used to store the sample values required to generate a desired sinusoid carrier.

For this particular design, there are 5 samples per carrier cycle. Because of this

conveniently chosen ratio, the LUT can be very sparse, requiring only 5 values. This

is because the modulator is driven by 4 MHz clock and the carrier generated from

LUT is 800 kHz.

The modulator is highly efficient to implement in an FPGA. The main reason for

choosing an FPGA as a design tool is because of its reconfigurable capability for

implementing DSP solutions. The design can easily be changed to add more features

without beginning from scratch. But FPGAs are not free from weakness.

53


Multiplication is an important but expensive operation in most FPGA-based signal

processing systems. Most FPGA targets contain a limited number of embedded

multipliers. The FPGA module compiler uses embedded multipliers to implement

multiply operations until it occupies all the embedded multipliers. If the FPGA target

runs out of embedded multipliers, the compiler uses generic logic gates instead, and

the multiply function becomes expensive in terms of FPGA resource usage. Many

techniques have been introduced for reducing the size and improving the speed of

FPGA-based multipliers. In our modulator design, the majority of the process can

easily be implemented directly using logic gates, with a simple multiplication on the

output. The RRC filter is implemented using a unique technique that does not require

multiplications and is discussed later.

4.3 BPSK Demodulator

The demodulator consists of a Costas loop [26], which provides carrier recovery and

demodulation of the BPSK signal within the same loop. This is the main reason for

designing our demodulator using the Costas loop. The local oscillator (LO) is derived

from a Numerically Controlled Oscillator (NCO) as shown in Figure 4.2.

Figure 4.2: BPSK Demodulation using the Costas Loop [26]

54


The feedback from the product of the I & Q channels adjusts the phase of the signal

generated by the LO so that the Q-channel has minimal response relative to the I-

channel. The output of the I-channel is the demodulated data when the loop is locked.

The Costas loop adjusts the LO until it matches the received BPSK signal in phase

and frequency. Ideally, the low frequency product of the BPSK signal and the

quadrature of the carrier should be zero. Each of the multipliers in the I and Q arms is

a part of a separate synchronous demodulator. Identical root raised cosine low-pass

filters are used in each of the upper (I) and lower (Q) paths of the Costas loop to

remove the high frequency component and minimise ISI. These root raised cosine

filters are identical to the one in the transmitter. That means they are a matched filter,

as well as working in conjunction with the RRC filter in the transmitter to provide a

net raised cosine filter response at the receiver to minimise ISI. The filtered output of

the I-channel is hard-limited before multiplying it to the output of the Q-channel using

a third multiplier. A hard limiter is placed in the I-channel of the Costas loop to

estimate the data pulse steam. The third multiplier simply inverts or non-inverts the

Q-signal according to the data estimate. The low pass component of this is used to

adjust the phase of the local carrier generated from the NCO. The Costas loop is

locked when it has adjusted the LO phase and frequency until the quadrature (Q)

signal is minimised. The Costas loop aims to maximise the output of the I arm and

minimize that from the Q arm. The output of the I-channel is the demodulated data

and thus the Costas loop not only acquires the carrier but also acts as a synchronous

demodulator.

The mechanism of the Costas loop carrier recovery is to adjust the LO until the Q-

signal is minimised. This means that the LO matches the received BPSK signal in

phase and frequency. The incoming BPSK modulated signal is multiplied by the local

55


carrier (I-channel) and 90o phase-shifted local carrier (Q-channel). The low-frequency

product of a BPSK signal and its coherent carrier is the demodulated information,

while the low-frequency component of the BPSK signal and the quadrature of the

carrier is zero. The outputs of both demodulators (I and Q) are passed through low-

pass filters (the RRC filters) to remove the high frequency component. The feedback

to the LO is just the Q-channel adjusted according to the sign of the I-channel. The

Costas loop is locked when it has adjusted its NCO phase and frequency by

minimising the Q-channel. In this particular design, the loop is considered locked

when the phase error (difference between I and Q channel) is less than a particular

threshold value i.e. the feedback/phase error oscillates around zero.

4.3.1 Numerically Controlled Oscillator (NCO)

As shown in Figure 4.3, our Numerically Controlled Oscillator (NCO) consists of a

phase accumulator, which provides an address for two LUTs containing a sine-wave

and cos-wave respectively. The memory locations of a sine LUT store binary values

calculated from the following equation for different initial phase [86]

θsin*)( AiLUT = … … … … … … (i)

where i is index of the LUT. The angular resolution θ∆ for a LUT with memory

words equal to L is given by [87],

Lii /2)1()( πθθθ =−−=∆ … … … … … (ii)

where i varies from 0 to L-1. Varying L produces a sinusoid of different frequency

when the input clock frequency is fixed. Angle θ at any sample can be expressed as

ii *)( θθ ∆= … …. … … …. …. … … … … (iii)

56


Substituting )(iθ into (i), we get,

)/**2sin(*)( LiAiLUT π= … … … … … … (iv)

To generate the cos LUT, we use the following equation:

)/**2cos(*)( LiAiLUT π= … … … … … … (v)

The resolution of the LUT can be varied by changing the value of L. The amplitude of

the output waveform depends on A of equation (i). The sample values for sine and cos

LUT can be calculated from equation (iv) and (v) respectively. The value of A can be

selected and scaled to suit the design requirement and to maximize the synthesizer’s

output dynamic range. For the 14-bit resolution DAC, the maximum value of A can

be chosen as 2^14-1 =16383 if the output is generated as an unsigned integer.

Figure 4.3: Block Diagram of NCO

The resolution (n-bit) of the phase accumulator, and hence frequency resolution, is

greater than the resolution (k-bit) of the LUTs. The upper k bits of the phase

accumulator are used to address into the LUTs, while the lower n-k bits are simply

used to carry forward the residual phase for future samples.

The current step size (n-bit) calculated from the output of LPF 2 and fixed step size is

added with the previous step size stored in the phase accumulator of the NCO. The

phase accumulator sends the upper k bits (k≤ n) of the summation to address the look-

57


up tables and sends all n bits to be added with the next step size for getting the next

numerical value to address the LUTs. By extending the precision of the phase

accumulator beyond the address size of the LUT, our tuneable oscillator (NCO)

design can deal with almost infinite frequency resolution from a relatively small LUT,

which overcomes the limited frequency resolution of existing NCO designs [86]. The

downside is that the phase resolution is set by the LUT length. This in turn sets the

phase noise of the NCO.

4.3.2 Root Raised Cosine Filter (LPF 1)

Two identical Root Raised Cosine Low Pass Filters (LPF 1) are used in the upper

and lower channels (I and Q-channels) of the Costas loop to remove high frequency

components and to avoid imbalances that will prolong loop settling time. The root

raised cosine filter helps in pulse-shaping in digital modulation due to its ability to

minimise ISI. As mentioned earlier, these two filters work in conjunction with an

identical RRC filter at the transmitter to provide the raised cosine filter effect at the

receiver for minimising ISI.

As shown in Figure 4.4, the filters in the Costas loop are designed as symmetric Finite

Impulse Response (FIR) filters, and are implemented in the FPGA as a tapped delay

line. However, instead of using multipliers, we implement the filter weights as a series

of right shifts and additions.

The output of a FIR filter is calculated using the following equation:

)(*)1(.........)1(*)2()(*)1( )( nmxnbmxbmxbmy −+++−+=

where, y(m) is the output signal, x(m) is the input signal, b(i) are filter coefficients and

n is the filter order.

58


Figure 4.4: Block Diagram of LPF 1

To design our multiplier-free filter, the filter coefficients (<1) are generated in

MATLAB and then approximated as a summation of two inverse powers of two.

Multiplication by an inverse power of two is simple to implement as a right shift

operation in the FPGA.

To illustrate this operation, suppose the original coefficient generated from the

MATLAB filter design tool for a particular filter tap is 0.78. We approximate this

coefficient by producing two right bit-shifted versions of the input - in this case a 1-

bit (0.5) and 2-bit (0.25) shift, and then summing the resultant values. For example, if

the current input sample is 128, then 1-bit and 2-bit right-shifted values would be 64

and 32 respectively, which would produce a filter tap output of 96. If the filters are

implemented using a multiplication at full precision the (correct) answer would be

99.84 (128*0.78). Implementing the filter taps using this right shift and addition

technique requires substantially less FPGA resources than performing direct

multiplication. The decision to add only two right-shifted values for each tap is a

design choice; higher filter coefficient resolution could be obtained by using more

right-shifted values, provided the FPGA resources were available.

59


4.3.3 Low Pass Filter (LPF 2)

The purpose of the second Low Pass Filter (LPF 2) is to remove the excess noise

products produced by the two previous multipliers and two filters in the I and Q

channels of the Costas loop. This filter (LPF 2) is used to remove spurious

components coming from the feedback signal. A rule-of thumb recommendation for a

safe, out of the loop, response would be to set the pole of second low pass filter (LPF

2) to a minimum of four times that of what the closed loop response would be without

this filter [26]. How fast the NCO will settle actually depends on the initial phase and

frequency of the NCO as it relates to the incoming BPSK signal.

LPF 2 does not significantly contribute to the Costas loop locking response and its

response should be far outside the closed-loop response. This filter should have its

pole at a low enough frequency that the Costas loop will not be too noisy, nor be

subject to carrier phase reversals in the presence of noise (i.e., the loop is equally

stable in both phases), while high enough that it doesn’t cause the loop to oscillate.

Setting this pole to eight times the LPF 1 pole is the point at which this filter

negligibly affects on the loop.

Our modem uses a 5 tap Chebyshev Type II IIR filter as the second filter (loop filter)

of the Costas loop. The cut off frequency of this filter is set to the 10 times the cut off

frequency of the data filter (LPF 1). As shown in Figure 4.5, we have designed this as

an IIR filter to implement in the FPGA as a tapped delay line and the filter output is

calculated using the following equation:

)3(*)4()2(*)3()1(*)2()4(*)5()3(*)4()2(*)3()1(*)2()(*)1()(

−−−−−−−+−+−+−+=

myamyamyamxbmxbmxbmxbmxbmy

60


where, y(m) is the filter output signal, x(m) is the input signal, b(i) are filter feed

forward coefficients, a(i) are feedback coefficients and the order of the filter is 4. The

MUL and ADD blocks in the figure represent Multiplication and Addition operations

respectively. SUB and D blocks are used to represent Subtraction and Delay

operations.

Figure 4.5: Block Diagram of LPF 2

This filter is implemented using the built in FPGA multipliers rather than any

methods of approximation (such as using right shift and addition operations used to

implement the LPF 1). This is because the second filter consists of only 5 taps,

compared to 101 taps for each of the three RRC filters, so it will not add much cost

and complexity to the design since we have sufficient resources to implement this

directly using the FPGA built in multipliers.

61


4.3.4 Hard Limiter

A hard-limited Costas loop can improve the carrier recovery process. The Hard

Limiter is placed in the I-channel of Costas loop and is used to estimate the data pulse

stream. This strips the modulation off and leaves the phase error for the phase-locked

loop (PLL). Since the feedback of the Costas loop forces the error towards zero, the

error channel is driven to zero, but either channel (the sine and cosine output of the

demodulator LO) could be the data channel. By hard-limiting one of the channels, this

automatically becomes the data channel since it produces a sign change. The other

channel becomes the error channel, which is driven to zero.

The Hard Limiter of the Costas loop implements the SIGN function (also known as

signum function) for the in-phase component. The SIGN function extracts the sign of

a real number. The SIGN function is defined as:

⎪⎩

⎪⎨

⎧

<=>+

=0. if 1-0, if 0 0, if 1

)( xxx

xSIGN

The Hard Limiter is placed in series between the upper LPF 1 and the third multiplier

of the Costas loop as shown in Figure 4.6 (a). The Hard Limiter implements the SIGN

function whereas the third multiplier of the costs loop adjusts the output of the Q-

channel according to the hard-limited signal. Our design is simplified by combining

the operations of Hard Limiter and the third multiplier as shown in Figure 4.6 (b). The

Hard Limiter in our demodulator implements the SIGN function and also performs the

operation of third multiplier in the Costas loop. The output of the SIGN function is

either +1, 0 or -1 and multiplying these values with the Q-channel leaves the Q-

channel unchanged, 0 or inverted respectively. So taking the I-channel as it’s input,

62


the Hard Limiter in our demodulator decides whether Q-channel, inverted Q-channel

or 0 is forwarded to LPF 2.

Figure 4.6 (b) shows that the Q-channel is passed to the input of LPF 2 based on the

sign of the I-channel and thus the third multiplier is omitted from the loop in the

actual design.

Figure 4.6 (b): Hard Limiter followed by Multiplier in FPGA Demodulator Figure 4.6 (a): Block Diagram of Hard

Limiter and Multiplier in the Costas Loop

4.4 Bit Synchronization

Once the Costas loop is locked, the BPSK demodulated signal is obtained from the I-

channel. The signal is then decoded by sampling each bit at the middle of each

symbol period. In our design, bit synchronization follows a forward error correction

(FEC) method to recover erroneous packets. In this method, the sender sends

redundant information along with the data bits to correct possible errors using this

information. In our design, each packet contains a preamble of extra bits at the

63


beginning of each data packet. Since, in wireless networks, packets are commonly

broadcast over shared channel and forwarded over multiple hops, using FEC is

preferable because it can reduce the need to retransmit data packets, thereby reducing

the power consumed in the process.

Figure 4.7 shows the algorithmic principle of the bit synchronization method used in

our design for decoding BPSK data bits. For each sample in the I-signal, the

synchronizer first checks whether this sample is in the middle of the symbol period. If

it is, then the sign of that sample value decides whether it is binary ‘0’ or ‘1’. The

positive sign indicates a binary ‘1’ whereas the negative sign of the sample value

indicates a binary ‘0’. To detect the exact bit position, the synchronizer keeps track of

the sample point in the I-signal where the last bit was detected. It then detects the

middle of the next bit period by adding half of the symbol length to the last bit

position detected. Once a binary ‘0’ or ‘1’ is detected, the synchronizer checks

whether the bit is in preamble mode or in the actual payload. If it is in the preamble

part, the synchronizer then checks if preamble detection is completed or not. If

completed, the phase of the data bits is detected from the phase of the preamble bits.

If the bit is not in preamble mode, then it is detected as a data bit and its phase is

decided from the phase of the preamble bits already detected. After detection, the

synchronizer counts the number of bits since last zero crossing is found. It also keeps

track of the last bit position detected in the demodulated signal. The synchronizer then

checks if the sample crosses zero and there is enough gap between two consecutive

zero crossings. The last bit position is also estimated from the information of actual

bit position and the zero crossing detected. The length of each bit period is also

calculated from this information.

64


Figure 4.7: Working Principle of Bit Synchronization

65


4.5 Summary

This chapter has discussed the detailed functional design of our high frequency FPGA

acoustic modem for underwater communication. Since the modem consists of the

modulator and the demodulator, the detailed design architecture of the modulator and

the demodulator has also been presented here. The working procedure of each of the

blocks of the modem is explained in this chapter. The next chapter will introduce the

FPGA design framework and demonstrate the implementation details of this high

frequency modem in Altium Winter 09. The performance of the modem will also be

reviewed in the following chapter.

66

Chapter Five Implementation and Performance Analysis -----------------------------------------------------------------------------

5.1 Introduction

This chapter gives the detailed description of the implementation of a high frequency

acoustic modem in an FPGA. The chapter presents the FPGA design framework and

demonstrates the design flexibility available in an FPGA with Altium Designer

software. A brief overview of Altium Winter 09 and all its necessary blocks needed to

support the design of the modem is also covered. The implementation of the modem

is carried out on Altera’s Cyclone III FPGA starter kit with a Terasic ADC/DAC

mezzanine card. The experimental results obtained from different test scenarios are

also shown and discussed in this chapter.

5.2 Overview of Altium Winter 09

As mentioned in previous chapters, with the flexibility to reduce the size and the cost

of the products, FPGA devices allow the designer to implement large, high speed

digital signal processing applications. These devices can be programmed to

implement even an entire digital system, including the microprocessor, peripheral

components and the interface logic [88].

To achieve this goal, a design environment is necessary - where engineers can capture

the hardware design, write the embedded software for the processor, and implement,

test and debug both the hardware and software on the target FPGA device. Altium

Designer provides this environment by bringing together the required tools and the

necessary communications systems. Hence, a complete FPGA design environment is

Chapter Five: Implementation and Performance Analysis

formed by combining Altium Designer with the selected FPGA implementation

board.

The design efficiency and flexibility offered by Altium Designer allows designers to

create complex custom designs more quickly and easily using their existing hardware

and software design skills. Altium provides flexibility to the designers to change the

way they think about developing electronic products and takes advantage of the

potential offered by today's large-capacity programmable devices [89].

Altium Designer provides designers with extensive libraries of FPGA-based

components, including a range of processors and peripherals to capture the system

design for FPGA implementation at the schematic level [89]. It provides designers

with the freedom to develop the design, and then compile it onto any of a wide range

of target programmable devices from multiple FPGA vendors, rather than locking

them into specific target devices. Designers are allowed to change the design at any

point in the design process and Altium Designer ensures design integrity by reflecting

these changes in all relevant documents/files in the project.

Altium Designer provides a single, unified environment for the designers throughout

the development process. With relatively less effort, designers can synchronize the

schematic capture with the FPGA layout, maintain I/O synchronization between

FPGA designs and the boards they reside on, and automatically ensure consistency of

memory and peripheral definition between the hardware and software elements of the

design.

Altium Designer’s FPGA development environment is used to capture, synthesize,

place and route and download a digital system design into an FPGA board. The

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process of implementing the design on the target device requires a better

understanding of the functionality and architecture of the device and this task is best

performed by the software tools provided by the device vendor [90]. The vendor

software is operated by the Altium Designer environment, which automatically

manages all project and file handling aspects necessary to generate the FPGA

program file. FPGA designs are captured in the Altium Designer design environment

as schematics and Verilog Hardware Description Language (VHDL) files. Our FPGA

modem is implemented in Altium Designer Winter 09 software [91].

Implementation related information such as device pin allocations and electrical

properties of pin are stored in a separate file called a constraint file. Constraint files

are generally mapped to a FPGA project by adding them to a project configuration

[92]. Constraint editors are used to define the constraints in the file. In our

implementation, we have used one constraint file, although multiple constraint files

can be used to separate constraints by their type. For example, design specific

constraints (such as specifying a net to be a clock) may be stored in one constraint

file, and implementation type constraints (such as pin allocations) in another

constraint file [92].

When an FPGA design is targeted for implementation in a device, one selects a

project/configuration combination, allowing the system to map the design to its

implementation. By defining multiple configurations, designers can easily re-target a

design from one device to another.

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5.3 Overview of Altera Cyclone III

To map the design of our BPSK modem implemented in Altium Winter 09 software,

Altera Cyclone III FPGA device [93] tools have been used which are integrated and

accessed in the Altium Designer environment through the Devices view (View »

Devices View). This view allows step-by-step control over the entire FPGA design

process, enabling designers to program and debug the system design on the FPGA

[90].

The Altium Build process allows interfaces with Altera tools and produces the device

program files such as SRAM object file (sof file) for downloading into the target

FPGA device. By clicking on the down arrow of Build process, a list of individual

steps - Translate Design, Map Design to FPGA, Place and Route, Timing Analysis

and Make BIT File, used to complete the Build process can be found. The object file

(*.sof) generated after building an FPGA project is downloaded into Cyclone III

device via the Altera Quartus II (version 8.1) software. The Quartus II Web Edition

software provides the necessary tools for developing hardware and software for Altera

FPGAs.

Our modem is based on a Cyclone III EP3C25 FPGA [94], containing approximately

25,000 logic gates, hosted on an Altera Starter Board. To use the Cyclone III FPGA

chip with Altium Designer Winter 09 software for compiling, synthesizing and

building of the FPGA project, we installed the USB blaster driver for the cyclone III

starter board to interface with a personal computer. The analog front end is provided

by a mating Terasic ADC/DAC card with dual high speed analog input and output

channels. Altera developed the specification for the HSMC (High Speed Mezannine

70


Card) to define and standardize the interface between optional daughter cards and host

boards.

5.4 High-Speed A/D and D/A Development Kit

The THDB_ADA (ADA) daughter board is designed to provide a high speed interface

for DE series, Cyclone III Starter Kit, or other boards with HSMC or GPIO interface

[95]. It is equipped with one ADC (Analog-to-Digital Converter) and one DAC

(Digital-to-Analog Converter), each providing dual-channel ports.

For our implementation, the ADA-HSMC package is used to work with Altera

Cyclone III FPGA starter kit. The package consists of the Terasic Analog-to-Digital

and Digital-to-Analog (ADA) board. This ADA board has dual AD channels with 14-

bit resolution and data rate up to 65 MSPS (Million Samples per Second), dual DA

channels with 14-bit resolution and data rate up to 125 MSPS (Million Samples per

Second) and dual interfaces include HSMC and GPIO, which are fully compatible

with the Cyclone III starter kit and DE1/DE2/DE3 respectively. The clock sources of

the ADA board include a 100 MHz oscillator [95], SMA clock input for AD and DA

each and a PLL input from either the HSMC or GPIO interface.

5.5 Implementation of the Modulator

The BPSK modulator is implemented in FPGA. The following five sections will

discuss how each of the individual blocks of the modulator - binary data bit

generation, upsample and dirac delta generation, sinusoid/carrier generation, root

raised cosine low pass filter and multiplication (as discussed in Section 4.2) is

implemented in FPGA. These components of the modulator are implemented in the

FPGA using Altium built in logic blocks as well as VHDL code.

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5.5.1 Binary Data Bit Generation

Our modem is implemented with a symbol (data) rate of 80 kbps. As shown in Figure

4.1, the modulator contains a binary data bit (0/1) generator. This block is

implemented in the FPGA using a look-up table (LUT) containing all the binary data

bits needed to transmit over the underwater communication channel. The FPGA board

master oscillator operates at 50 MHz [96]. Using built-in clock managers from the

Altium FPGA Generic Library; a 320 kHz clock frequency is generated from the

50 MHz clock as shown in Figure 5.1. The clock manager CLKMAN_1, is a single

operational generic digital clock manager [97]. This component provides a means to

generate a wide variety of clocks depending on the user's need at design time. The

CLKMAN_1 components are automatically linked with the Altium core generator

engine. Once an FPGA design containing this component is synthesized, the FPGA

device clock manager is automatically inferred in the design output before place and

route occurs. An 8-bit Altium built-in binary counter is used for dividing the clock of

320 kHz by 4 to generate a clock of 80 kHz. The binary data bit generation block is

written in VHDL code. For each clock pulse of the 80 kHz clock, a bit 0/1 is

generated from binary data bit generator block in the Altium schematic.

Figure 5.1: Binary Data Bit Generation in FPGA

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5.5.2 Upsample and Dirac Delta Pulse Generation

The next step of the modulation is to upsample the data bit for generating the dirac

delta pulse. Figure 5.2 shows the generation of dirac delta pulse from binary data bit

0/1. To generate a dirac delta pulse from binary input data, we first changed the

magnitude level of the binary input data generated from the binary data bit (0/1)

generator block (discussed in Section 5.5.1). For our FPGA implementation, a binary

data bit ‘0’ is represented by the magnitude level of -8000 (0xE0C0) and a binary data

bit ‘1’ is represented by the magnitude level of +8000 (0x1F40). The magnitude level

is chosen to confine the values within 14-bit resolution of ADC/DAC. The binary

representations of two different magnitudes +8000 and -8000 are

“0001111101000000” and “1110000011000000” respectively. Both these

representations have their least significant 7 bits common which are “1000000”. We

have changed only the upper 9 bits to reflect the corresponding magnitude level. To

change the magnitude level of binary data bit ‘0’ we first represent it as 9 zeros

(000000000) and then XORing it with “111000001” produces the upper 9 bits of the

desired magnitude level of -8000 (111000001). To change the magnitude level of

binary data bit ‘1’ we first represent it as 9 ones (111111111) and then XORing it

with 111000001 produces the upper 9 bits of the desired magnitude level of +8000

(000111110). Appending the remaining fixed 7 least significant bits “1000000” thus

produce the required magnitude level for binary data bits ‘0’ and ‘1’.

The upsampling is then done by inserting 49 zeros between consecutive symbols. The

dirac delta pulse train generated after upsampling is sent to the root raised cosine

filter for further processing.

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Figure 5.2: Generation of Dirac Delta in FPGA

5.5.3 Carrier Generation

The LUT for the sinusoid generator is implemented in Altium using a logic block

coded in VHDL. In the modulator, we store 5 samples in the LUT as our initial design

requires 5 samples per carrier cycle. Figure 5.3 shows the generation of carrier in

Altium. The sinusoid generation block is driven by a 4 MHz clock and, for each clock

pulse, one sample from the LUT is generated. The carrier generated from the LUT is

800 kHz. A 16 MHz clock is also generated from the 50 MHz FPGA master clock

using a clock manager CLKMAN_1 of the FPGA generic library as discussed in

section 5.5.1. An 8-bit Altium built-in binary counter is used for dividing the clock of

16 MHz by 4 to generate a clock of 4 MHz.

For this particular implementation, a carrier of 800 kHz is generated from the pre-

defined LUT. The samples stored in the LUT are generated in Matlab using equations

(i)-(iv) of Section 4.3.1.

Figure 5.3: Carrier Generation in FPGA

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5.5.4 Root Raised Cosine Low Pass Filter

As discussed in Section 4.2, our modulator uses a 101 tap low pass filter (root raised

cosine filter). Our demodulator also uses the same filter in the upper and lower

channels (I and Q - channels) of the Costas loop. These three identical filters are

implemented in the FPGA as a tapped delay line. But to avoid expensive multipliers,

we implemented the filter weights as a series of right shifts and additions.

The filter coefficients (<1) are generated in Matlab using the following function,

( )delayrflagtypeffinerb sd ,,_,,cos=

Each coefficient is then approximated as a summation of two inverse powers of two.

The rcosine function of Matlab designs a FIR raised cosine filter and returns its

transfer function. The digital input signal has sampling frequency . The sampling

frequency for the filter is . The ratio

df

sf ds ff must be a positive integer greater than 1.

The default roll off factor should be a real number in the range [0, 1]. The filter's

group delay, which is the time between the input to the filter and the filter's peak

response, is actually dfdelay seconds.

For our implementation, is 80 kbps and is 4 MHz, is ‘fir/sqrt’, df sf flagtype _ r is

0.4 and the delay is 1. So, we have generated our coefficients using the following

equation,

( )1 0.4, ,'sqrtfir' 50, ,1cos inerb =

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Since the data rate is symbolsamplesperf s and sampling rate is , multiplying the

data rate and sampling rate by

sf

sfsymbolsamplesper produce the data rate 1 and

sampling rate which is 50, for our implementation. symbolsamplesper

Each of the 101 taps of the filter is implemented by two right shifts and one addition

operation. All the operations in the filter are carried out on 16-bit signed numbers. As

mentioned in the previous chapter, using this right shift and addition techniques to

implement the filter operations consume considerably less FPGA resources rather

than doing the multiplications directly using FPGA multiplier blocks. In our

implementation, we avoid multiplication and quantize the coefficient as (2-x + 2-y),

where x and y are integers. For example, the original coefficient 0.78 is quantized as

(0.75 =2-1+2-2) to implement using 1 bit and 2 bit right shift operation in FPGA.

Figure 5.4 shows the implementation of one tap operation of the root raised cosine

filter using two right shift operations - x bit right shift and y bit right shift on the input

and then summing the results together. This avoids the need for an explicit

multiplication, which is expensive to perform in an FPGA.

Figure 5.4: FPGA Implementation of One Tap Filter

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Figure 5.5 shows the implementation of two taps of the filter as b(1)*x(2)+b(2)*x(1);

where b(1) is positive and b(2) is negative. Assume that b(1) is quantized and

approximated as x1 and y1 bit right shift operations and b(2) is quantized and

approximated as x2 and y2 bit right shift operations respectively. Since b(2) is

negative, the input x(m) is right-shifted according to x2 and y2 and then twos

complemented to produce -b(2)*x(m) and is sent to the next tap.

Figure 5.5: FPGA Implementation of Two Tap Filter

For each clock pulse, the input x(m) is right-shifted according to the filter coefficient

and then is fed to the next tap. If the coefficient is negative then the right-shifted input

is twos complemented before feeding to the next tap. We have implemented “5 taps

per schematic sheet”, except the last tap to simplify the design. This required 21

schematics (20 schematics each with 5 taps and one schematic for last tap) to

implement the 101 tap filter. The Altium built in Delay block (D flip-flop) is used to

delay the signal for one symbol period before sending it to the next tap.

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5.5.5 Multiplication

The carrier signal (generated from Sinusoid Generator) and the filtered signal are

multiplied to generate the BPSK modulated signal as shown in Figure 5.6. All the

blocks in the modulator are implemented in 16-bit twos complement resolution. So,

every sample of the carrier as well as the filtered signal is a 16-bit twos complement

integer. To multiply these two 16-bit samples, a signed 16-bit Altium built in

multiplier is used. This multiplier takes two 16-bit signed integers as input and

produces a 32-bit signed integer as the output. Since, our DAC works on unsigned

resolution, a 32-bit adder is used next to the 32-bit multiplier to change the scale of

the multiplied signal from signed to unsigned resolution. An optimization is carried

out at the output of the adder to send the most significant 14-bits (carrying most of the

information) to the DAC which is of 14-bit resolution.

Figure 5.6: Generation of Modulated Signal in FPGA

5.6 Implementation of the Demodulator

The demodulator has been implemented in the FPGA. The demodulator consists of

three multipliers, three low pass filters (two 101 tap root raised cosine filters - LPF 1

and one 5 tap Chebyshev Type II IIR filter - LPF 2), one hard limiter and a

numerically controlled oscillator (NCO) as discussed in Section 4.3. These

components are implemented in the FPGA using Altium built in virtual logic devices

78


as well as VHDL code. The following four sections will discuss the implementation

of the NCO, Root Raised Cosine low pass filters (LPF 1) in the I and Q channels (LPF

1), Chebyshev Type II IIR filter (LPF 2) in the feedback channel and a Hard Limiter.

5.6.1 LPF 1

Two identical 101 tap root raised cosine low pass filters (LPF 1) are used in the I and

Q arms of the Costas loop. This is the same filter used in the modulator since two

such root raised cosine filters (one at the transmitter and one at the receiver) produce

the effect of a raised cosine filter at the receiver. This section avoids detailed

discussion of the implementation of this 101 tap root raised cosine FIR filter since it

has already been covered in Section 5.4.4.

5.6.2 LPF 2

Our demodulator uses a 5 tap Chebyshev Type II IIR filter as the second filter (loop

filter) of the Costas loop. The cut off frequency of this filter is set to 10 times the cut

off frequency of the data filter (LPF 1) as mentioned in Chapter Four. The filter

output is calculated using the following equation:

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )( ) ( ) ( ) ( ) ( ) ( )342312

)4(5)3(423121−×−−×−−×−

−×+−×+−×+−×+×=myamyamya

mxbmxbmxbmxbmxbmy

To implement the filter in the FPGA, we have generated the filter coefficients in

Matlab using the following functions:

[ ] ( )RsRpWsWpordchebWsn ,,,2, = … … … (i)

[ ] ( )WsRsnchebyab ,,21,1 = … … … (ii)

79


The function in equation (i) returns the lowest order of the Chebyshev Type II filter

that loses no more than dB in the passband and has at least dB of attenuation

in the stopband. The scalar (or vector) of corresponding cut off frequencies Ws , is

also returned. The passband corner frequency Wp , the cut off frequency, is a scalar or

a two-element vector with values between 0 and 1, with 1 corresponding to the

normalized Nyquist frequency,

n

Rp Rs

π radians per sample and, Ws the stopband corner

frequency is a scalar or a two-element vector with values between 0 and 1, with 1

corresponding to the normalized Nyquist frequency. For data sampled at 4 MHz, a

Chebyshev Type II low pass filter with less than 3 dB of ripple in the passband

defined from 0 to 400 kHz, and at least 60 dB of attenuation in the stopband defined

from 1200 kHz to the Nyquist frequency (2 MHz) is designed for the Costas loop

demodulator. For our implementation, we have chosen = 3 and = 60 dB,

= 400000/2e6 and Ws = 1200000/2e6. The function in equation (i) returns = 4

and Ws = 0.6000.

Rp Rs

Wp n

The filter coefficients are generated using equation (ii) to design an order low pass

digital Chebyshev Type II filter with normalized stopband edge frequency Ws and

stopband ripple dB down from the peak passband value. It returns the filter

coefficients in the length

n

Rs

1+n row vectors, and . As shown in Figure 5.7, we

have implemented this IIR filter in FPGA as a tapped delay line in Altium Winter 09

using 16-bit signed multipliers, 32-bit adders and 16-bit D flip flops.

1b 1a

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Figure 5.7: FPGA Implementation of LPF 2

The binary values for the coefficients generated from Matlab are directly used in the

Altium schematic as wired lines to implement the filter. To avoid some unexpected

problems caused by Altium subtractors, we have replaced the subtraction operation in

the design by twos complement and adder operations. To do this, we have used 32-bit

Altium adders and VHDL code to perform the twos complement operation.

For our implementation, the filter coefficients generated from equation (ii) are

represented in 2:14 binary bit format where the upper 2 bits represent the integer part

of the coefficient and the lower 14 bits represent the fractional component of the

coefficient. The input signal is represented in 16:0 binary format to represent 16-bit

twos complement integer. The feedback coefficients a2 and a4 generated from Matlab

are negative. So, we did not need to use twos complement operation for negating

these two coefficients and we directly fed them to the 32-bit adders after multiplying

with 16-bit feedback coming out of the filter.

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5.6.3 NCO

As shown in Figure 5.8, the feedback error calculated from the output of LPF 2

multiplied by the Costas loop’s gain is added with the fixed step size (64.0/5 = 12.8)

using a 16-bit built-in adder in Altium. The 16-bit adder (Adder-A) takes the input as

a fixed point number in 8:8 format, where the upper 8 bits represent the integer part

and the lower 8 bits represent the fractional component. The 16-bit output coming

from Adder-A is also in 8:8 format and is added with the previous step size coming

from the 16-bit D flip-flop using another 16-bit adder (Adder-B). The output of

Adder-B is sent to a 16-bit multiplexer (MUX) to check the sign of this number. The

MUX checks the sign of the output of Adder-B and sends the number as is if the

number is positive or if the number is negative, it sends the number added with 64.0

(01000000 00000000) using Adder-C to a 16-bit comparator.

The comparator compares the output of MUX with 64.0 ie, 0100000000000000 in

binary (8:8 format) to confine the index of the LUT within the range of 1-64. The one

bit output of the comparator (0/1) is sent to an Expansion block implemented using

schematic wired lines to expand 1 bit to 16 bits. The Expansion block generates either

“0000000000000000” when the output of the comparator is ‘0’or

“1111111111111111” when the output of the comparator is ‘1’. The output of

Expansion block is ANDed with 64.0 to produce either 0/64.0 depending of the output

of comparator 0/1 respectively. To implement this AND operation, we have used a

built-in AND gate of Altium. The current phase value calculated by adding the

previous step size, current fixed step size and the output of LPF 2 is used to address

the index of both LUTs (Sine and Cos).

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Figure 5.8: Implementation of NCO in the FPGA

The SUB block in the Figure 5.8 subtracts either 0/64 from the current step size

calculated from the MUX to limit the index of the LUT. The output of the SUB block

is the current step size and the upper 8 bits of it is used to address the look-up tables

and sends all 16 bits to a 16-bit D flip-flop (latch) to be added with the next step size

for getting the next numerical value to address the LUTs. Two LUTs with 64 samples

in each are used in the NCO for generating sine-wave and cos-wave for the I and Q

channel respectively. These two LUTs are implemented in Altium using logic blocks

written in VHDL codes.

5.6.4 Hard Limiter and Multiplier

Two multipliers in the I and Q channel are implemented using Altium built in 16-bit

multiplier. Figure 5.9 shows the block diagram of FPGA implementation of the hard

limiter and the third multiplier in the Costas Loop. An OR operation is carried out

using Altium built-in OR gate on the 16 bit, binary signed output of the I-channel.

The OR operation decides whether the output of the I-channel is zero or not. The

83


output of the OR operation and the MSB of the I-output are sent to a logic AND gate

to check whether the I-channel output is positive or negative. The Altium built-in

AND gate is used to carry out this operation. The output of the AND gate and the

output of the OR gate are sent to a 2-to-4 bit decoder where D0 (Least Significant Bit)

output of the decoder goes high when the I-channel is zero. The output D3 (Most

Significant Bit) goes high when the I-channel is negative. Both D0 and D3 go to low

when the I-channel is positive. To carry out this decoding, an Altium built in 2-to-4

bit decoder is used. A Multiplexer (MUX 1) is used to forward the Q-channel output

or zero depending on the sign bit of the I-channel to the input of a second multiplexer

(MUX 2) as shown in Figure 5.9. The second multiplexer (MUX 2) either forwards

the Q-channel/zero (output of MUX 1) or the inverted Q-channel to the input of

LPF 2. Both multiplexers (MUX 1 and MUX 2) operate on 16-bit signed numbers and

are implemented using VHDL codes.

Figure 5.9: FPGA Implementation of Hard Limiter and Third Multiplier

84


5.7 Experimental Set-up and Test Results

The BPSK modem was implemented on the Altera Cyclone III FPGA starter kit [93]

and a Terasic ADC/DAC mezzanine card [95] as mentioned in the previous sections.

The FPGA board master oscillator operates at 50 MHz. Each design block of the

modem was built and validated separately. The experimental results from each

individual block were obtained at the output of the DAC in the THDB-ADA daughter

board on the Cyclone III starter Kit with HSMC interface and over a custom USB

interface.

5.7.1 Testing Individual Components

Each individual component of the modem was tested before integrating them. This

section discusses the test results obtained from the implementation of NCO and root

raised cosine low pass filter of the modem. The NCO output frequency depends on

the phase increment value calculated from the previous step size and the output of

loop filter (LPF 2). To test the NCO individually, a fixed look-up table with 64

samples representing a sine-wave was implemented in Altium.

Figure 5.10 (a) shows the sinusoid output of the NCO with frequency 390.6 kHz when

the step size (phase increment) of NCO was 0.5. For each clock pulse, the phase

accumulator scanned one sample value from the LUT for sine-wave (LUT_1). The

phase accumulator scanned 128 samples (each sample in the LUT was used twice per

cycle) from the LUT to generate the frequency of 390.6. The FPGA clock operates at

speed of 50 MHz. Dividing 50 MHz by 128 produced the desired frequency of 390.6

kHz.

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Figure 5.10(a): NCO Output with 0.5 Phase Increment

Figure 5.10 (b) shows the sinusoid output of the NCO with frequency 588.2 kHz

when the current step size (calculated from the output of LPF 2 and previous step

size) was 0.75. The NCO scanned 85 samples from the LUT. Dividing 50 MHz by 85

produced the desired frequency of about 588.24 kHz. The accuracy and stability of

NCO were driven from the crystal on the FPGA board.

Figure 5.10(b): NCO Output with 0.75 Phase Increment

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Figure 5.11(a) shows the frequency response of the root raised cosine filter (LPF 1)

used both in the transmitter and receiver of the modem. The coefficients of the filter

were generated from MATLAB.

Figure 5.11(a): Calculated Frequency Response with Original MATLAB Coefficients

Figure 5.11(b) shows the frequency response of root raised cosine filter (LPF 1) with

the quantized coefficients approximated in the FPGA to implement the multiplication-

free filter. The response of the filter was calculated in MATLAB using both the

original filter coefficients as well as FPGA quantized coefficients.

Figure 5.11(b): Calculated Frequency Response with Quantized FPGA Coefficients

Each tap of the 101 tap root raised cosine filter in our modem was implemented using

two right shifts and one addition operation to avoid expensive multiplication in the

FPGA. To do this, each filter coefficient was quantized to be represented as two

inverse powers of two. Each coefficient was then represented as two right-shifted

87


coefficients. The impulse response of the root raised cosine filter with original

MATLAB coefficients is shown in Figure 5.12(a).

Figure 5.12(a): Impulse Response with Original Filter Coefficients

The impulse response of the root raised cosine filter with quantized filter coefficients,

but using multiplication throughout, is shown in Figure 5.12(b).

Figure 5.12(b): Impulse Response with Quantized Filter Coefficients

The multiplication-free filter on the FPGA was implemented with the quantized

coefficients and the impulse response is shown in Figure 5.12(c). Our result shows

88


that the multiplication-free filters produce a similar frequency and impulse response

as filters implemented with multiplication but avoid the multiplication cost.

Figure 5.12(c): Impulse Response of Multiplication-free Filter with Quantized Coefficients

The impulse response of the root raised cosine low pass filter shown in Figure 5.12(b)

does not exactly match Figure 5.12(c) due to quantization error of the filter

coefficients. Figure 5.12(c) shows the impulse response of a multiplication-free filter

implemented as a series of right shift operations and is different from Figure 5.12(b)

since the right shift operation causes loss of some precision at the output signal. If the

need to exactly match the response of Figure 5.12(b) is found to be important, then

rounding rather than the truncation could be considered when right-shifting.

Figure 5.12(d) shows the impulse responses of Matlab calculated root raised cosine

low pass filter (LPF 1) using original coefficients, quantized coefficients and FPGA

implemented multiplication-free filter with quantized coefficients together. It is

clearly evident from the figures that our multiplication-free filter implemented as a

series of right shifts produces correct impulse response with very little loss of

precision.

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Figure 5.12(d): Figures 5.12(a), 5.12(b) and 5.12(c) Superimposed

5.7.2 Modem - Initial Verification using Square Pulse Input Signal

The initial implementation of the FPGA acoustic modem uses a BPSK modulation

scheme with a symbol rate 10% of the carrier frequency. The modulator is

synchronous, with the carrier generation, with data encoding and pulse shaping

operations driven by a single clock. There are an integer number of carrier cycles in

each symbol period at the selected carrier and symbol rates. This is used to simplify

the circuitry for decision directed carrier recovery. A Costas loop demodulator is used

to recover the carrier and demodulate the data bits at the receiver in this

implementation.

The design of the modulator was completed, and programmed into the FPGA. The

Matlab model of the demodulator was developed and tested on recordings of both

laboratory and open water signals. To test the modem performance, the binary data bit

generation block of the FPGA modulator generated a data packet of 62 bits to be sent.

The first 30 bits of the packet were used for carrier synchronization and the next 10

bits acted as a data preamble of the packet for bit synchronization at the receiver. The

packet contained 22 bits of actual data payload for transmission.

90


In order to verify the performance of the modulator, a 25 kl water-tank having

2.8 metre height and 3.5 metre in diameter was used as shown in Figure 5.13. A

transducer was used as the transmitter and a hydrophone was used as the receiver.

Both transmitter/transducer and receiver/hydrophone were about 1 metre below the

surface of water, and approximately 70 cm from the water-tank edge. The receiving

hydrophone was about 1 metre away from the transmitter.

The BPSK modulated signal generated in the FPGA was sent through a DAC front

end provided by the Terasic daughter board to an amplifier which in turn forwarded

the amplified signal to the transducer (transmitter). The receiving hydrophone

captured the signal and passed it through several preamplifiers. Finally the modulated

signal was recorded by a PC oscilloscope device and stored in a computer for later

demodulation using the MATLAB model of the demodulator. The BPSK signal

recorded at the tank was generated from an erroneous square pulse BPSK data rather

than Dirac Delta pulse. This was generated with our initial design of the modulator

which generated square pulse from the binary input bits, rather than the dirac delta.

Figure 5.13: Tank Set-up

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The transmitted packets were kept short (<1 ms), with an intervening silence of

approximately 20 ms between packets to minimize the effect of reflections within the

tank. A typical recording of the modulated signal in the tank is shown in Figure 5.14.

The signal was recorded using a Picoscope device and stored in a computer for

demodulation. The reverberation caused by reflections in the tank is clearly seen in

the figure. The 20 ms interval between packets proved sufficient gap for any

remaining echoes in the tank to die away.

Figure 5.14: Sample BPSK Modulator for 80 kbps at 800 kHz Carrier in Tank

The Matlab model of the Costas loop was coded and tested to demonstrate the ability

to achieve synchronization even with substantial simulated carrier and phase offsets.

The modulated signal recorded (shown in Figure 5.14) in tank was demodulated using

the closed Costas loop and the output of the I and Q channels are shown in Figure

5.15. The output of the I channel produced the expected demodulated data. Bit

synchronization was also been achieved successfully for this particular test setup at

tank.

It is evident from Figure 5.15 that the Costas loop was well locked after 1500

samples/30 bits (used for carrier synchronization and test instrumentation purposes)

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and the BPSK demodulated data was decoded from the I channel. The bit

synchronization was also achieved with 0% bit error for this particular recording. The

transmission was almost noise free but had noticeable reverberation after the data

packet.

Figure 5.15: Demodulated BPSK Signal for Tank Recording

Open water testing of the modem was carried out at Lake Burley Griffin, Canberra,

Australia as shown in Figure 5.16. The performance of the modem was tested using

both transmitter and receiver in one boat. The test was carried out with various

combinations of distances and depths of the transmitter and receiver.

Figure 5.16 shows the test set-up at lake with the receiving hydrophone about 1 metre

away from the transmitter to capture the modulated signal. Both transmitter and

receiver were about 3 metres below the surface of the water. The signal captured by

the hydrophone was passed to a pre-amplifier followed by an amplifier. Finally the

modulated signal was recorded by a PC oscilloscope device and stored in a computer

for later processing by the Matlab model of the demodulator.

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Figure 5.16: Lake Test Set-up with 1 m Distance

Figure 5.17 shows the modulated signal recorded with 1 metre distance between

transmitter and receiver. The signal was recorded using a Picoscope with sampling

rate of 160 ns, and resampled at 250 ns intervals for later processing.

Figure 5.17: Sample BPSK Modulator for 80 kbps at 800 kHz Carrier at Lake with 1 m Distance

The signal recorded from the lake was tested using the Matlab model of the open loop

demodulator and decoded successfully to recover the BPSK demodulated data. The

demodulated signal at the I channel and the error signal at the Q channel of the Costas

loop are shown in Figure 5.18. The Q channel does not go to zero in the figure. This is

because we deliberately ran the Costas loop with no feedback from the Q channel.

The NCO of the Costas loop was a free run oscillator (run with fixed constant

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frequency increment). This test was done to realize the behaviour of the open water

signal. Bit synchronization was achieved with 0% BER for this recording, because the

LO was only approximately 45o out of phase.

Figure 5.18: Demodulated BPSK Signal for Lake Recording with 1 m Distance

Figure 5.19 shows the BPSK modulated signal recorded in Lake Burley Griffin with 2

metre distance between the transmitter and the receiver. The test set-up was similar to

that shown in Figure 5.16 except for the distance between the transducer and the

hydrophone. This recording was taken by increasing the distance between transmitter

and receiver to check the maximum distance that we could cover with our modem.

The BPSK modulated signal captured by the hydrophone was passed to a preamplifier

and then to an amplifier. The final BPSK signal was recorded by a Picoscope for later

processing using MATLAB model of the demodulator.

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The modulated signal recorded from the test set-up in lake with 2 metre distance

between transducer and hydrophone is shown in Figure 5.20. The modulated signal

recorded by increasing the distance between transmitter and receiver still had

sufficient SNR to be decoded by the decoder.


Figure 5.21 shows the output of the I and Q channel of the Costas loop for the BPSK

recorded signal with 2 metre distance between transducer and hydrophone at lake. The

bit synchronization follows on from the carrier recovery after the loop is locked. The

recorded signal was decoded here with the open loop Costas loop demodulator to test

the shape and behavior of the I and Q channel signals as shown in Figure 5.21. Bit

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synchronization was carried out with 0% bit error rate. Again the receiver local

oscillator was allowed to free run.


Another recording was taken in the lake with 10 metre distance between the

transmitter and the receiver as shown in Figure 5.22. The test set-up was also similar

to that shown in Figure 5.16 except for the distance between the transmitter and the

hydrophone.


A typical recording of the modulated signal is shown in Figure 5.23. The recorded

signal is much more noisy than the signal recorded with <10 metre distances.

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Figure 5.24 shows the I and Q signal generated from the Matlab model of the open

loop demodulator. The decoding was also done with 0% BER. In this case the LO

offset was small.


The lake experiments were carried out for through-water transmission ranges from

1 metre to 20 metres. Figure 5.25 shows the signal-to-noise ratio of the modulated

signal calculated to test the signal power as the distance between transmitter and

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receiver was increased. The x-axis represents the distance between the transmitter and

the receiver and y-axis represents the SNR calculated from the recording of the

modulated signal in the lake.

Figure 5.25: Distance between Transmitter and Receiver vs SNR

It is evident from the above figure that the SNR decreases as the distance increases,

with one exception at 2 metre where a much stronger signal was received. The SNR

was very poor for weak signals recorded at 6, 11 and 12 metre distances. These might

be explained by interference for the transmitter framework. The decreasing nature of

the SNR with respect to the distances was due to the limited transmission power of

the amplifier we used to transmit the signal.

Figure 5.26 shows the absorption and spreading loss at fresh water from 1 metre to

20 metre distances between the transmitter and the receiver. The total loss calculated

is also shown in the graph. The figure shows that we should get 10 dB more spreading

loss, plus an extra 4 dB of absorption or an SNR that was 14 dB lower as the link

distance was increased from 5 to 20 metres.

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Figure 5.26: Range vs Loss in Fresh Water at 800 kHz

The next test plan was to record the signal for a long duration to capture a large

number of packets and to eliminate the biasness of strong packets. We also changed

the amplifier to record the signal with more transmission power and used two boats

for separating the transmitter and the receiver.

Another test was carried out in Lake Burley Griffin, Canberra, Australia as shown in

Figure 5.27 using two boats and a new amplifier. The transducer and the hydrophone

were about 2.7 metre and 3 metre respectively below the surface of water. This tested

the modem performance by transmitting from one boat to another to cover ranges up

to 50 m. The performance of the modem was tested using various combinations of

distances (between transmitter and receiver) and depths of transmitter and receiver.

Signals were recorded at ranges between 10 m and 50 m. SNR and bit error rates were

also calculated as a function of link range.

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Figure 5.27: Lake Test Set-up using Two Boats

Figure 5.28 shows the band-pass filtered received modulated signal recorded in the

lake with 15 m distance between transmitter (depth 2.7 m) and receiver (depth 3 m).

The figure shows 1 second of signal collection, containing approximately 10 packets,

each packet with 22 actual data bits. The signal was recorded using a PC based CRO

(Cleverscope) with sampling rate of 220 ns, and resampled at 250 ns intervals for

post-processing using Matlab model of the demodulator. The bandpass filter was

narrow, capturing the long sequence of unmodulated signal in the packet preamble.

Figure 5.28: Sample BPSK Modulator for 80 kbps at 800 kHz Carrier in Lake for 15 m Distance

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Figure 5.29 shows the output of the I and Q channel of the Costas loop for a noisy,

band limited BPSK recorded signal for 15 m distance between transducer and receiver

in lake. The bit synchronization follows on from the carrier recovery after the loop is

locked. The demodulated data was obtained from the I channel after the loop was

locked (carrier is recovered). It is observed from the figure that the Costas loop

demodulator performs well at regenerating the carrier as long as we have strong SNR

input.

Figure 5.29: Demodulated Data along with I and Q for 15 m Distance in Lake

Though the pattern of I and Q signals in Figure 5.29 is random, the Costas loop was

locked and data bits were detected with bit error rates down to 4.76%. This data was

affected by an AM radio signal at 846 kHz, broadcast from a radio tower (Black

Mountain Tower, Canberra, Australia), about 2 km from the test site as shown in

Figure 5.30. Upon investigation it was determined that the interference was

transferred into the received signal as a result of inappropriate earthing in the CRO

device.

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Figure 5.30: Black Mountain Tower, Lake Burley Griffin, Canberra, Australia [98]

Although the communication was tested for up to 50 metres, the I and Q plots are

shown for up to 30 metre distance. Figure 5.31 shows the demodulated data along

with the I and Q response of the Costas loop for 20 metre distance in open water. The

PLL was locked and demodulated data bits were obtained with 4.76% BER.

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Figure 5.32 shows the I and Q channel data of the Costas loop for signals recorded at

30 metre distance in open water. The BER obtained for this recording was 23.8%,

driven in large part by the AM radio interference.


The FPGA design of the modulator is easily adaptable to other carrier frequencies and

symbol rates. Tests in the open water were conducted to verify the modem

performance with various communication distances between transmitter and receiver.

A better understanding of the propagation characteristics of high frequency acoustic

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signals and their impact on the quality of communication channel quality were also

obtained from these lake trials.

5.7.3 FPGA Modem

The modulator and demodulator were completed and programmed into FPGA. Each

of the individual blocks of the modulator and demodulator was previously tested and

validated. This modulator design in FPGA follows the standard approach, where data

should be a series of dirac delta's spaced at the symbol rate - rather than a square wave

and this signal was then pulse shaped in the root raised cosine 101 tap filter. Using

dirac delta pulse to generate the modulated signal changes only in the amplitude

levels of the signal, which does not make much difference in BPSK where amplitude

levels are not important but does make the transmission power less variable.

The FPGA demodulator was also tested individually by storing the modulated signal

in a VHDL file and then using this signal as the input of the demodulator. The

operations of the demodulator were synchronous with the modulator, and carrier

recovery was achieved successfully.

A bench test was carried out to record the FPGA modulated signal in the lab. To test

the FPGA modem in the lab, we generated the BPSK modulated signal in one FPGA

Cyclone III board and then sent it to the DAC channel-A of that board. The analog

signal coming out of the DAC was sent to ADC channel-A of another FPGA Cyclone

III board. The ADC converted the signal back to digital. The digital signal was then

sent to the Costas loop for demodulation.

Figure 5.33 shows the BPSK modulated signal recorded in lab using one FPGA

board. The modulated signal was sent to an FPGA board and then recorded using a

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USB device. This recording contained 8 packets with each packet containing 62 bits

of same data bits. The packet duration was 0.775 ms and the gap between two

consecutive packets was also same as the packet duration.

Figure 5.33: Sample BPSK FPGA Modulator for 80 kbps at 800 kHz Carrier in Lab: Recording 1

The modulated signal containing one packet recorded using a Picoscope in the lab is

shown in Figure 5.34. The packet contains 62 bits, with 30 bits for carrier

synchronization, 10 bits for bit synchronization at the beginning and 22 bits: 1 0 1 1 0

0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 of actual payloads.

Leve

l

TimeFigure 5.34: BPSK Modulated Signal (One Packet) for 80 kbps at 800 kHz Carrier in Lab: Recording 1

106


Figure 5.35 shows the BPSK modulated signal transmitted from one FPGA board to

another in Lab. This recording had the same signal shown in Figure 5.33 using one

FPGA board, and contained 8 data packets, each with 62 bits/3100 samples. The ADC

only changed the magnitude of the modulated signal and plotted it in different scale.

Figure 5.35: BPSK Modulated Signal for 80 kbps at 800 kHz Carrier in Lab using

Two FPGA Boards: Recording 1

Figure 5.36 shows one packet of BPSK modulated signal recorded in lab using two

FPGA boards - one board acted as a transmitter and the other one as a receiver.

Figure 5.36: BPSK Modulated Signal (One Packet) for 80 kbps at 800 kHz Carrier

in Lab using Two FPGA Boards: Recording 1

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Figure 5.37 shows the demodulated signal of the bench recording as shown in Figure

5.35.

Figure 5.37: Demodulated BPSK Signal for Bench Test: Recording 1

Figure 5.38 shows one packet of the demodulated signal of the bench recording as

shown in Figure 5.37.

Figure 5.38: Demodulated BPSK Signal (Zoom in) for Bench Test: Recording 1

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Figure 5.39 shows another recording of the modulated signal containing 15 packets,

each with 20 bits.

Figure 5.39: Sample BPSK FPGA Modulator for 80 kbps at 800 kHz Carrier in Lab:

Recording 2

Figure 5.40 shows zoom in view of one packet of the modulated signal recorded in

Figure 5.39. The packet contains data sequence of - 1, 1, 0, 1, 0, 0, 1, 0, 1, 0 with 5

bits for carrier synchronization and 5 bits for data preamble at the beginning.

Figure 5.40: BPSK Modulated Signal (One Packet) for 80 kbps at 800 kHz Carrier in Lab:

Recording 2

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Figure 5.41 shows the demodulated signal of the closed FPGA demodulator (Costas

loop) for the modulated signal of Figure 5.39.


Figure 5.42 shows I and Q channel responses of the Costas loop for one packet (20

bits) of the modulated signal. The loop was locked after almost 5 bits/250 samples

and the Q signal oscillated around zero after this point forward.


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Figure 5.43 shows the BPSK modulated signal transmitted from one FPGA board to

another in the lab. The recording contained 8 packets, each with 62 bits/3100 samples.

This packet contains different data bits from the packet shown in Figure 5.36.

Figure 5.43: Sample BPSK FPGA Modulator for 80 kbps at 800 kHz Carrier in Lab:

Recording 3 Figure 5.44 shows one packet of BPSK modulated signal recorded in lab using two

FPGA boards - one board acted as a transmitter and the other one as a receiver.

Figure 5.44: BPSK Modulated Signal (One Packet) for 80 kbps at 800 kHz Carrier

in Lab: Recording 3

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Figure 5.45 shows the demodulated signal of the bench recording as shown in Figure

5.43.


Figure 5.46 shows one packet of the demodulated signal of the bench recording as

shown in Figure 5.45.


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The observation found from the analysis shows that the proposed FPGA modem is

able to operate at high frequency for short range communication. Though the

recording from the lake shows interference on recorded signal, but still those

recordings were decodable with some BER.

5.8 Constellation Diagram of BPSK

A constellation diagram [99] is a graphical representation of a digitally modulated

signal. The signal is displayed as a two dimensional scatter diagram in the complex

plane at each sampling instance of the symbol. Visually the constellation diagram

shows the phases of the symbols and their relationship to each other. The x-axis of the

diagram represents the in-phase component and the y-axis represents the quadrature

component of the symbol. The distance between signals on a constellation diagram

indicates how different the modulation waveforms are and how well a receiver can

differentiate between all possible symbols in the presence of noise.

A constellation diagram helps to design a transmission system which is less prone to

error. This diagram helps to design error correction and error detection schemes to

recover from transmission problems and can be used to recognize the type of

interference and distortion in a signal. The noise/corruption in the transmission

channel and receiver may cause the received symbol to move closer to another

constellation point than the one transmitted. Figure 5.47 shows the constellation

diagram for the BPSK signal. The positions of the constellation points can be

anywhere in the diagram though the figure shows all the points in x-axis at 0o and

180o phase.

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Figure 5.47: Constellation Diagram of Ideal BPSK Signal

Figure 5.48 shows the constellation diagram of our BPSK signal for one packet

(shown in 5.36) with 22 bits of actual payloads. The x-axis represents amplitude of

each sample in the I-signal (in-phase component) and y-axis represents the

corresponding sample amplitude in the Q-signal (quadrature component). As long as

the constellation point of one symbol does not cross the vertical boundary along zero

axis, the feedback error to the NCO is small enough to detect correct bit/symbol at the

receiver.

Figure 5.48: BPSK Signal (One Packet) Constellation Diagram

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5.9 Lock-on Characteristics of the Costas Loop

In order to demodulate the signal, the PLL at the receiver tracks the phase of the

received signal which can be shifted from that of the transmitter due to transmission

delay. If the received incoming signal has a phase lag of θ in relation to the signal

generated by the local oscillator (LO), the phase offset (Phase of the local carrier -

Phase of the incoming received signal) is positive which means that the feedback error

to the NCO is negative which decreases (negatively increases) as the phase shift or

phase delay increases. This directs the NCO to slow down to reduce the phase delay

between the incoming and local signal. On the other hand, if the received signal has a

phase lead of θ in relation to the locally generated carrier, the phase offset is negative

which means that the feedback error to the NCO is positive. The positive feedback

error speeds up the NCO to adjust the phase difference. The stable locking point of

the Costas loop is where the phase difference between the incoming signal and locally

generated signal is zero.

Figure 5.49 shows the phase offset characteristics between the incoming and locally

generated signal of the Costas loop. The x-axis represents the phase difference

between the locally generated signal and the received signal and y-axis represents the

feedback error to the NCO.

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Figure 5.49: Phase Offset Characteristics of the Costas Loop

The receiver also needs information about the frequency offset, ∆f of the received

signal, which can be caused by Doppler shifts due to motion, or the fact that the

transmitter oscillator is not exactly equal to that of the receiver. If the frequency seen

by the receiver fr is higher than the frequency of the locally generated carrier fc, the

feedback error to the NCO is positive. It speeds up the NCO by decreasing the step

size, which defines the frequency to lock in frequency. If the frequency of the

received signal is smaller than the frequency of the locally generated carrier, the

feedback error is negative. It slows down the NCO by increasing the step size to lock

in correct frequency.

Figure 5.50 shows the frequency offset characteristics between the incoming and

locally generated signal of the Costas loop. The x-axis represents the frequency

difference between the received incoming signal and the locally generated carrier and

y-axis represents the feedback error to the NCO. The feedback error increases as the

frequency difference between the received signal and locally generated signal

increases and vice versa. The stable lock point (feedback error is zero) is found when

the frequency difference is zero.

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Figure 5.50: Frequency Offset Characteristics of the Costas Loop

Our Costas loop demodulator can acquire lock to the incoming signal and adjust the

phase of the locally generated signal to match it in phase. The loop does not directly

track the frequency of the received waveform. As the frequency is a rate of change of

phase, the loop has some ability to track frequency, such as a Doppler shift or a

difference in clock frequency between the transmitter and the receiver, by making

constant phase adjustments.

5.10 Summary

This chapter introduces Altium Design environment and gives the detailed description

of the implementation of the proposed high frequency FPGA modem for underwater

communication. All the necessary blocks needed to implement the modem in Altium

Winter 09 software are also given in this chapter. A general discussion about Altera

Cyclone III - the FPGA device needed to map the Altium design into the FPGA board

has also been carried out in this chapter. This chapter also analyzes the performance

of this modem. The observations obtained from different test results have also been

covered.

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Chapter Six Summary and Conclusion ----------------------------------------------------------------------------- 6.1 Summary The primary target of this thesis was to design and develop a high frequency FPGA

acoustic modem for underwater communications. Many ideas have been proposed in

the literature to provide modulation and demodulation for underwater communication.

Some of those have been explored in this dissertation. The noticeable feature observed

in most of the existing underwater communications modem is their low operating

frequency to minimise absorption. Design of a high frequency modem is necessary to

take advantage of high frequency acoustic signals, which offer high channel

bandwidth and better channel quality. As high frequency signals suffer from a high

absorption rate, only short range communication can be achieved on each link at high

frequency. To achieve high frequency, short range underwater communications, a

novel design idea for an FPGA modem has been proposed in this thesis. The modem

is designed to support BPSK modulation and demodulation, with coherent detection.

The modem is implemented completely in the FPGA to take advantage of the benefits

of reconfigurable computing. This distinguishes it from most of the existing

underwater modems which are implemented in DSP. The detail design and

implementation of the BPSK modem is covered in this thesis with some test results.

The modulator is built to generate the BPSK modulated signal. The demodulator is

also built in the FPGA to demodulate the BPSK modulated signal generated from the

modulator. Both the modulator and demodulator use 101 tap root raised cosine pulse

shaping FIR filter and each of the 101 taps of the filter is implemented as two right

Chapter Six: Summary and Conclusion

shifts and one addition operation in the FPGA to avoid expensive multiplication

operations, which in turn leads to reduced FPGA resource consumption. The

demodulator uses a Costas loop for both carrier recovery and synchronous data

detection within the loop.

The modem has been implemented in a Cyclone III EP3C25 FPGA based on an

Altera Starter Board. The EP3C25 contains approximately 25,000 logic gates. The

modulator uses 3,623 (15%) and the demodulator uses almost 7,936 (32%) of the

available logic gates. Initially, the modulator was implemented in the FPGA, to

support laboratory and open water tests, the results of which conform to modelling.

The Matlab model of the demodulator then recovered the carrier, code

synchronization and data from recordings of both laboratory and open water tests.

Coding of the demodulator into the FPGA has then been completed and the

performance and behaviour of the modem was evaluated.

6.2 Conclusion This thesis documents the design and FPGA implementation of a high data-rate

software-defined BPSK acoustic modem for underwater communication. The novelty

behind the design of the modem is the high operating frequency supported which is an

order of magnitude higher than conventional underwater acoustic modems. At such

high frequencies, much higher data rates can be achieved at relatively short

communication range. This high data rate enables new applications, and longer range

communication can be enabled by relay or non-acoustic backhaul.

The software implementation of the BPSK modem allows us to avoid the cost of

specialized hardware and makes modification of the design easier. In addition, the

filter implementation using right shifts and addition avoids multiplication which

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would consume considerable resources on an FPGA. Implementation of filters

without multiplier blocks also makes the design suited to low power devices. The low

number of logic gates used in the FPGA also reduces the implementation cost of the

modem. The potential offered by a reconfigurable FPGA is a promising platform to

support more robust signal processing or communication systems. The modem does

all its processing in the digital domain and thus provides flexibility. Test results

obtained from bench, tank and open water revealed that our low cost, software defined

FPGA modem is suitable for high frequency, short range communication.

The thesis required multi-disciplinary knowledge from underwater acoustic

communications, digital signal processing and FPGA programming. A Matlab model

of the modulator and demodulator was simulated and verified before implementing

the modem in FPGA.

6.3 Future Work The current work deals with developing a FPGA acoustic modem targeted for high

frequency short range underwater communications. There are further improvements

that can be suggestions for future research.

The data/symbol rate chosen for the initial design is 80 kbps and each symbol

contains 50 samples. Although this data rate is modest, there is ample scope to

increase the symbol rate and bits per symbol - especially if the channel is as

benign as initial measurements indicate.

The modem is designed to modulate and demodulate only the BPSK data. The

demodulator uses the Costas loop to reconstruct the carrier and to synchronize

the data bits. Features can be added to make demodulator more tolerant of

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channel effects and to support a wide range of data rate and modulation

schemes.

Though the design was targeted for 100 m distance, only 30 m distance

communication was demonstrated in open water with our current working

modem. Testing the modem in water to cover large distances can be a future

scope.

The current implementation of our FPGA modem implements each filter

weight using 2 right shift operations. This is simply our initial design choice

and more accuracy can be obtained using more than 2 right shifts for each tap

if sufficient FPGA resources are available. Likewise some right shifts could be

removed to further reduce the number of logic gates used in the design.

The bit synchronization is simulated in MATLAB in the current design.

Implementing this part in the FPGA is our future goal.

The present work can be used to support a high data rate MAC layer protocol

for underwater communications.

Further development of high frequency underwater communications acoustic modem

concepts is still an open research area. Such modems promise to provide high data

rate networks in the underwater environment. Much research is going on and some of

the problems are addressed to be solved in future to improve the communication

efficiency.

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132

Appendix A Sample Schematics and VHDL Files -----------------------------------------------------------------------------

The BPSK modem is implemented in Altium Winter 09 using built in virtual logic

devices as well as VHDL code. The modulator and the demodulator have been

implemented in two different FPGA project files. The FPGA project file of the

modulator contains some schematics and VHDL files required to implement the

modulator. The FPGA project file of the demodulator as well contains some

schematics and VHDL files to implement different blocks of the demodulator. Each of

the schematics within a project file is designed to implement a small block of the

whole design to reduce design complexity.

A constraint file is also used to store design and implementation specific constraints

for the implementation. This file defines the design constraints (specifying a port to be

a clock) and pin allocations of the FPGA. The following sections will show some of

the schematics, VHDL files and a snapshot of the constraint file used in our BPSK

modem design.

A.1 FPGA Schematic of the BPSK Modulator

A sample schematic of the FPGA Modulator Modulator_Fpga.SchDoc is shown in

Figure A.1. This schematic has several Sheet Symbols, each of which implements a

small function of the modulator.

Appendix A: Sample Schematics and VHDL Files

Figu

re A

.1: F

PGA

Sch

emat

ic o

f the

BPS

K M

odul

ator

134


A.2 Defining Logic Constants

The following portion of the schematic Modulator_Fpga.Schdoc is used to define

logic constants (binary ‘0’ or ‘1’). The logic constant is obtained using Altium wire

‘A’.

Figure A.2: Defining Logic Constants

This logic block is implemented in Altium using a VHDL code Logicblock.vhd. A

small portion of the code is shown in Figure A.3.

//Logicblock.vhd

Library IEEE; Use IEEE.Std_Logic_1164.all; use IEEE.std_logic_unsigned.all; entity Logicblock is port ( Loggic1 : out std_logic; Loggic01 : out std_logic; Loggic02 : out std_logic ); end entity; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- architecture Structure of Logicblock is begin Loggic1 <= '1'; Loggic01 <='0'; Loggic02 <='0'; end architecture; -------------------------------------------------------------------------------- Figure A.3: VHDL Code to Define Logic Constants

135


A.3 Packet Transmission and Pause Time

The following block of the schematic Modulator_Fpga.SchDoc is used to define the

transmission time of the data packet and the time interval between transmissions of

two consecutive data packets. The output of this block labeled ‘C’ is used to define

the number of clock cycles we need the FPGA clock to enable or disable.

Figure A.4: Defining Packet Transmission and Pause Time

A small portion of the VHDL code test.vhd used to implement this part is shown

below.

//test.vhd

Wait until clk'event and clk='1'; if(check = 1) then if (counter1 = "1001011101011110") then --0.775 ms packet transmission time -- if(counter1 = "0011000011010100") then --20bits counter1:="0000000000000001"; check := 0; else counter1 := (counter1 +'1'); --increment counter. flag<end if;

='1' ;

else if (counter2 = "00000000000000001001011101011110") then -- for 0.775 ms delay between packet transmission counter2 := "00000000000000000000000000000001";

136


k := 1; chec else counter2 := (counter2+'1'); flag <= '0'; end if;

end if;

Figure A.5: VHDL Code to Define Packet Transmission and Pause Time

A.4 Clock Division

The following portion of the schematic Modulator_Fpga.SchDoc shows the

generation of 16 MHz and 320 kHz clocks respectively from the FPGA master clock

of 50 MHz. The clock of 16 MHz is obtained from the wire labeled ‘D’ and the clock

of 320 kHz is obtained from the wire labeled ‘E’ as shown in Figure A.6.

Figure A.6: Clock Division

137


A.5 Carrier Generation

Figure A.7 shows the generation of carrier signal in Altium. The counter (U1) is used

to divide the 16 MHz clock labeled ‘D’ by 4 to generate 4 MHz clock labeled ‘G’ for

the VHDL implemented logic block LUT.vhd. This block implements a counter which

counts through the samples in a SIN LUT implemented in a VHDL file

LUT_Carrier.vhd. The output of this SIN LUT is the carrier signal obtained at data

bus ‘F’.

Figure A.7: Carrier Generation

138


A small portion of the VHDL code LUT.vhd and LUT_Carrier.vhd is shown in Figure

A.8.

//LUT.vhd

shared variable Counter: std_logic_vector(5 downto 0) := "000000"; begin process begin Wait until CLK'event and CLK='0'; -- Count up on every negative edge of the clock IF (counter = "000100") THEN counter := "000000"; --counters through 4 address locations ELSE counter := (counter + '1'); --storing the sine wave lookup table END IF; count_out <= counter; --Set bits of output count_out to value of counter variable END Process;

end architecture;

…………………………………………………………………………………………………………………………………………………………………………………………………………

………

// LUT_Carrier.vhd

begin process (address) begin case ddress is a when "000000" => data <= my_rom(0); when "000001" => data <= my_rom(1); when "000010" => data <= my_rom(2); when "000011" => data <= my_rom(3); when "000100" => data <= my_rom(4); when others => data <= "0000000000001111"; end case; end process;

end architecture behavioral;

Figure A.8: VHDL Code for Carrier Generation

139


A.6 Binary Data Bit Generation

The following part shows the binary data bit generation block of the modulator in

Altium. The clock of 320 kHz obtained from Figure A.6 is used in the input of a

binary 8-bit counter which is triggered by a clock enable input labeled ‘C’.

Figure A.9: Binary Data Bit Generation

The VHDL block Logicblock3.vhd implements a counter which counts through the

LUT implemented in a VHDL file Cacode_62.vhd, which stores the binary data bits.

The output ‘H’ of the VHDL logic block Cacode_62.vhd is the binary data bits. These

two VHDL blocks are implemented using the same logic of LUT.vhd and

LUT_Carrier.vhd as shown in Figure A.8.

A.7 Changing the Magnitude Level

Figure A.10 shows the schematic which changes the magnitude level of binary data

bit ‘0’ by the magnitude level of -8000 and a binary data bit ‘1’ by the magnitude

level of +8000. This portion of the schematic Modulator_Fpga.Schdoc is

implemented using Altium built-in XOR logic gate. The input in the following figure

is the output of Figure A.9 and labeled as ‘H’. The logic constant ‘C’ is obtained from

the block in Figure A.2. The output of this block labeled ‘K’ is the 16-bit binary

representation of +8000/-8000.

140


Figure A.10: Changes of the Magnitude Level

A.8 Upsample and Dirac Delta Generation

Figure A.11 shows the upsample and Dirac Delta generation from the output labeled

‘K’ obtained from Figure A.10. The Dirac Delta generated from this block labeled ‘L’

is sent to the input of the Root Raised Cosine 101-tap low pass filter.

141


Figure A.11: Upsample and Dirac Delta Generation

A.9 Sample Schematic of the LPF 1

A portion of the FPGA schematic Filter_modulator.SchDoc of the 101 tap Root

Raised Cosine Filter (LPF 1) is shown in Figure A.12. Each green block in the figure

implements a 5 tap of LPF 1. The input signal labeled ‘L’ is obtained from Figure

A.11, the clock signal ‘G’ for the filter is obtained from Figure A.7 and the clock

enable signal ‘C’ is obtained from Figure A.2.

142


Figure A.12: FPGA Schematic of LPF 1

A.10 Sample Schematic of One Tap of LPF 1

Figure A.13 shows the FPGA schematic of the one tap of LPF 1 filter. Each tap of the

filter is implemented as two right-shifts and one addition operation. The input labeled

‘X’ is right-shifted based on the filter co-efficient. The output ‘Y’ of each tap is added

with the delayed version of the previous input ‘Z’. The delay is implemented in

Altium using built in logic block “FD16CEB” as shown in Figure A.13.

143


Figure A.13: FPGA Schematic of One Tap LPF 1

To implement negative coefficients, twos complement operation is carried out in the

implementation. This block is implemented in separate schematic

Tcomplement.Schdoc in Altium as shown in Figure A.14. The input signal is inverted

and then added with ‘1’ using Altium built in adder “ADD16B” to get the twos

complemented output.

144


Figure A.14: FPGA Schematic of Twos Complement

A.11 Generation of Modulated Signal

Figure A.15 shows the final multiplication which is carried out between the carrier

signal ‘F’ and the filtered signal ‘Y’ in Altium. The built in virtual logic block of

Altium “MULT16B” is used to multiply these two signals. An offset ‘O’ is added to

this signal using another virtual logic block “ADD32B” to change the scale into the

unsigned magnitude. The 14-bit modulated signal is sent to DAC for transmission.

Figure A.15: Multiplication and Generation of Modulated Signal

145


A.12 Sample Schematic of the Demodulator

The demodulator is implemented using several schematics and VHDL codes in

Altium. A portion of the FPGA schematic Demodulator_FPGA.SchDoc of the BPSK

demodulator is shown in Figure A.16. This schematic has several Sheet Symbols,

each of which implements a small function of the demodulator. The modulated signal

labeled ‘M’ is sent to a sheet symbol Demodulator.SchDoc which implements the

Costas loop. The demodulated signal ‘P’ is sent to the DAC for bit detection.

Figure A.16: FPGA Schematic of the Demodulator

A.13 Reading Incoming Signal using ADC

The modulated signal is received using ADC channel A of the FPGA board. This

signal is the input of the Costas loop demodulator. Figure A.17 shows the portion of

FPGA schematic which reads modulated signal using ADC channel A.

146


Figure A.17: Reading Modulated Signal using ADC

A.14 Multiplication of Incoming Signal and Carrier

The incoming modulated signal ‘M’ is multiplied by the carrier signal and 900 phase

shifted carrier signal generated from the NCO at the upper and lower loop of the

Costas loop respectively. Figure A.18 shows the portion of the schematic in the

demodulator which does this function. Two multiplications at the I and Q channel of

the Costas loop are carried out using Altium 16-bit built in multiplier. The outputs of

these multipliers ‘L1’ and ‘L2’ respectively are sent to the LPF 1 in both of the I and

Q-channels for filtering. This is the same filter used in the modulator. The schematic

of these filters is already discussed in A.9 and A.10. The following figure also shows

the schematic block of NCO which is implemented in a separate schematic diagram.

147


Figure A.18: Multiplication of Incoming Signal and Carrier

A.15 Sample Schematic of the NCO

The feedback error calculated from the output of LPF 2 labeled ‘F’ is multiplied by

the Costas loop’s gain and is added with the fixed step size (64.0/5 = 12.8) using a 16-

bit built-in adder “ADDR16B” in Altium. The output of this adder is added with the

previous phase value ‘F’ using another 16-bit adder “ADD16B”. Figure A.19 shows

the portion of the schematic NCO_Modem.SchDoc which is used to carry out this

operation. A 16-bit MUX is used to check the sign of the output coming out of the

second adder. This MUX is implemented in Altium using a VHDL code MUX3.Vhd.

148


The output of the MUX labeled ‘V’ is sent to a 16-bit Altium built in comparator

“COMPM16B” which is used to check whether the index of the LUT is within the

range of 1-64. The second input of the comparator is 64.0 and is labeled as B.

Figure A.19: NCO Operation: Part-1

A portion of the VHDL code to implement MUX is shown in Figure A.20.

149


//MUX3.vhd

architecture behav1 of MUX3 is begin process(sel) begin for i in 15 downto 0 loop c(i) <= (a(i)and not sel) or (b(i) and sel); end loop; end process; e nd behav1;

Figure A.20: NCO Operation: Part-1(VHDL Code)

Figure A.21 shows the potion of the schematic which expands 1-bit output of the

comparator to 16-bit using Altium built in AND gate “AND2S”. The AND operation

is carried out between the output ‘A’ and the second input of the comparator as shown

in Figure A.20 is The 16-bit output of the expansion block is obtained at the output of

this figure labelled ‘D’.

150



Figure A.22 shows the subtraction operation of the NCO to subtract 0/64 from the

current step size calculated from the MUX labelled ‘V’. This operation is carried out

using Altium built in 16 bit Adder-Subtractor “ADSU16B”. The upper 8-bits of the

current step size are taken using Altium wired lines and lower 8-bits (fractional part)

are compared using Altium built in 16-bit comparator “COMP16B” with 0.5. The

output of this comparator is sent to an adder “ADD16B” to get the current index

labelled ‘I’ of the LUT.

151



Figure A.23 shows the implementation of Sine and Cos LUTs in Altium using VHDL

codes Sin_table.vhd and Cos_table.vhd respectively. A small portion of the VHDL

code to implement SIN LUT is shown in Figure A.25. The COS LUT was

implemented using the same logic as the SIN LUT.

152



//Sin_table.vhd architecture of RO is behavioral M3 type is array ( 1 to 64) of std_logic_vector(15 downto 0); mem constant my_Rom : mem := ( 1 =>"0000000000000000", 2 =>"0000001100100011", 3 =>"0000011000111110", 4 =>"0000100101001010", 5 =>"0000110000111111", 6 =>"0000111100010101", 7 =>"0001000111000111", Figure A.24: VHDL Code to Implement Sine LUT

153


A.16 Sample Schematic of the LPF 2

Figure A.25 shows the implementation of one tap of LPF 2 using Altium built in logic

blocks and schematics. The previous input signal ‘A’ is delayed using Altium built in

32-bit Delay circuit “FD32CEB”. The clock input is shown by label ‘G’ and clock

enable is shown by label ‘C’ in the figure. The current input signal is shown by label

‘H’ which is multiplied by a coefficient presented as wired lines in Altium. The feed-

forward coefficient is multiplied with the input signal ‘H’ using built in multiplier

“MULT16B” and then added with the previous delayed input signal using a 32-bit

Adder “ADD32B”. The feedback coefficient ‘D’ is also multiplied with the output

signal ‘E’ using another built in multiplier “MULT16B”. The multiplied signal is

added with the previous delayed input signal and current input signal multiplied by

co-efficient using a 32-bit adder “ADD32B”. The final output is obtained at the output

of this adder labeled ‘F’.

154


Figure A.25: Schematic of One Tap of LPF 2

A.17 Sample Schematic of the Hard Limiter

The Hard Limiter and the third multiplier in the Costas loop are implemented in a

separate schematic HardLimiter.SchDoc. The first part of the schematic is shown in

Figure A.26. The Altium port “Upper [15..0]” is the output of the upper (I) LPF 1.

155


Figure A.26: Schematic of the Hard Limiter and the Third Multiplier: Part 1

The second part of the schematic is shown in Figure A.27.


The third part of the schematic is shown in Figure A.28. Here Q is the output of lower

LPF 1.

156



A.18 Sample Snapshot of the Constraint File

Figure A.29 shows a snapshot of the constraint file Cyclone3Updated.Constraint of

our FPGA project.

Figure A.29: FPGA Constraint File

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Appendix B Published Papers

-----------------------------------------------------------------------------

B.1 A High Data-Rate, Software-Defined Underwater

Acoustic Modem

Title: A High Data-Rate, Software-Defined Underwater Acoustic Modem

Conference Name: MTS/IEEE Oceans, Seattle, September, 2010.

Abstract: Most underwater acoustic modems offer only low data rates. This is largely

because they operate at low frequency, which limits the channel bandwidth available,

and hence the symbol rate. The low frequency acoustic channel suffers from

substantial multipath and doppler effects, which constrain the signal quality at the

receiver. As a result only 1 or 2 bits per symbol are achieved, with the effective data

rate further reduced by error control coding. High frequency acoustic signals are

heavily attenuated in water, severely constraining the range of high frequency links.

High frequency signals however offer substantially greater signal bandwidth, and

probably improved channel quality which guides our design choice of a high

frequency acoustic modem for underwater communication. Contemporary Field

Programmable Gate Arrays (FPGAs) can provide good system functionality at low

cost and with the flexibility to perform rapid testing and development of

communication algorithms. They may also be competitive in production systems. In

this paper we describe current progress in development of a high frequency, high

data-rate modem which is implemented entirely in FPGA. This differs from most

existing modems which are based on DSP processors. Being software defined, the

Appendix B: Published Papers

modem is flexible because the parameters can be reconfigured with relative ease,

minimising the cost of rework as the design evolves. This modem will not only

demonstrate the feasibility of high frequency FPGA based modems, but will also be a

valuable tool to provide a better understanding of the high frequency acoustic channel,

and demonstrate the utility of absorption to enhance channel re-use rates in

underwater acoustic networks. The modulator has been implemented in the FPGA, to

produce laboratory and open water tests that conform to modelling. The demodulator

has been implemented in Matlab, and recovers the carrier, code synchronisation and

data from recordings of both laboratory and open water tests. Coding of the

demodulator into the FPGA is currently in progress.

B.2 Design of a High Frequency FPGA Acoustic Modem for

Underwater Communication

Title: Design of a High Frequency FPGA Acoustic Modem for Underwater

Communication

Conference Name: IEEE Oceans, Sydney, May, 2010.

Abstract: Contemporary underwater acoustic networks use low frequency modems.

While these modems can provide long range communication, their low operating

frequencies mean that only low channel bandwidth is available, which results in slow

data rates. This motivates our development of a high frequency modem which offers

the potential for large channel bandwidth, and hence greater link capacity. There is a

range-frequency trade-off because absorption becomes very high at high frequency.

Our intended operating frequencies from 100 kHz to 1 MHz would only support link

ranges perhaps from 1 km down to under 100m, with communication ranges longer

than this requiring forwarding over a network. Reconfigurable computing based Field

159

Appendix B: Published Papers

Programmable Gate Arrays (FPGAs) are used to accelerate product development and

support evolution of fielded systems. Given the immaturity of the field of underwater

communication, a reconfigurable modem is a valuable tool for development and

testing modem techniques. We present a design idea to implement an acoustic modem

solely in FPGA, whereas most existing modems are implemented as a combination of

FPGA and DSP processors. Aside from simple anti-aliasing filters, which could be

incorporated in the preamplifier stage, the modem does all of its processing in the

digital domain – maximising flexibility. In this work, we describe the initial design

and architecture of our software based acoustic modem that avoids the monetary cost

or time investment required to design a commercial modem or custom hardware for

many applications. Our demodulator is implemented using a Costas loop which

performs both suppressed carrier reconstruction and synchronous data detection

within the loop. Results from initial implementation are also reported in this paper.

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