01/11/2002 SNS Software Final Design Review 1

V123S Event Link Encoder, Transmission System and PLL

Receiver

Thomas M. Kerner (BNL)

SNS Global Controls

01/11/2002 SNS Software Final Design Review 2

Event Link System Features

– Low Latency Event Delivery using short code length, 17MHz carrier, passive fanouts and short code lengths.

– Asynchronous 12-bit encode and decode with hardware prioritization to allow fast event delivery. High priority events will transmit first. Trigger priority runs from left to right on input modules.

– Hybrid optical and shielded twisted wire pair system

– 1 ns Jitter Clock Recovery using PLL receiver– Low Bit Error Rate with high signal to noise ratio– Single Cable Clock and Data eliminates clock skew and reduces

cable cost– 256 Event Codes with priority translation table so new

priorities may be assigned to event codes without affecting receivers.

01/11/2002 SNS Software Final Design Review 3

Event Link System Features (cont.)

– Beam Synchronous Event Link carrier is a multiple of the RF clock

– Free PLL receiver drop-in artwork, parts list and program file available to DOE facilities for the PLL Link Receiver Interface.

– Lock out of low priority events including the message stack between pre-pulse PP and TEXT to avoid delaying the extraction event.

– A linked series of events with programmable delays may be generated by feeding back outputs to inputs.

– Message FIFO for software generated events.– Tracks with LLRF for machine tune an energy changes

01/11/2002 SNS Software Final Design Review 4

Provides:

• Facility-wide broadcast event timing, LLRF synchronous clock, and informational events for distributed systems:

– Neutron chopper

– LINAC chopper

– LINAC and Ring RF

– Injection and Extraction

– Beam Instrumentation

– Scopes

– Utility Modules

01/11/2002 SNS Software Final Design Review 5

Status & Control Registers

• CONTROL– Interrupt enable

– On-line/Off-line

– Interrupt ROAK/RORA

– Automatic clock switching on LLRF status (between internal / external LLRF)

– Manual clock override

– Interrupt vector register

– Interrupt level register

– Event FIFO input register

• STATUS– VME ID string

– RF clock bad (occ.)

– Beam clock fault (r.t.)

– FIFO full (r.t. & occ.)

– FIFO empty (r.t.)

– Clock in-use (r.t.)

– PP – Text lockout (r.t.)

– Input error registers (occ.)• FIFO Value < 64 error

• V101 Input module > 63 error

• Input rate error, lost event

For details see V123S Event Link Module manual at http://www.sns.bnl.gov/epics/timing/doc/v123s/V123S revA1.htm

01/11/2002 SNS Software Final Design Review 6

Event Link System - Block Diagram

PECL to FiberOptic Transmitter

P2 Event Bus

V123S BeamSync Master

PECL FanoutA

VMEbus

Passive FiberOptic Splitter

IOC

(PP), T0

Long HaulFiber Optic Runs

Short Haul

DDSCW= 32xFREV

LLRF = FREV

( aligned to FREV)

CounterReset

60Hz LineDSP-PLL

Asst. Triggers

CW

V101S (4 x 16)Prioritized Triggers

V124S Decode/ DelayEvt Xn Evt Xn+1

1 < n < 7532

8

Ethernet

FrevFrom V124S

50 OhmTTLFiberDiff. PECL

KeyRT

DL

LLRF to ring cavities

CW

TEXT . . .

01/11/2002 SNS Software Final Design Review 7

Event Link System - Block Diagram

PECL FanoutB

V124STrigger Module

Fiber Optic toPECL Receiver

V124STrigger Module

V124STrigger Module

VMEbus

IOCs

Long HaulFiber Optic

Runs

Short Haul

8 88

Neutron choppersLinac chopper

Linac and Ring RFInjection and ExtractionBeam InstrumentationUtility Module, Scopes

Event Monitor

Frev toLow LevelRing RF

Ethernet

01/11/2002 SNS Software Final Design Review 8

Event Link Encoder & Input Module

01/11/2002 SNS Software Final Design Review 9

64ExternalInputs

PrivateP2 bus

VME BUS

P2 P2 P2 P2 P2

32x FREV

Clock

BeamSyncEncoder

EventInputModule

EventInputModule

EventInputModule

EventInputModule

EncodedBeamSyncoutput

Event Link Encoder – P2 Dedicated Bus

01/11/2002 SNS Software Final Design Review 10

Event Link Encoder - Bi Phase Mark Encoding

32 * Frev low level ring rf clock input

Event Link 12-bit Event Code = 0xF4, Even Parity, 709 ns

Event Link 16 * Frev (Idle 1 carrier)

32 * Frev low level ring rf clock input

Start

1 1 1 1 0 1 0 0 1 10

Parity Stop1

1

Stop2

1 1 1 1 1 1 1 1 1 11 1

01/11/2002 SNS Software Final Design Review 11

PLL Receiver – IP Module

• Insert IP module Prototype Picture Here

01/11/2002 SNS Software Final Design Review 12

Fanout & Fiberoptic Chassis

16 outputs on production units

Fiber opticreceiver module

Fiber optictransmitter module Power supplies

01/11/2002 SNS Software Final Design Review 13

Machine Cycle & Accumulation Detail

T0 TEXTPP

17,625 turns

PP T0 TEXT

Typical 60 Hz Line Cycle

Planned Extra Cycle

Accumulating BeamT0 AC Line Zero CrossingPP Pre Pulse

TEXT Turns - Extract

TEXT

TLBS + TACC turns2 turns

T0 + TLBS + TACC + 3 turns

T0

TLBS turns

Accumulation Cycle Detail

PP- T0- TEXT-

PP

> 1 turn-

TLBE

TLBE Turns - Linac Beam EndTACC Turns - Accumulate

TLBS

TLBS Turns - Linac Beam Start

T0 + TLBS + TACC + 3 turns