01 EDS Webnar omura 02DecV6 DL TO BE SHARED

Power semiconductor device: Basics

Ichiro OmuraKyushu Institute of Technology

Japan

Since 1909IEEE EDS Webinar Dec. 2, 2015

Ichiro Omura Kyushu Inst. Tech.

Outline• Introduction

– History– Power electronics circuit

• Power semiconductor devices– Power MOSFET / Super-junction MOSFET– IGBT– Thyristors– Lateral devices

• Future possibility • Related technology


1965 - "Moore's Law" Silicon Engine to drive ICT

Robert Noyce

Integrated circuit patent in 1959

Number of components per integrated circuit

Man

ufac

turin

g co

st p

er

com

pone

nt

Gordon E. Moore

CMOS

To digital cost free => ICT for everybodyIchiro Omura Kyushu Inst. Tech.

AC power distribution system


www.cz-toshiba.comtransm.web.fc2.com

AC to ACConstant frequency

No active control function

100 years of power device development (High voltage)

Rotary converter(AC-DC)

SemiconductorTechnology

Thyristor/GTO(AC-DC/DC-AC)

IGBT(AC-DC/DC-AC, MOS gate)

Electronics(Vacum Tubes) Neutron doped FZ wafer

Carrier lifetime control

R&DElectric Machine

mm

0.1mm

10-100um

<1-10um

Advanced LSI Tech.(CMOS, DRAM)

1940 1960 1980 2000


Mercury arc rectifier(AC-DC)

Photos:Nippon inst. tech, MuseumNikkeiTokyu MuseumJR KyushuNagahama Railway MuseumToshiba

IGBTInsulated Gate Bipolar Transistor

Thin wafer technology

Cosmic ray SEUChip Parallel operation

Carrier Injection Enhancement

Edge termination technology

R&D

PWM: Pulse Width Modulation

MotorAC

IGBT

PDS: Power Drive System

Carrier waveModulation wave

Modulated signal to Power Semiconductor switch (ON/OFF)

1. PWM signal control power semiconductors switch (ON / OFF)2. Motor current follows the modulation wave

PWM


C

CR

R

Ring gear

Sun gear

Carrier/Planetary gear

ICE

MotorGenerator

Inverter for motor Inverter for generator

to Wheels

Half-bridge boost converter

Battery

S

IGBTPower Diode

Z. Shen and I. Omura. Proceeding of the IEEE, Vol. 95 No. 4, 2007.(Figure)*A. Kawahashi et al., Proc. of ISPSD 2004, pp. 23-29, 2004.

Total chip area for IGBT and power diode is more than 40 cm2 of silicon wafer for Toyota Prius[*].

Hybrid electric vehicle propulsion system

~200V

~500V


Power Semiconductor Devices


Power Semiconductor Devices

IGBT: Insulated Gate Bipolar TransistorGTO: Gate Turn-off ThyristorGCT: Gate Commutated Turn-off ThyristorLTT: Light Triggered Thyrisotor (optical fiber coupled)

Power MOSFET

Low

High

IGBT

GCT/GTO

Sys

tem

Pow

er

MOS-gateBipolar gate

LTT

• MOS gate devices cover wide-power range.• Bipolar gate devices cover very high power applications(>10MW).

Opt- turn-on


1kW

1GW

Photos:InfineonToshibaABBTMEIC

GTO GCT

LTT

IGBT

Power MOS

Vertical device

Types of power semiconductors(Switch)

GateN-source Source

Drain

N-sub

P-well

N-drift

P-base

N-base

N-emitter

P-emitter

Gate Cathode

Anode

N

P

PN

GateN-source

Emitter

Collector

P-emitter

P-base

N-base

P

P

N

GateN-source

Emitter

Collector

P-emitter

P-base

N-base

GateN-source

Emitter

Collector

P-emitter

P-base

N-base

P

P

N

Power MOSFET IGBT

Thyristors (GTO,GCT)

IGBT: Insulated Gate Bipolar TransistorGTO: Gate Turn-off ThyristorGCT: Gate Commutated Turn-off Thyristor

1. MOS-gate (voltage) control or bipolar gate (current) control2. Unipolar conduction or bipolar conduction in high resistive layer(N-)

N+

P

N-

-

N

-


MOS control +

UnipolarMOS control

+Bipolar

Current control+

Bipolar

Remark: Vertical Device Structure

Edge termination area

Elec

tric

Cur

rent

Volta

ge


Top viewCross section of active area

Cell

Active area

Power MOSFET

Low

High

IGBT

GCT/GTO

Sys

tem

Pow

er

MOS-gateBipolar gate

LTT

Opt- turn-on


1GW


GTO GCT

LTT

IGBT

1kW

Power MOS

Power MOSFET

Power MOSFETGate

N-source Source

Drain

N-sub

P-well

N-drift

Conduction carrier…… Electron or holeSwitching control ……. MOS-gateSwitching Freq. ………. High

Source

DrainGate

De-coupling Capacitor

Imput Voltate

Sync. Rect. MOSFET

High Side MOSFET

Inductor

Output Capacitor

CPU-chip

DC to DC Converter CPU=Load

Current


Function of N-drift layer

Source

Drain(VB)

Ey

drift

dyD L

Edy

dEqN ⋅=−= εε

dE

S

D

G

Source

Drain

Ey

Charge neutrality

Voltage Blocking Conduction

p

n+

n-drift

drift

condDncondDnn L

VNqENqJ μμ ==

condE

electron

driftL

Function of N-drift layer:1. Voltage blocking (higher breakdown voltage)2. Current conduction (lower resistivity)

Blocking state (Poisson eq.) Conduction state (current eq.)

μn: electron mobility

donor


driftcritB LEV ×=21

3

24

critn

Bdrift E

VRεμ

=

Ey

critE

driftL

y drift

critD L

EqN ⋅= ε

Drift layer doping, length and drift layer resistance

0.0

5.0

1.0

1.5

2.0

2.5

3.0

1012 1013 1014 1015

X105 V/cm

Crit

ical

Ele

ctric

Fie

ld fo

r Sili

con

(Ecr

it)

N-drift Donor Concentration (/cm3)

ｐｎ-

Ecrit

B

critD qV

EN2

2

⋅= ε

crit

Bdrift E

VL 2=

Drift layer doping

Drift layer length

drift

condDnn L

VNqJ μ=

Drift layer resistance[Ωcm2]

10V 100V 1kV 10kV0.1mΩ

1mΩ

10mΩ

100mΩ

1000mΩ

RON

Ecrit: critical E-field strength


1. Cell size reduction for channel density 2. Trench gate for channel density and JFET resistance removal 3. Charge compensate (Vertical Field Plate) technology for drift

resistance reduction.

Low Voltage MOSFET (Vertical)

N-drift layerP-well

N-source

GateSource

Drain

Breakdown voltage (V)10 100 1000

1000

100

10

1

0.1

Ron

A(m

Ωcm

2 ）

Si-limit

10 100 1000

1000

100

10

1

0.110 100 1000

1000

100

10

1

0.1

1997

2002

2007

2012

Fig from Lecture Slide by W. Saito, Toshiba


DMOSFET

P/N column drift layerEasy to deplete for high impurity concentrationLow Ron + High Breakdown Voltage

SJ-MOSFET

0

5

10

15

20

25

0 5 10 15 20 25 30

P/N column pitch (μm)

On-

resi

stan

ce R

onA

(mΩ

cm2 )

VB=700V

Higher

colum

n dop

ingBreakdown voltage (V)

10 100 1000

1000

100

10

1

0.1

Ron

A(m

Ωcm

2 ）

Si-limit

10 100 1000

1000

100

10

1

0.110 100 1000

1000

100

10

1

0.1

1997

2002

2007

2012

Fig from Lecture Slide by W. Saito, Toshiba

Super Junction MOSFET

Charge compensate (Super Junction) technology for drift resistance reduction.


Column doping(ND) and Breakdown Voltage(VB)

Source

Drain

Ey

holE

Ex

VB

Ex

Ey

1. Horizontal field for P/N column depletion

Vertical field

column

holxD W

Edx

dEqN 2⋅== εε

columnWcolumnW vertE

driftvertB LEV ⋅=2.Vertical field for voltage blocking between drain and source

Electric field in SuperJunction structure high drift layer donor doping1. Horizontal electric field for depletion of PN junction in narrow columns 2. Vertical electric field for sustain blocking voltage across drift layer

condDnn ENqJ μ21=

3. A half area of drift layer contribute current conduction


VB

Ehol

Evert

|E|<Ecrit

2 Ecrit

2 Ecrit

column

critD qW

EN 2⋅= ε

source

Drain

Ey

holE

Ex

VB

Horizontal field

columnWvertE

drift

condDncondDnn L

VNqENqJ μμ21

21 ==

Drift N-column doping

Drift layer length

driftvertB LEV ⋅=column

holD W

EqN 2⋅= ε 2crit

holEE ⇐

2crit

vertEE ⇐

crit

Bdrif E

VL 2=

Drift layer resistance[Ωcm2] 2

2

critn

colomnBdrift E

WVRεμ⋅=

Drift layer doping, length and drift layer resistance

Assumption: N-column and P-column are same widthIchiro Omura Kyushu Inst. Tech.

1GW

IGBTInsulated Gate Bipolar Transistor

Low

High

GCT/GTO

Sys

tem

Pow

er

Bipolar gate

LTT

Opt- turn-on



GTO GCT

LTT

Power MOSFET

1kW

Power MOS

IGBT

MOS-gate

IGBT

1. Bipolar Transistor + MOSFET (before IE-effect)2. High current capability3. ~0.8V collector-emitter threshold voltage for conduction4. Medium switching speed (15kHz for motor drive, 100kHz for ICT

current supply and FPD driver )

Collector

Gate

Emitter

IGBT

50

100

1985 1990 1995 2000 2005

200

300

500

Rat

ed C

urre

nt D

ensi

ty(A

/cm

2 ) Thin wafer NPT

Thin wafer PT

Trench gate

NPT-IGBT

Carrier enhancement effect

Non latch-up IGBT

IPM

Year2010 2015

Thermal management

High Temp.

Protection

Noise control

Vce

Ic

0.8V

Shen, Omura, “Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell Vehicles” Proc. Of the IEEE, Issue 4, 2007


Operation mechanism of IGBT

Ionized impurity (donor)

0≅E

0≅E

0≅E

0≅E

Electron

0)( ≅−=⋅ nNqdx

EdD

ε

0)( ≅−+=⋅ npNqdx

EdD

ε

npND ,<< npni ≅<<

Conduction modulation in N-base

positive negative

Hole

)(2 npkTq

i enpnφφ −

=

2inpn =

GateN-source

Emitter

Collector

P-emitter

P-base

N-base

P

P

N

GateN-source

Emitter

Collector

P-emitter

P-base

N-base

P

P

N

np φφ ≅

Vce

Ic

0.8V

IGBT

MOSFET

PN-junction built-in potential

Conduction modulation

Unipolar

N-base

Conduction modulation1. Both hole and electron contribute to current

conduction2. High stored carrier density in N-base (>1016cm-3)3. Built-in voltage with the stored carrier


Epitaxial layer with carrier lifetime control

Electric field at blocking state

Low resistance P-type Substrate

Stored Carrier during on-state

P-emitter

N-buffer

N-base

P-baseN-source

Gate

Emitter

Collector

High minority carrier(hole) injection efficiency

Punch-through IGBT (PT-IGBT)

1. Epi grown N-buffer (field stop) and short / lightly doped N-base

2. High minority (hole) carrier injection from P-emitter

3. Low-conduction loss and large switching loss

4. Carrier lifetime control (high energy electron irradiation etc.) required


Electric Field at blocking state

Neutron transmutation doped wafer


Shallow P-emitter

N-base

P-baseN-source

Gate

Emitter

Collector

M. Tanenbaum and A. D. Mills J. Electrochem. Soc., vol. 108, pp.171 1961J. Cornu and R. Sittig IEEE Trans. Electron Devices, vol. ED-22, pp.108 1975IAEA-TECDOC-1681, Neutron Transmutation Doping of Silicon at Research Reactors, 2012

Neutron transmutation doping

Low minority carrier(hole) injection efficiency

Non-Punch-through IGBT (NPT-IGBT)

1. NTD wafer without N-buffer 2. Low minority (hole) carrier

injection from P-emitter3. Higher-conduction loss and

lower switching loss4. No carrier lifetime control

requiredIchiro Omura Kyushu Inst. Tech.

Electric field at blocking state


N-buffer

N-base

Shallow P-emitter

NTD wafer etc.

P-baseN-source

Gate

Emitter

Collector

Thin wafer IGBT technology

N-base length Short Long Short

Carrier lifetime in N-base

Short Long Long

P-emitter hole injection High Low Low

PT NPT Thin-wafer-PT

Thin Wafer Technology -Reduction of turn-off tail current with short N-base-Reduction of conduction loss with short N-baseLow Hole Injection P-emitter with long carrier lifetime-Reduction of turn-off tail current with low hole injection-Better thermal coefficient without carrier lifetime control


=FS-IGBT


N-base

Pemitter

N-buffer

P-baseN-source

Gate

Collector

Emitter

Hole current

Electron current

Problem in High Voltage IGBT Device Design

High conduction resistance for high voltage IGBT

Carrier storage



Pemitter

N-buffer

P-base

N-source

Gate

Collector

Emitter

Hole current

Electron current

Electron Injection Enhancement Effect

Trench gate technology with special structure enhances majority carrier (electron) injection in N-base Low conduction loss under high current density

Kitagawa et al. “A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor,” IEDM’93, 1993.Omura et al. “Carrier injection enhancement effect of high voltage MOS devices-device physics and design concept,” ISPSD 97, pp. 217-220, 1997.Omura, “High Voltage MOS Device Design: Injection Enhancement and Negative Gate Capacitance, (ETH thesis 2000), Series in Microelectronics Vol. 150, Hartung-Gorre Verlag, 2005.

N-base

Carrier storage


Summary of IGBT Technology

N-base

P-emitter

Gate

•Thin Wafer Technology – Both conduction and turn-off loss reduction with

with short N-base

•Trench Gate–Conduction loss reduction with electron injection enhancement –Channel resistance, JFET resistance reduction

•Low Injection P-emitter + Long Carrier Lifetime

– Turn-off loss reduction with low hole storage in N-base

– Better thermal coefficient without carrier lifetime control


N-base

Pemitter

N-buffer

Floating P

Gate

Collector

Emitter

Holecurrent

Electron current

Ey

Voltage blocking

E-field

n

Conduction (flat carrier distribution is assumed)

Ey

E-fieldCharge neutrality

p

Electron hole

storedncrit

Bbasen

crit

B

EVL

EV ≥≥ −2

storednnp =≅

N-base length

Stored Carrier density

Conduction and Breakdown Voltage

i

stroedinbuilt n

nq

kTV ln2=−

critstoredpn

BbaseN Enq

VR⋅⋅+

=− )(2~1

μμN-base conduction resistance


Vce0.8V

IGBT

MOSFETIc


DMOSFET

Drift Layer Doping(Stored carrier density)

Drift Layer Length(N-base length) crit

Bdrif E

VL 2=

Drift Layer Resistance(N-base conduction resistance) 3

24

critn

Bdrift E

VRεμ

=

B

critD qV

EN2

2

⋅= εcolumn

critD qW

EN 2⋅= ε

crit

Bdrif E

VL 2=

2

2

critn

colomnBdrift E

WVRεμ⋅=

Device Structure

Assumption: N-column and P-column are same width

IGBT

N-base

Pemitter

N-buffer

Floating P

Gate

Collector

Emitter

Holecurrent

Electron current

storedn

crit

Bbasen E

VL 2~1=−

critstoredpn

BbaseN Enq

VR⋅⋅+

=− )(2~1

μμ

(flat carrier stored carrier distribution is assumed

(>1016cm-3)

SJ-MOSFET


none nonei

storedinbuilt n

nq

kTV ln2=−

600V class device 80-100 mΩcm2 <10 mΩcm2 ~1.5V at 200A/cm2

Omura et. al, International Workshop on Physics of Semiconductor Devices, 2007. IWPSD 2007, pp. 781 – 786, 2007

.


DMOSFET

Device Structure

IGBT

N-base

Pemitter

N-buffer

Floating P

Gate

Collector

Emitter

Holecurrent

Electron current

SJ-MOSFET

V-I characteristics

Omura et. al, International Workshop on Physics of Semiconductor Devices, 2007. IWPSD 2007, pp. 781 – 786, 2007

.

Switching charge (turn-off charge)

Vce

Ic

inbuiltV −

VDS

ID baseNR −

VDS

IDdriftON RR ≅

driftON RR ≅

Charge in main-junction capacitance Stored carrier sweep out

PN-column depletion charge


Types of Power Semiconductors

Low

High

Sys

tem

Pow

er



Power MOSFET

1kW

Power MOS

IGBT

MOS-gate

1GW IGBTGCT/GTO

Bipolar gate

LTT

Opt- turn-on

GTO GCT

LTT

N-emitter

N-baseCathode Anode

Stored carrier concentrationunder current conduction

Impu

rity

conc

entra

tion

P-baseP-emitter

Light Triggered Thyristor(LTT)Photos: http://dbnst.nii.ac.jp/


Forward blocking

ConductionReverseblocking

Trigger pulse

1. PNPN structure2. Light triggered turn-on3. Cannot turn-off by gate4. One wafer per one device 5. Pressure contact package6. Highest power per single semiconductor

1.4GW system by Toshiba

ABB GTO(GCT)

Integrated gate circuit5.5kV, 5kA HPT IGCT

Gate drive current

ABB

ABB

GCT: Gate Commutated Turn-off Thyristor

1. PNPN structure2. One wafer per one device 3. > 100um cell size4. Pressure contact package5. Very low stray inductance

integrated gate driver for couple of kA gate current

6. Highest power per single semiconductor turn-off device


Motor Driver

Audio Speaker Driver

~1kV

<100V

Oxide

BOX

Emitter Collector

Substrate

Lateral DevicesControl and Power = Power IC

P n+ n+n-drift

Source DrainGate

Trypath datasheet

Toshiba


Breakdown at vertical PN-junction

N-drift Dose

Bre

akdo

wn

volta

ge

Breakdown near N+

Breakdown near P

RESURF principle for breakdown voltage design

N-drift dose (atm/cm2) is the key parameter for breakdown voltage design (~1e12/cm2)

Figure J. A. Appels et al. IEDM1979, pp. 238- 241, 1979

PP-

N+

Gate

Source Drain

High dose N-drift

GND

Ey

ExElectricfield

N-driftN+

PP-

N+

Gate

Source Drain

Ex

Low dose N-drift

GNDElectricfield

N+ N+N-drift

PP-

N+

Gate

Source Drain

Medium dose N-drift

GND

Ey

ExElectricfield

N-drift


Oxide

D. Disney et al. A new 600V lateral PMOS device with a buried conduction layer, pp.41-44, ISPSD’ 03

Gate

P-buried

N

P-substrate

DrainSourceX2 amount of conduction carriers OxideGate

P-buried

NP-substrate

P-buried

Lateral “Super Junction” MOSFET


SOI IGBTOxide

BOX

GND

Emitter

Substrate

Nbase Ey

Future Power ICsPower IC VBK in ISPSD papers

Digital RichPower IC

Omura, ECPE workshop Jan. 2012

Future HV Power IC will be …


1

10

100

1000

10000

0.1 1 10 100 1000Current（A）

Volta

ge（V）

Max

(Vin

, Vou

t)

CPU Power Supply(POL)

Appliances

Mobile Power Supply

TransmissionsHigh power motor drives

Vicor VIChip

DIP IPM

Max(Iin, Iout)

HEV IPM

Power ICs on PCB

SOI single chip inverter

Single chip power supply

Transfer molded power

devices / Power SiP

on PCB

IPM with ceramic

Insulator

Power SoC

High power Industrial DrivesEV/HEV

High Power Modules

/ PPIs

On board Power Supply

Industrial IPM

Omura, CIPS 2010

Kilowatt Power IC

Future Possibility



PowerIntegrated

Circuit area

PowerIntegrated

Circuit area

GaNHEMT/MOS/SBD

Wide band-gap semiconductorPlatform (SiC::2010 ～、GaN::2015 ～Diamond::2025～）

SiCMOS/SIT/SBD

SiCIGBT/PiN

Blocking voltage [v]1 10 100 1k 10k

DiamondFET/ BJT/PiN/Field

emitter

CMOS, MOSFET (SJ)/SBD, PiN

IGBT, Thyristor/PiN

Si-MOS(SJ)SiC-SBD

Si-IGBTSiC-SBD, SiC-PiN

Silicon

Silicon

GaAs-FET

Advanced power devices Road map

Silicon platform (～2030）

Hybrid pair platform of Si-switchingdevice and SiC diode (2013～2035）

H. Ohashi et al. “Role of Simulation Technology for the Progress in Power Devices and Their Applications,” IEEE T-ED, Vol. 60, issue 2, 2013.

Future possibility• 1) Si-power devices still have much room for development toward ultimate

MOSFETs and IGBTs.• 2) The combination of Si-switching devices and SiC freewheeling diodes will

be a significant step not only for strengthening the SiC market but also for Si-device development.

• 3) Si-IGBT will be replaced by SiC MOSFET in the voltage range of more than 1000 V in some applications, and SiC-IGBT has the potential to be used for applications of more than 10 kV. (Si-IGBT for volume market, SiC for high end market)

• 4) GaN power devices will replace some of Si-power ICs and will be used for faster switching applications.

• 5) The unique properties of diamond have potential for new power devices particularly in high-voltage applications.

• 6) The ultimate CMOS has the potential to be used for power integrated devices in ICT applications.

H Ohashi, I Omura - IEEE transactions on electron devices, 2013Ichiro Omura Kyushu Inst. Tech.

Related Technology


Examples of High Power IGBT Package

125mm

42 Chips

15mm

Shen, Omura, “Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell Vehicles” Proc. Of the IEEE, Issue 4, 2007Ichiro Omura Kyushu Inst. Tech.

Wafer technology(Silicon)Productivity

Quality Functionality

Low voltage commodity

Low voltage high spec

6500V IGBT

1200V IGBT1200V PiN diode

High voltage power MOS

Thyrisotrs

300mm, CZ, MCZ

150-200mm FZEpi, SOI, SJ-structure etc(Pre-structured wafer)

Special Power Devices

6500V PiN diode

Long carrier lifetime

Material (wafer) engineering will share the major part of total power device design, fabrication and

PE application

Large Market, Short time to market

Smaller Market, Long term Integration, Game change


Power electronics and micro electronicsforming Cyber-Physical System

Hardware

Micro-electronics

Service

LSI, Adv. CMOS

Power Semi.

PowerCircuit, ControlLegacy Power-

Electronics

Energy network

Software,Software,Sensing,Protocol Legacy Micro-

Electronics

Power-electronics

Digitalnetwork

Networking

Clustering

Integrating

ActuatingLighting

HeatingCoolingE-Storage

High speed communication

CloudInternet

SNSIoT, Industrie 4.0

I. Omura, SIIQ report, Oct. 2012, in Japanese

Integration


Generating

Electron devices are the key technology for future energy networking New phase of electronics has started with close link between power

and micro electronics for future sustainable society

Z. John Shen, Ichiro OmuraArticle Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell VehiclesProceedings of the IEEE 05/2007; 95(4-95):778 - 789.

H. Ohashi and I. Omura “Role of Simulation Technology for the Progress in Power Devices and Their Applications,” IEEE T-ED, Vol. 60, issue 2, 2013.


See also

Documents

01 EDS Webnar omura 02DecV6 DL TO BE SHARED