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3. DIGITAL PLL M ODEL

As previously, a linear general DPLL model is now considered.

Due to the discrete and feedback characteristics of the loop, aDPLL implementation implies that someplace inside the loop a

time delay must exist to avoid a delay-free loop. I n order to achieve

simplicity and a straightforward realisable model, the time delayis attached to the phase detector feedback branch (eq. 7), becausethis will be the loop first operation to be performed inside the DSP.

(7)

Again, assuming a linear PD characterized by kd, a filter char-acterized by F ( z ) , a DCO characterized by a generic function

O(z) = @ o ( z ) / a f ( z )nd gain factor k, and a frequency/phase

division factor N , a generic DPLL Mth-order transfer function,

a o ( z ) / a i ( z ) , ay then be written as:

@.d(Z) = kd [@i Z) - @,(Z)]

For the usual first-order DCO derived from its analogue counter-

part VCO, O(z)= k,/(l - z - ' ) , it is possible to express the loopfilter coefficients as:

Considering the Bilinear Transformation [4] as the method to mapthe APLL to the DPLL specification and imposing the constraintthat the number of DPLL zeros is one less the number of poles

y ~ 0 , it is possible to explicitly identify an APLL zero at2Fs [5]. This restriction implies that a M )th-o rder digitalfilter is obtained which means a perfect match between the APLLand DP LL compo nents results as desired. S ince several of the mostcomm on low-pass frequency response characteristics (such as But-terworth, Chebychev, Elliptic (odd order) [4]) have y~ = 0 it is

always possible to add this extra zero to the APLL specificationwithout affecting the desired DPLL a nd loop filter orders.

On resume, once the APLL frequency response is specified,

an additional zero is imposed at 2F.9 and the DPLL transfer func-

tion coefficients are obtained via the Bilinear Transform ation. TheA4 )th -or de r digital filter coefficients may then be obtained

through eq. 9.

4. DESIGN EXAMPLES

R o APLL/DPLL illustrative design examples are now consid-

ered. A 3'd-order (usually the maximum practical order [l , 21)

and a 7th-ord er PLL with Butterworth [4] frequency response werechosen. In order to allow a perfect match between the APLL and

DPLL realizations and their performance stand comparison, thechoice of the PL L parameters was mainly restricted due to the dig-

ital realization limitations (as explained in section 6). Since it is

usual to have a PLL with a very lower cut-off frequency than theoscillator free-running frequency [ 21, due t o these limitations,

a cut-off frequency of 398Hz (approximately 1/50 of the sam-pling frequency) was chosen for both PLLs. The VC O/DCO free-running frequency was set to fo = 3 k H z and its desired linearlimits to fo 1 .5kH.z . The APLL design takes into account its

realization with a commercially available circuit with an exclusive-

or (XOR) PD (see section 5). The DPLL design considers its im-

plementation on a fixed-point DSP with a direct phase difference

PD (see section 6). For the purpose of illustration, the 3Td-order

APLL and DPLL design parameters (obtained with the proposed

design equations) are derived in the following subsections.

4.1. APLL 3 d-order Butterworth Design

For the 3'd-order low-pass Butterworth frequency response with

39 8H z cut-off frequency (at 3dB), the theoretical transfer coeffi-cients are: cy0 = P = 1, cy1 = cy = cy3 = 0, p1 = 7.99773583E-4,Z = 3.19818892E-7, p 3 = 6.39456754E-11, which leads to N =

1 . Assuming a power supply with V+= -V- 5 V is used, the

XOR phase detector gain is kd = 3.18309886 V / r a d . With the

same power supp ly and the limits specified in the previous section,

the VCO gain is k, = 1884.955592 r a d / s / V . The resulting Znd

order filter is then characterized by: FO = 0.20839231, a0 =.bo =

1, a1 = a2 = 0, bl = 3.99886792E-4, bz = 7.99547231E-8, whichcorresponds to a pole frequency of w 3536.53482 r a d l s withquality factor Qp = 0.70710678.

The m odulus of the desired A PLL frequency response aind itsfilter are depicted (flipped left-right) in fig. 5 (solid lines lalbeled

T 3 and F 3 , respectively). Th e corresponding curves for the 7t h-

order APLL design are also depicted T7 nd F7).

4.2. DPLL 3 d-~rd erButterworth Design

Starting with the APLL transfer function (derived in the previous

subsection), after adding the necessary extra zero at 2F s and ap-

plying the bilinear transformation, the DPL L transfer function co-efficients are: yo = 4.41303009E-4, y~ = 8.82606018E-4, 7 2 =

63 = -7.77315688E -1. M aintaining the parallel with the APLI,, theDPLL parameters are: N = 1, kd(ALU)= 0.31831 aZu/raa ( ahmeans here fictional ALU units), k,(ALUf = 0.47505 r a d / s / a Z u

The resulting IIR [4] filter is characterized by: FO = 0.404011966,

4.41303009E-4,73 =0,150= 1,61= 2.74842215,62 = 2.52750305,

CO = 7.22338342E-3, CI = 1.44467668E-2, ~2 = 7.22338342E-3,

do = 1, d l = -1.74886346, dz = 7.77756993E-1.

As in the analog case, in fig. 6 are depicted the the oretic curves

(solid lines) corresponding respectively to the flipped left-right fre-

quency response of the DPLL (T3) and the loop filter (F3) . Thecorresponding curves for the 7th-order DP LL design are als'o de-picted ( 7 and F7) .

5. APLL REALIZATION

The APLL realization was based on the commercially availablephase locked loop 4046 circuit [6]. It includes a VCO andl two

PDs (a XOR and an edge-controlled digital memory network). TheXOR was chosen for two reasons. Its characteristic is identical to

the one of the digital direct phase difference detector [3] and it hasan higher immu nity to noise [6]. In order to obtain a rectangu-

lar wave clean from interference, a voltage comparator circuit [7]

was also included at the input (see fig. 2). The external compo-nents that control the VCO characteristic ( , and C a b ) were

chosen to obtain a frequency offset [6] and to satisfy the designrequirements. Since the VC O experimental gain was higher thanthe desired value, an attenuator with a variable resistor a )as

included fig. 2).

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4046 +T-Thornas -Thomas HT-Th om as

Biquad 1 Biquad 2 Biquad

vcoo

Figure 2: Simplified block diagram of the APLL realization.

The external loop filter was realized with Tow-Thomas biquad

sections (fig. 3) which are versatile and easy to design [7]. The

3 T d - ~ r d e rPLL is implemented with only one biquad. The 7th-order filter includes three biquads. The first section has unity gain

and the lowest quality factor. The second section gain was adjusted

to maximum unity gain. The last section has the highest quality

factor and its gain was adjusted to provide the remaining global

filter gain. The values of the used components differed 15 at

most from the theoretic values.

Figure 3: Tow-Thomas biquadratic section.

The loop filter frequency responses proved to be very accurate

showing that the filter was not affected by the finite gain bandwidthproduct of the operational amplifiers [7] for the frequency range of

interest. The 7tha nd 3 P d - ~ r d e rilter theorical frequency responsemodulus are depicted in fig. 5 (solid lines labeled F7 and F3).

6. DPLL REALIZATION

The DPLL realization was accomplished using the 16 bit fixed-

point DSP TM S320C25 and its software development system en-

vironment [4]. An analog interface board with two analog in-

putloutput channels which is based on the TLC320 40 analog in-terface circuit [5] was used. This circuit has a reconstruction anti-

XIN

DCO,

XOUT

Figure 4: Simplified block diagram of the DPLL realization.

aliasing lowpass filter that was software programmable to half the

sampling rate which in turn is also software changeable bu t limitedby the 12 bit ADC and DAC supported rate. A sampling frequency

of FS = 19 .84 kH z was chosen. Due to the one input channel andone output channel with anti-aliasing filter limitation, besides the

DPL L structure two extra block were added (fig. 4). An inputDCO Dco,,) imulates the input phase signal ( ,) to which,for instance, external noise ztn)ay then be added to analyze theDPLL performance in the presence of noise. A sine wave gener-ator addressed by the loop D CO output is also included. A directtable lookup scheme with linear interpolation was used, providingan output sine waveform with very low harmonic distortion.

A direct realization of the phase difference PD was imple-

mented based on the D SP arithmetic logic unit wraparound char-

acteristic [4] ts input phase signals are sawtooth waveforms vary-

ing between i l which simulates the phase variation between f rBoth the input DCO and the loop DC O also take advantage of the

DSP arithmetic logic unit wraparound characteristic.The filter was implemented through the cascade of second-

order canonic IIR sections with coefficients and node scaling al-

lowed [4]. As in the analog case, the 3'd-order DPLL includesonly one section, while the 7th-order includes three sections. T he

7 t h an d 3 P d - ~ r d e rilter theorical frequency response mo dulus a re

depicted in fig. 6 (solid lines labeled F7 and F3).

7. EXPERIME NTAL RESULTS

Since in the DP LL a direct phase difference realization was imple-

mented ( 1 and 0 are sawtooth signals ig. 4) and a XOR PD

211 and v re rectangular waves - ig. 2) was used in the APLL ,it is difficult to experim entally obtain T(ejUT8)r T ( j w ) n a di-rect way. An additional transfer function relating the filter output

P-OdWf iH*]

5 1 0 7 0 5 3 0 1 0 . 0 7 0 0 5

Figure 5: APLL 7thand (flipped left-right) 3rd-order experimen-tal (dotted lines) and theoretic (solid lines) frequency responses

modulus: T - PLL; F - ilter; H - iltered phase error fun ction.

with the input phase signal was defined (respectively H(eJwTs)and H( jw )) . This transfer function is named here as the filteredphase error function.

Both the loop filter and filtered phase error function frequen cy

response modulus were experimentally characterized and are de-

picted in fig. 5 and 6. To maximize the charts dynamic range

for both the 7th and 3'd-order PLLs, the 3'd-order plots were

flipped left-right and are depicted with different scales (top andright scales) from those of the 7th-order (bottom and left scales).

A direct comparison with the theoretic curves (solid lines)shows both APLL and DPL L precise frequency response achieve-

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