e x a m p l e 2.20 a n N - r e s i s t o r c u r r e n t d i v i d e r Nowconsider the more general current divider having N resistors, as shown in Figure 2.38.It can be analyzed in the same manner as the two-resistor current divider. To begin, theelement laws are

i0 = −I (2.101)

vn = Rnin, 1 ≤ n ≤ N. (2.102)

Next, the application of KCL to either node yields

i0 + i1 + · · · iN = 0 (2.103)

and the application of KVL to the N − 1 internal loops yields

vn = vn−1, 1 ≤ n ≤ N. (2.104)

Finally, Equations 2.101 through 2.104 can be solved to yield

i0 = −I (2.105)

in = Gn

G1 + G2 + · · · GNI, 1 ≤ n ≤ N (2.106)

vn = 1

G1 + G2 + · · · GNI, 0 ≤ n ≤ N (2.107)

where Gn ≡ 1/Rn. This completes the analysis.

As was the case for the two-resistor current divider, the preceding analysis shows thatparallel resistors divide current in proportion to their conductances. This follows fromthe Gn in the numerator of the right-hand side of Equation 2.106. Additionally, theanalysis again shows that parallel conductances add. To see this, let GP be the equivalentconductance of the N parallel resistors. Then, from Equation 2.107 we see that

GP = I

vn= G1 + G2 + · · · GN (2.108)

from which it also follows that

1

RP= 1

R1+ 1

R2+ · · · 1

RN(2.109)

where RP ≡ 1/GP is the equivalent resistance of the N parallel resistors. The latter resultis summarized in Figure 2.40.

83a

F IGURE 2.40 The equivalenceof parallel resistors; for N = 2,RP = R1R2/(R1 + R2).

R1R2

Rp1R1------ 1

R2------ ... + 1

RN-------+ +

1–=RN

. . .

. . .

Finally, the two current-divider examples illustrate an important point, namely thatparallel elements all have the same voltage across their terminals because their terminalsare connected directly across one another. This results in the KVL seen in Equations 2.80,2.81, and 2.104, which state the equivalence of the terminal voltages.

83b

e x a m p l e 2.28 b a s i c c i r c u i t a n a l y s i s m e t h o d Solvethe circuit in Figure 2.58 using the basic method.

Step 1 is to assign the branch variables. Figure 2.59 shows the circuit with the variablesproperly assigned.

In Step 2, we write the constituent relations:

vS = −V (2.153)

v1 = i1R1 (2.154)

v2 = i2R2 (2.155)

v3 = i3R3 (2.156)

v4 = i4R4 (2.157)

v5 = i5R5. (2.158)

In Step 3, we write the KVL and KCL equations. The KVL equations with respect tothe loop choice shown in Figure 2.60, are

vS + v1 + v2 + v4 = 0 (2.159)

−v2 + v3 = 0 (2.160)

−v4 + v5 = 0 (2.161)

R1

R4

R5

+

-

V

R2

R3F IGURE 2.58 Circuit example.

97a

F IGURE 2.59 Circuit withproperly assigned variables.

v

R1v2

v3

R4

R5

+

-V

v1 R2

v4

v5

R3

+

+

+

+

+-

-

-

-

-

iS

i3

i2

i4

i5

i1

vS

+

-

F IGURE 2.60 Loop and nodechoice.

+

-V

L1 L2

L3

(a)

(b)

(c)(d)

97b

At node (a), the KCL equation is

i1 − i2 − i3 = 0. (2.162)

Notice that nodes (b) and (c) are connected by a wire, so they yield only one KCLequation

i2 + i3 − i4 − i5 = 0. (2.163)

Lastly, at node (d), we have

i4 + i5 − iS = 0. (2.164)

Combining the constituent relations with KVL equations, we obtain

−V + i1R1 + i2R2 + i4R4 = 0 (2.165)

−i2R2 + i3R3 = 0 (2.166)

−i4R4 + i5R5 = 0. (2.167)

By adding Equations 2.162 2.164, we have

iS = i1. (2.168)

Eliminating i2 and i4 and substituting back into Equations 2.166 2.167 gives us

i3 = iSR2

R2 + R3(2.169)

i5 = iSR4

R4 + R5(2.170)

V = iS

(R1 + R2 + R4 − R2

2

R2 + R3− R2

4

R4 + R5

)(2.171)

= iS

(R1 + R2R3

R2 + R3+ R4R5

R4 + R5

). (2.172)

As a quick sanity check of the solution, one might notice that the equivalent resistanceof the network around the voltage source is R1 + R2‖R3 + R4‖R5, which is correctlyshown by Equation 2.172.

97c

e x a m p l e 2.33 v o l t a g e - c o n t r o l l e d r e s i s t o r Thus farwe have dealt with resistors that have a fixed resistance. However, like dependentsources, we can also have resistors whose values depend on other parameters. As anexample, Figure 2.71 depicts a voltage-controlled resistor whose resistance RX is afunction of vI.

Let us suppose we are interested in determining vO as a function of vI for

RX = f (vI) = RovI

where Ro is some known constant. Let Ro = 5 k/V.

First, R1 and R2 form a simple voltage divider, and since R1 = R2, we have vI = V/2.Second, RL and RX also form a voltage divider. Therefore,

vO = VRX

RL + RX

= VRovI

RL + RovI

= V5 k/vI

10 k + 5 k/vI

= VvI

2 + vI

= VV2

2 + V2

= V2

4 + V.

Substituting V = 5 V, we find that vO = 25/9 V.

F IGURE 2.71 Circuit withvoltage-dependent resistor.

vI vO5 V+

- V

R1 100= kΩ RL = 10 kΩ

RX = f (vI)R2 100 kΩ=

107a

2.7 A FORMULAT ION SU I TABLE FOR ACOMPUTER SOLUT ION *

Thus far we have seen several circuit examples that we solved by writing aset of equations based on the constituent relations for the elements, KVL,and KCL. There were as many independent equations as unknown variables,which allowed us to solve for any variable by simple algebra. The same setof equations can be written in matrix form so that they are amenable to acomputer solution. For example, the circuit in Figure 2.1 analyzed using thebasic method in Section 2.3.5 resulted in ten equations and ten unknowns.These ten equations are summarized as follows:

v1 = i1R1 (2.202)

v2 = i2R2 (2.203)

v3 = i3R3 (2.204)

v4 = i4R4 (2.205)

v5 = V (2.206)

−v5 + v1 − v2 = 0 (2.207)

+v2 + v3 + v4 = 0 (2.208)

−i5 − i1 = 0 (2.209)

+i1 + i2 − i3 = 0 (2.210)

i3 − i4 = 0. (2.211)

The ten unknowns are v1, v2, v3, v4, v5, i1, i2, i3, i4, and i5. The equations can berewritten so that constant voltages and currents appear on the left-hand side ofthe equation.

0 = v1 − i1R1 (2.212)

0 = v2 − i2R2 (2.213)

0 = v3 − i3R3 (2.214)

0 = v4 − i4R4 (2.215)

V = v5 (2.216)

0 = v1 − v2 − v5 (2.217)

0 = v2 + v3 + v4 (2.218)

0 = −i5 − i1 (2.219)

0 = i1 + i2 − i3 (2.220)

0 = i3 − i4. (2.221)

107b

This set of equations can be written in matrix form as follows:

0000V00000

=

1 0 0 0 0 −R1 0 0 0 00 1 0 0 0 0 −R2 0 0 00 0 1 0 0 0 0 −R3 0 00 0 0 1 0 0 0 0 −R4 00 0 0 0 1 0 0 0 0 01 −1 0 0 −1 0 0 0 0 00 1 1 1 0 0 0 0 0 00 0 0 0 0 −1 0 0 0 −10 0 0 0 0 1 1 −1 0 00 0 0 0 0 0 0 1 −1 0

v1v2v3v4v5i1i2i3i4i5

(2.222)

This matrix equation is in the form

b = Ax

where x is a column vector of unknowns and b is the column vector of drivevoltages and currents. This vector of unknowns can be solved by a computerusing standard linear algebraic techniques such as Cramer’s rule. In fact, the wellknown SPICE software package uses methods such as these to solve circuits.5

5. The examples in this chapter focused on linear circuits, which result in a set of linear simulta-neous equations. However, the fundamental method of solving circuits based on KVL, KCL, andconstituent relations applies equally well to nonlinear circuits. A nonlinear circuit might containnonlinear circuit elements with constituent relations such as v = i3R, or, i = K(ev/VT − 1). Theresulting set of equations that arise will be nonlinear. Computer solution of such circuits makes useof another technique called linearization, which is discussed in Chapter 4. Further discussions oflinearity are in Chapter 3, and a further treatment of nonlinear circuits is in Chapter 4.

107c

e x a m p l e 3.9 e v e n m o r e o n t h e n o d e m e t h o d Aswe discussed earlier, it is often inefficient to use only Kirchhoff’s laws to analyze com-plicated circuits. For example, if we simply modify the example we saw on page 192to the circuit shown in Figure 3.18, Kirchhoff’s laws alone will not be able to solve iteasily. We will use the node method to solve the problem and the node assignment inFigure 3.19.

With respect to the node assignment in Figure 3.19, we have the following equations:

V − e1

R1+ e2 − e1

R2+ e3 − e1

R3= 0 (3.29)

0 − e2

R4+ e1 − e2

R2+ e3 − e2

R6= 0 (3.30)

e1 − e3

R3+ e2 − e3

R6+ 0 − e3

R5= 0. (3.31)

We can rearrange the terms and express the equations in matrix form:

1R1

+ 1R2

+ 1R3

− 1R2

− 1R3

− 1R2

(1

R2+ 1

R4+ 1

R6

)− 1

R6

− 1R3

− 1R6

(1

R3+ 1

R5+ 1

R6

)

e1

e2

e3

=

VR1

0

0

R1v2

v3

R5

+

-V

v1 R2

v4

v5

R3

+

+

+

+

+-

-

-

-

-

iS

i3

i2

i4

i5

i1

R6

v6+

-

i6R4

F IGURE 3.18 Circuit withappropriate branch variables.

135a

F IGURE 3.19 Nodeassignments of the circuit.

R1v2

v3

R5

+

-V

v1

R2

v4

v5

R3

+

+

+

+

+-

-

-

-

-

R6

v6+

-

e1

e2

e3

R4

Standard matrix techniques can be used to solve for the unknowns. Let us assign thefollowing values to the resistors and voltage source:

V = 5 V

R1 = 50

R2 = 100

R3 = 100

R4 = 75

R5 = 75

R6 = 150 .

Then we have:

125

−1100

−1100

−1100

3100

−1150

−1100

−1150

3100

e1

e2

e3

=

110

0

0

Solving for e1, e2, and e3, we have e1 = 35/11 V, e2 = 15/11 V, and e3 = 15/11 V.Notice that e2 = e3, that is, there is no current going through resistor R6. Since R2 = R3

and R4 = R5, the symmetry of the network between node e1 and ground splits thecurrent going into node e1 evenly, thus causing the same voltage drop.

135b

e x a m p l e 3.12 a m o r e c o m p l e x d e p e n d e n t - c u r r e n ts o u r c e p r o b l e m As a more complex example of the node analysis of acircuit containing dependent sources, consider the analysis of the circuit shown inFigure 3.28. This circuit has two dependent sources: one VCCS and one CCVS.In addition, its resistors are labeled with their conductances for convenience.

To analyze the circuit in Figure 3.28, we redraw it as shown in Figure 3.29. Here, theVCCS is replaced by an independent current source having value I, and the CCVS isreplaced by an independent voltage source having value V. Note that the new indepen-dent voltage source is not a floating voltage source because it is connected to groundthrough the known voltage V.

The circuit in Figure 3.29 can be analyzed by the node method presented earlier. Sinceground is already defined in the figure at Node 5, Step 1 is already complete. Tocomplete Step 2, the node voltages are labeled as shown. The voltages at Nodes 1 and2 are the unknown node voltages e1 and e2. The voltage at Node 3 is set by the originalindependent voltage source, and is labeled accordingly. The voltage at Node 4 is alsoknown since the new voltage source is an independent source, and it is labeled as such.

Next, we perform Step 3, writing KCL for Nodes 1 and 2 in the process. This yields

G1(e1 − V − V) + G2(e1 − e2) − I = 0 (3.64)

G1

G4

ri

e2

Node 4

Node 2

Node 1

G2

V+

-

Node 3G3

e1

Node 5

+

-

V

i

I

gv

+- v

F IGURE 3.28 A circuit with twodependent sources.

145a

F IGURE 3.29 The circuit fromFigure 3.28 redrawn withindependent sources.

G1

G4

e2

Node 4

Node 2

Node 1

G2

V+

-

Node 3G3

e 1

Node 5

V

i

I

+- v

+

-V

V + V

I

for Node 1, and

G2(e2 − e1) + G3(e2 − V ) + G4e2 + I − I = 0 (3.65)

for Node 2. Equations 3.64 and 3.65 can be restated as

[G1 + G2 −G2

−G2 G2 + G3 + G4

][e1

e2

]=[

1 G1 0 G1

−1 G3 1 0

]IVIV

. (3.66)

Following Step 4, Equation 3.66 is solved for e1 and e2. This yields

[e1

e2

]= 1

[G2+G3+G4 G2

G2 G1+G2

][1 G1 0 G1

−1 G3 1 0

]IVIV

= 1

[(G3+G4)I+(G1(G2+G3+G4)+G2G3)V+G2 I+G1(G2+G3+G4)V

−G1I+(G1G2+G1G3+G2G3)V+(G1+G2)I+G1G2V

]

(3.67)

145b

where

= (G1 + G2)(G2 + G3 + G4) − G22. (3.68)

Finally, we use Equations 3.67 and 3.68 to solve for i and v, the branch variables thatcontrol the CCVS and the VCCS, respectively. This yields

i = I − G4e2

= 1

[G1G4I − (G1G2 + G1G3 + G2G3)(G4V − I ) − G1G2G4V

](3.69)

v = e1 − V − V

= 1

[(G3 + G4)I − G2G4V + G2 I − G2(G3 + G4)V

], (3.70)

which completes the node analysis of the circuit in Figure 3.29. Note that KCL was usedat Node 5 to derive the first equality in Equation 3.69.

To find the actual values for I and V, we now substitute Equations 3.69 and 3.70 intothe element laws for the CCVS and the VCCS, respectively. This yields

V = ri = r

[G1G4I − (G1G2 + G1G3 + G2G3)(G4V − I ) − G1G2G4V

](3.71)

for the CCVS, and

I = gv = g

[(G3 + G4)I − G2G4V + G2 I − G2(G3 + G4)V

](3.72)

for the VCCS. Finally, Equations 3.71 and 3.72 are jointly written as

[ − gG2 gG2(G3 + G4)

−r(G1G2 + G1G3 + G2G3) + rG1G2G4

][I

V

]

=[

g(G3 + G4) −gG2G4

rG1G4 −rG4(G1G2 + G1G3 + G2G3)

][I

V

](3.73)

and then solved simultaneously to yield

[I

V

]=

[g(G3 + G4) −gG2G4(1 − rG3)

r(G1G4 + gG3) rG4(G1G2 + G1G3 + G2G3)

][I

V

]

+ rG1G2G4 − gG2(1 − rG3). (3.74)

The actual values of the dependent sources are now known. Finally, to complete thenode analysis, at least to the point of determining e1 and e2, Equation 3.74 is substituted

145c

into Equation 3.67 to yield

[e1

e2

]=

[G3(1 + rg) + G4(1 + rG1) − G2G4 − rG1G3G4 − gG2(1 − rG3)

g − G1 G1G2 + G1G3 + G2G3 − gG2(1 − rG3)

][IV

]

+ rG1G2G4 − gG2(1 − rG3).

(3.75)

Now, with Equations 3.74 and 3.75, all node voltages are known and so allbranch variables may be computed explicitly.

As was the case for the circuit in Figure 3.26, it is also possible to apply the simple nodeanalysis described in Subsection 3.3 to the circuit in Figure 3.28. However, for the lattercircuit, the savings in time is not as great because some effort and thought is neededto express i and v explicitly in terms of e1 and e2. Furthermore, since these expressionscan be obtained in several different ways, the simple analysis becomes somewhat ad hocwhen applied to the circuit in Figure 3.28.

To begin the simple node analysis of the circuit in Figure 3.28, we express i and vexplicitly in terms of e1 and e2. The ability to do so will be needed to carry out the spiritof Step 3. From the definition of v in Figure 3.28, it is apparent that

v = e1 − V − ri. (3.76)

Thus, v can easily be expressed explicitly in terms of e1 and e2 once i is so expressed.One relatively convenient way to express i explicitly in terms of e1 and e2 is to combineKCL applied at Nodes 1, 3, and 4. This results in

i = I + G2(e2 − e1) + G3(e2 − V). (3.77)

The first term on the right-hand side of Equation 3.77 is the current through theindependent current source, and the second term on the right-hand side is the cur-rent through the resistor labeled G2. These two currents combine at Node 1, and theirsum exits Node 1 through the resistor labeled G1. Finally, the combined current passesthrough Node 4 and the CCVS, before entering Node 3. At Node 3, the combinedcurrent also combines with the current through the resistor labeled G3, and togetherthey exit Node 3 as i. The last term on the right-hand side of Equation 3.77 is thecurrent through the resistor labeled G3. Thus, Equation 3.77 does express KCL appliedto Nodes 1, 3, and 4. Finally, the substitution of Equation 3.77 into Equation 3.76 yields

v = e1 − V − r (I + G2(e2 − e1) + G3(e2 − V)), (3.78)

which expresses v explicitly in terms of e1 and e2.

Next, we apply the simple node method, beginning with Step 3, yielding

0 = G1v + G2(e1 − e2) − I, (3.79)

145d

for Node 1 and

0 = I + G2(e2 − e1) + G3(e2 − V ) + G4e2 − g v (3.80)

for Node 2. At this point Equations 3.79 and 3.80 still contain v. However, uponsubstitution of Equation 3.78, they can be rewritten as

[G1 + G2 + rG1G2 −G2 − rG1(G2 + G3)

−G2 − g − rgG2 G4 + (1 + rg)(G2 + G3)

][e1

e2

]

=[

1 + rG1 G1(1 − rG3)

−1 − rg G3(1 + rg) − g

][IV

]. (3.81)

Finally, following Step 4, Equation 3.81 can be solved to yield

[e1

e2

]=

[G3(1 + rg) + G4(1 + rG1) − G2G4 − rG1G3G4 − gG2(1 − rG3)

g − G1 G1G2 + G1G3 + G2G3 − gG2(1 − rG3)

][IV

]

+ rG1G2G4 − gG2(1 − rG3),

(3.82)

which is identical to Equation 3.75, as it should be. The main point here is that whilethe application of the simple node analysis described in Section 3.3 to circuits containingdependent sources can result in less work, it also generally becomes less structured. Thisis because, as part of the analysis, it is necessary to determine the variables that controlthe dependent sources explicitly in terms of the unknown node voltages before the nodeanalysis is actually completed. It may not always be obvious how to do this in a simpleway. For this reason, when it is necessary to carry out a well-structured node analysis,such as when the analysis is to be computerized, then the node analysis presented in thissubsection is preferred.

145e

3.3.4 T H E CONDUC T ANC E AND SOU R C E MA T R I C E S *

As we saw earlier in Equation 3.27, when a resistive circuit is linear (that is,when its resistors and dependent sources are all linear), the equations resultingfrom Step 3 of a node analysis can be formulated as a matrix equation, whichtakes the form

G e = S s. (3.83)

Here, e is a vector of the unknown node voltages, s is a vector of the knownindependent source amplitudes, and G and S are known matrices, referred tohere as the conductance and source matrices, respectively. Examples of suchequations can be seen in Equations 3.27 and 3.66.

As previewed in the discussion following Equation 3.27, the matrices Gand S have a very special structure. This structure allows us to skip the details ofStep 3 of a node analysis, and derive the two matrices directly from the topol-ogy of the circuit. This also facilitates the computerization of a node analysis.Alternatively, the special structure of the two matrices can be used to checkour work during Step 3. For simplicity, in this subsection we will examinethe structure of G and S that arises from circuits that contain neither floatingvoltage sources nor dependent sources. However, it is possible to extend ourobservations to accommodate these sources as well.

The special structure of G and S can be exposed by studying the partialcircuit shown in Figure 3.30. By the end of Step 3 of a node analysis, oneexpression of KCL has been derived in terms of the unknown node voltages foreach node having an unknown node voltage. In the case of the partial circuit in

F IGURE 3.30 A partial circuit. G2

e3e2

e1

G1

V+

-

G3

I

Node 1

Node 2Node 3

V

145f

Figure 3.30, the corresponding expression of KCL for Node 3 is

G1(e3 − e1) + G2(e3 − e2) + G3(e3 − V ) − I = 0. (3.84)

In writing Equation 3.84, KCL has been taken to state that the sum of thecurrents exiting a node must vanish. Next, we rearrange Equation 3.84 as

−G1e1 − G2e2 + (G1 + G2 + G3)e3 = G3V + I. (3.85)

By writing KCL as in Equation 3.85, the special structure of the expressionbecomes apparent. For example, the conductance of each resistor connectedto Node 3 contributes positively to the coefficient of e3, and negatively to thecoefficient of the node voltage at the other end of the resistor. This is becausee3 acts to drive currents out from Node 3, while the other node voltages actto drive currents in to Node 3. The same observation holds for the coefficientof the grounded independent voltage source, except for a change in sign due tothe fact that the corresponding term is moved to the opposite side of the equalsign. We also see that the current source enters positively into Equation 3.85,once its term is moved to the opposite side of the equal sign, since it sourcescurrent into Node 3.

Now consider assembling Equation 3.85, and its counterparts from theother nodes in the circuit, in the form of Equation 3.83. Each expression ofKCL becomes a row within Equation 3.83. For the sake of discussion, let usassume that these rows are ordered according to the number of the node forwhich they are written, and further that the node voltages in e are listed in orderof their corresponding node numbers. In this case, Equation 3.85 enters intoEquation 3.83 as

.

.

.−G1 −G2 G1 + G2 + G3 0 · · ·...

e1e2e3e4

.

.

.

=

.

.

.1 G3 · · ·...

I

V

.

.

.

.

(3.86)

Thus, we see that G is a matrix of conductances. A diagonal element at theposition [m, m] in G is the sum of the conductances connected Node m. Anoff-diagonal element at the position [m, n] in G, m = n, is the negative ofthe conductance connecting Nodes m and n. This is true even for the zeroelements within G since a zero conductance indicates the absence of a resistor,

145g

or no connection. As a consequence of this structure, G is symmetric about itsmain diagonal, at least in the absence of dependent sources.

Similarly, the matrix S contains the coefficients of the sources. For eachindependent current source, there will be a +1 in its column in S at Row m ifthe source enters Node m, a −1 if the source exits Node m, and a 0 otherwise.For each grounded independent voltage source, the conductance connecting itto Node m will appear in Row m of its column in S, including zeros to indicatethe absence of a connecting resistor.

Again, the structure of G and S can be seen in Equations 3.27 and 3.66.Consider, for example, the matrices in Equation 3.27. The [1,1] element of G isG1 +G2 +G3 because the resistors labeled G1, G2, and G3 are all connected toNode 1. Similarly, the [2,2] element in G is G3+G4 because the resistors labeledG3 and G4 are both connected to Node 2. The [1,2] and [2,1] elements in G areboth −G3 since G3 connects Nodes 1 and 2. Since the voltage source connectsto Node 1 through the resistor labeled G1, but does not connect to Node 2, the[1,1] element of S is G1 and the [2,1] element is zero. Similarly, since the currentsource enters Node 2, but does not connect to Node 1, the [2,2] element of Sis +1 and the [1,2] element is zero. Thus, the matrices in Equation 3.27 couldhave been derived by inspection of the circuit topology only.

145h

3.4 LOOP METHOD *

We have already seen several examples of a complementary relationshipbetween voltage and current, so it should come as no surprise that there isa simplified analysis method based on an astute choice of current variables thatclosely parallels the method in the preceding section. Here we choose currentvariables that flow in loops, that is, in closed paths. By this definition, the currentflowing into any node will always be identically equal to the current flowingout, so KCL is identically satisfied. As in Chapter 2, we continue to define loopcurrents until every element is traversed by at least one loop current. To illus-trate, let us define a set of current loops for the circuit we previously analyzed,as in Figure 3.31. KCL at Node 1 gives

(i1 + i2) − i1 − i2 = 0 (3.87)

which is identically zero for all values of i. Thus because KCL is automaticallysatisfied for this choice of current variables, we have to write only KVL and theconstituent relations. Combining these in one step, we obtain

−V + (i1 + i2)R1 + i1R2 = 0 (3.88)

−i1R2 + i2R3 + (i2 + I )R4 = 0. (3.89)

Now rewrite to place the source terms on the left:

V = i1(R1 + R2) + i2R1 (3.90)

IR4 = i1R2 − i2(R3 + R4). (3.91)

R1

R2

+

R3

-V R4

I

1 2Node Node

I

i1

i2

F IGURE 3.31 Loop currents.

145i

By Cramer’s Rule,

i1 = V(R3 + R4) + IR4R1

(R1 + R2)(R3 + R4) + R1R2. (3.92)

The voltage across R2 can now be found from Equation 3.92 and

e1 = i1R2. (3.93)

Equations 3.92 and 3.93 can be reduced to Equation 3.8 by simple algebra.

145j

e x a m p l e 3.13 l o o p m e t h o d Let us use the loop method to analyzethe circuit depicted in Figure 3.18 in our previous example. Figure 3.32 shows our choiceof the loops for this circuit.

The corresponding loop equations are

−V + i1R1 + (i1 − i2)R2 + (i1 − i3)R4 = 0 (3.94)

(i2 − i1)R2 + i2R3 + (i2 − i3)R6 = 0 (3.95)

(i3 − i1)R4 + (i3 − i2)R6 + i3R5 = 0. (3.96)

By rearranging the terms into matrix form, we obtain

R1 + R2 + R4 −R2 −R4

−R2 R2 + R3 + R6 −R6

−R4 −R6 R4 + R5 + R6

i1

i2i3

=

V

00

.

Assigning the same values to the voltage source and resistors,

V = 5 V

R1 = 50

i1 i2

i3

+

-V

(b)

(c)(d)

R2

R1

R6

R3

R5

R4

(a)

F IGURE 3.32 Circuit withproperly assigned current loops.

145k

R2 = 100

R3 = 100

R4 = 75

R5 = 75

R6 = 150

we obtain 225 −100 −75

−100 350 −150−75 −150 300

i1

i2i3

=

5

00

.

Solving, we have i1 = 2/55 A, i2 = 1/55 A, and i3 = 1/55 A. As a sanity check, thecurrent flowing through R6 is i2 − i3 = 0, as desired.

145l

e x a m p l e 3.17 s u p e r p o s i t i o n a p p l i e d t o a b e e h i v en e t w o r k Superposition and a bit of creativity can also be used to solve morecomplicated resistive networks. Figure 3.45 shows a resistive network containing aninfinite plane of resistors in a beehive shape. Each of the resistors have a resistancevalue R. What is the equivalent resistance Reqv when looking into port A-B?

One of the key ideas of this problem is to properly choose a reference node or aground node for measuring voltages of the internal nodes in the network. Referringto Figure 3.46, we take ground at infinity. Then, we introduce a current IP into node Ausing a current source, and draw IP out of node B using another current source. If wecan compute the resulting voltage VP between nodes A and B, then we can obtain theeffective resistance between A and B as

Reqv = VP

IP.

Our circuit has two sources, one injecting a current IP into the network, and the otherdrawing a current IP out of the network. We will determine the voltage VP usingsuperposition by adding the voltages across A and B resulting from each of the currentsources acting alone. Figure 3.47 shows the circuit with the current source at B

B

AF IGURE 3.45 An infinite planeresistive network. Each resistor hasa resistance value R.

153a

F IGURE 3.46 Introducingground into the network. B

A

IP

IP

VP

+

-

F IGURE 3.47 The circuit withonly the current source at A beingapplied.

B

A

IP

i1

i2

i3

VP1

+

-

153b

B

A

IPi6

i4i5

VP2

+

-F IGURE 3.48 The circuit withonly the current source at B beingapplied.

turned off, and Figure 3.48 shows the circuit with the current source at A turned off. LetVP1 be the voltage across A and B when the current source at A acts alone, and let VP2

be the voltage across A and B when the current source at B acts alone. By superposition,we know that

VP = VP1 + VP2.

Referring to Figure 3.47, the current IP injected into node A will split evenly into threecurrents, i1, i2, and i3. We know that

i1 = i2 = i3

because the injected current faces a symmetric situation in each of the three directions.Since, by KCL,

IP = i1 + i2 + i3,

we can write

i1 = i2 = i3 = IP3

.

153c

Since the current through the resistor connecting nodes A and B is

i1 = IP/3

and since the resistance value of the resistor is R, we can write

VP1 = Ri1 = RIP3

.

Similarly, referring to Figure 3.48, the current IP drawn out of node B comprises threecomponents i4, i5, and i6, where

i4 = i5 = i6.

Since, by KCL,

IP = i4 + i5 + i6,

we can write

i4 = i5 = i6 = IP3

.

And in like manner, since the current through the resistor connecting nodes A and B is

i4 = IP/3,

and since the resistance value of the resistor is R, we can write

VP2 = Ri4 = RIP3

.

Composing the expressions for VP1 and VP2 we get

VP = VP1 + VP2 = 2IP3

R.

Therefore,

Reqv = VP

IP= 2

3R.

153d

e x a m p l e 4.5 n o d e m e t h o d This example uses the device shown inFigure 4.5. Recall that this device is characterized by the following device equation:

iD = 0.1v 2D for vD ≥ 0, (4.17)

iD is given to be 0 for vD < 0.

iD

v1

+

-V+

-

v2

+

-

D1

D2

F IGURE 4.14 Nonlinear devicesconnected in series.

Referring to the series connected nonlinear devices in Figure 4.14, determine iD, v1, andv2, given that V = 2 V.

We will use the node method to solve this problem. We first select a ground node andlabel node voltages as shown in Figure 4.15. We have one unknown node voltage v2.

Next, we write KCL for the node with the unknown node voltage. Recall that theKCL equations in the node method are written directly in terms of the node voltages.Accordingly,

0.1v 22 = 0.1(V − v2) 2.

The term on the left-hand side is the current through device D2. Similarly, the term onthe right-hand side is the current through device D1.

iD

V+

-v2

D1

D2

V

F IGURE 4.15 Circuit with nodevoltages labeled.

Solving, we get

v2 = V

2.

Given that V = 2V, we get v2 = 1V. We now obtain the remaining voltages andcurrents by applying KVL and the relevant device laws. Thus,

v1 = V − v2 = 1 V

and

iD = 0.1v 22 = 0.1 A.

Notice that we could have also solved the circuit intuitively by realizing that the samecurrent flows through two identical nonlinear devices. Thus, the same voltage mustdrop across both. In other words,

v1 = v2.

Furthermore, by KVL

2 V = v1 + v2.

Or, v1 = v2 = 1 V.

201a

e x a m p l e 4.8 m a k i n g s i m p l i f y i n g a s s u m p t i o n sSometimes, there are a few special cases of interest that can be solved analytically bymaking appropriate simplifying assumptions. The circuit in Figure 4.19 is one suchexample. Here for variety, we will solve the circuit by a direct application of KVL andKCL. KVL around the path containing the voltage sources and the diodes yields

−2E + vD1 − vD2 = 0 (4.28)

and KCL at the junction of the two diodes gives

iD1 + iD2 = IA. (4.29)

These two equations, together with the equations for the diodes of the form ofEquation 4.1, can be solved for the diode currents, assuming identical diodes.

Now, if we assume that the diode voltages are always positive enough to makethe −1 term in the diode equation negligible (for Equation 4.1, true within less thanone percent for all vD larger than 125 mV), then iD1 becomes

iD1 = IA1 + e−2E/VTH

. (4.30)

We can obtain this equation by following these steps. First, substitute in Equation 4.28expressions for vD1 and vD2 in terms of iD1 and iD2 derived from the diode equations(neglecting the −1 term). Second, obtain iD2 in terms of iD1 from this equation, substitutein Equation 4.29, and simplify to get Equation 4.30.

The diode current is thus a hyperbolic tangent function of the voltage E, except for anoffset of IA/2.

F IGURE 4.19 Hyperbolictangent generator.

-

+

-

+vD1

vD2

E

iD1

iD2

-

+

IA

-

+

E

203a

e x a m p l e 4.9 v o l t a g e - c o n t r o l l e d n o n l i n e a rr e s i s t o r Let us now determine vO as a function of vI for the circuit inFigure 2.71 when

RX = f (vI) = Ro

vI − 1 V.

where Ro = 10 kV.

We have,

vO = VRX

RL + RX

= VRo

vI−1v

RL + RovI−1

v

= VRo

RL(vI − 1 V ) + Ro.

Substituting, Ro = 10 kV and RL = 10 k,

vO = V10 kV

10 k(vI − 1 V ) + 10 kV

= V

vI

= V(V2

)= 2 V.

203b

e x a m p l e 4.13 h a l f - w a v e r e c t i f i e r r e - e x a m i n e dAs another example of piecewise linear analysis, we re-examine the half-wave rectifiercircuit for a sinusoidal input previously analyzed using graphical analysis in Section 4.10.This time around, we will use a piecewise linear model for the diode, but use the samegraphical approach of Section 4.10.

Thus we start with the same circuit topology as in Figure 4.21a, except that the diodeis modeled using its piecewise linear approximation, the ideal diode, as shown inFigure 4.32a. Assuming as before a ten-volt sinusoidal input voltage, as might be typicalin power supplies, we draw a succession of load lines on the piecewise linear characteris-tics, Figure 4.32b, for representative values of the input wave, and plot the output voltagepoint by point. The desired output voltage is vR, which in the graph is the horizontal

F IGURE 4.32 Half-waverectifier: ideal diode piecewiselinear analysis.

+-

+

-

R vRE Eo ωt( )cos=

iD

vDE

vR

Slope = -1/R

t

vR

(a)

(b)

(c)

214a

distance from the operation point intersection to the input voltage. The resulting outputwave is shown in Figure 4.32c.

Comparison with the previous analysis, Section 4.10 and Figure 4.21, indicates thatat least for this problem, the simple ‘‘ideal diode’’ approximation yields a reasonablyaccurate answer. As one would expect, the error mainly derives from the neglect of the0.6-V drop across the diode. Clearly, the error would be more objectionable if the inputsinusoid had been of one volt peak rather than 10 volts.

214b

4.4.1 I M P R O V E D P I E C EW I S E L I N E A R MOD E L SF O R NON L I N E A R E L EM EN T S *

The accuracy of the results of a piecewise liner analysis depends on the accuracyof the model used. In this section, we will discuss the process of creating moreprecise models of nonlinear elements when increased accuracy is desired.

To illustrate the process, let us use the diode as an example of a nonlinearelement. Thus far, we used the simple, ideal diode model. It is obvious from thepreceding example that the major effect in the model is when the voltage vDacross the diode is positive, and above about 0.6 V. Substantial improvementcan be made by adding a 0.6-V source in series with the ideal diode, as shown inFigure 4.33a. The corresponding i v characteristic for the improved piecewiselinear model is shown in Figure 4.33b. Let us work a simple example using thispiecewise linear model.

F IGURE 4.33 Improvedpiecewise linear diode models.

+

-

+

-0.6 V

(a)

(c)

iD

vD

iD

vD

0.6 V

(b)

+

-

+

-0.6 V

iD

vD

Rd

iD

vD

0.6 V

(d)

Slope =1

Rd

-----

214c

e x a m p l e 4.14 a n o t h e r e x a m p l e u s i n g p i e c e w i s el i n e a r m o d e l i n g Let us rework the example containing a voltage source,resistor, and diode in Figure 4.16 using the piecewise linear model for the diode fromFigure 4.33b. The behavior of this model, comprising an ideal diode in series with avoltage source, can also be summarized in two statements:

Diode ON (vertical segment): vD = 0.6 V for iD > 0

Diode OFF (horizontal segment): iD = 0 for vD < 0.6 V (4.47)

Let us determine iD for E = 3 V and E = −5 V, given that R = 500 . According tothe piecewise linear method, we will focus on one straight-line segment at a time, usinglinear analysis within each segment.

Vertical segment When iD and vD are in the vertical segment of their characteristic,the circuit shown in Figure 4.34b results, and we can write

iD = E − 0.6 V

R. (4.48)

Horizontal segment Figure 4.34c shows the corresponding circuit when the diode isoperating as an open circuit. In this segment,

iD = 0. (4.49)

Combining the results Intuition tells us that the vertical segment applies whenE > 0.6 V (the diode turns on) and the horizontal segment applies otherwise (diodeis off). Thus, when E = 3 V, Equation 4.48 applies, and

iD = E − 0.6 V

R= 3 − 0.6

500= 4.8 mA.

Comparing to Equation 4.40, notice that the value of iD predicted by this improvedmodel is slightly lower than that predicted by the ideal diode model. The ideal diodemodel did not account for the 0.6-V drop across the diode, and so overestimatedthe current.

Equation 4.49 applies when E = −5 V, so

iD = 0.

214d

F IGURE 4.34 Piecewise linearanalysis in the vertical and horizon-tal straight-line segments using thediode model containing a voltagesource.

-

+R

-+

vD

iD

vR

(a) Complete model

-

+R

-+

vD

iD

vR

(b) Vertical segment

-

+R

-+

vD

iD

vR

(c) Horizontal segment

-

+E

-

+E

0.6 V

0.6 V

0.6 V-

+E

Further improvement in accuracy can be realized by adding a series resistor Rd ofsuitable value to the ideal diode and voltage source, as shown in Figure 4.33c.The specific choice of resistor value depends on the application; one shouldstrive to make the characteristic match over the range of diode current expectedin the specific circuit (see Figure 4.35). We will illustrate the use of this model inan example. More examples using these and other more complicated piecewisemodels will appear throughout the book, and specifically in Chapters 7 and 16.

214e

e x a m p l e 4.15 t h e d i o d e r e s i s t a n c e Choose values for Rdfor the piecewise linear diode model in Figure 4.33c assuming that the resistance mustprovide a reasonable match for currents up to 0.4 A and 1 A. Assume VTH = 0.025 Vand Is = 10−12 A.

Figure 4.35 plots the v i characteristics for the diode. The figure shows that the resistancevalue Rd1 = 0.1 provides a good match for the diode v i characteristics up to 1 A,while the resistance value Rd2 = 0.2 provides a better match in the smaller currentrange from zero to 0.4 A.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.10.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

vD (V)

i D (

A)

Slope = 10, Rd1 = 0.1 Ω

Slope = 5, Rd2 = 0.2 Ω

F IGURE 4.35 Choosing a valueof the resistance in the piecewiselinear diode model.

214f

e x a m p l e 4.16 a m o r e c o m p l i c a t e d p i e c e w i s el i n e a r m o d e l Let us further rework the previous example using the piece-wise linear model for the diode from Figure 4.33c. The behavior of this model,comprising an ideal diode in series with a voltage source and a resistor, can besummarized in two statements:

Diode ON (vertical segment): vD = 0.6 V + iDRd for iD > 0.

Diode OFF (horizontal segment): iD = 0 for vD < 0.6 V.

(4.50)

Again, let us determine iD for E = 3 V and E = −5 V, given that R = 500 andRd = 10 .

Vertical segment When iD and vD are in the vertical segment of their characteristic,the circuit shown in Figure 4.36b results, and we can write

iD = E − 0.6 V

R + Rd. (4.51)

Horizontal segment Figure 4.24c shows the corresponding circuit when the diode isoperating as an open circuit. In this segment,

iD = 0. (4.52)

Combining the results For E = 3 V, Equation 4.51 applies, and so

iD = E − 0.6 V

R + Rd= 3 − 0.6 V

500 + 10= 4.7 mA.

Equation 4.52 applies when E = −5 V, so

iD = 0.

As illustrated using the diode, increasingly better fits to an actual nonlineardevice characteristic can be obtained by introducing more and more idealelements. For example, for the diode, increasingly better fits to the actualdiode characteristic can be obtained by introducing more and more ideal diodes,batteries, and resistors. But again a price is paid; increased accuracy of themodel brings increased complexity. The proper compromise between simplic-ity and accuracy is not always obvious. Start with the simplest model, then addcomplexity to see if the solution changes in major ways.

214g

-

+R

-+

vD

iD

vR

(a) Complete model

-

+R

-+

vD

iD

vR

(b) Vertical segment

(c) Horizontal segment

-

+E

-

+E 0.6 V

0.6 V

Rd

Rd

-

+R

-+

vD

iD

vR

-

+E 0.6 V

Rd

F IGURE 4.36 Piecewise linearanalysis in the vertical and horizon-tal straight-line segments using thediode model containing a voltagesource and a resistor.

214h

e x a m p l e 4.21 d i o d e r e g u l a t o r To further illustrate the use ofincremental analysis, we examine the diode circuit shown in Figure 4.45, another crudeform of voltage regulator that is slightly better than our previous regulator. As before,we assume that the supposedly DC source supplying the circuit in reality has 5 voltsof DC with 50 millivolts of AC superimposed. The regulator is designed to reduce thisunwanted AC component relative to the DC.

To understand how the circuit operates, first draw the DC subcircuit to determineID and VO, the operating point variables of the circuit. We will use the piecewiselinear analysis method (based on the piecewise linear model of the diode shown inFigure 4.33c) to determine the operating point variables. Accordingly, Figure 4.45bshows the DC subcircuit in which each diode has been replaced with its piecewise linearmodel comprising an ideal diode, a 0.6-V voltage source and a resistor of value Rd. Byinspection From Figure 4.45b,

ID = 5V − 1.8V

R + 3Rd. (4.84)

For R = 1000 and Rd = 10 , a reasonable value for diode currents in the 1- to10-mA range,

ID = 3.2

1030= 3.1 mA. (4.85)

Next, draw the incremental subcircuit, as shown in Figure 4.45c. Here we will usethe accurate v i relation for the diode from Equation 4.1 to compute the value of

F IGURE 4.45 Diode regulator.

+

-

vOTotal

50 mV AC

5 V DC

+-

+-

R

source

+

-

VO5 V DC+-

0

R

+-1.8 V

3 Rd

(a)

(b) DC subcircuit

+

-

vo

50 mV AC+-

0

R

3 rd ∆

(c) Incremental AC subcircuit

228a

the incremental diode resistance rd. This incremental resistance can be derived usingEquation 4.75, in which f is the diode v i relation. We have also seen that the applica-tion of Equation 4.75 for the diode v i relation results in Equation 4.74, which directlyyields the value of rd as

rd = 25 mV

3.1 mA 8.1 . (4.86)

Now, from Figure 4.45c, we can write an expression for the small signal AC output

vo = 503rd

3rd + R= 50

24.3

24.3 + 1000= 1.19 mV AC. (4.87)

(From Equation 4.66, with vo equal to 1.19 mV we expect an error of about 2%in the neglect of higher-order terms in the incremental analysis.)

The total DC output voltage of the regular can be found from the DC subcircuit,Figure 4.45b,

VO = 1.8 + 3IDRd (4.88)

= 1.8 + 3 × 3.1 × 10−3 × 10 = 1.89 V. (4.89)

The fractional ripple at the input,

fractional ripple = 50 × 10−3

5= 10−2 (4.90)

and at the output,

fractional ripple = 1.19 × 10−3

1.89 10−3 (4.91)

so the ripple has been reduced relative to the DC by a factor of 10.

228b

e x a m p l e 4.22 s m a l l s i g n a l a n a l y s i s u s i n g ap i e c e w i s e l i n e a r d i o d e m o d e l In the diode regulator exam-ple, we used the piecewise linear model for the diode when conducting the DC operatingpoint analysis, but reverted to the accurate diode equation when computing the small sig-nal resistance. This example will illustrate that small signal analysis of nonlinear devicescan also be carried out by using their piecewise linear models for both the DC operatingpoint analysis and in computing the small signal device resistance. Of course, the accu-racy of the results will depend on the fidelity of the piecewise linear model used for thenonlinear device.

The example will be based on the simple diode-resistor circuit shown in Figure 4.46.Let us suppose we are interested in the small signal values of the output voltage andthe diode current for a 50-mV incremental input. As promised, throughout this exam-ple, we will use the piecewise linear model for the diode illustrated in Figures 4.33aand 4.33b.

We start by drawing the DC subcircuit to determine the operating point variablesID, VO as shown in Figure 4.46b. By inspection, we can write

ID = 5 − 0.6

R.

For R = 1000 , ID = 4.4 mA and VO = 0.6 V.

F IGURE 4.46 A simplediode-resistor circuit.

+

-

vO

50 mV

5 V

+

-

+

-

R

+

-

VO5 V+

-

0

R

0.6 V

(a) Total circuit

(b) DC subcircuit

+

-

vO

50 mV+-

0

R

rd = 0

(c) Incremental subcircuit

iD

ID

id

228c

Next, we draw the incremental subcircuit for the operating point given by ID = 4.4 mAand VO = 0.6 V. Since we chose to use the piecewise linear model for the diodethroughout our analysis, we must derive rd based on this model. Since ID > 0, noticethat the diode is operating in the vertical segment of the piecewise linear v i curve shownin Figure 4.33b. Since the reciprocal of the slope of this curve segment is zero, rd is alsozero. In other words, the ideal diode looks like a short circuit for incremental changesin the current. Figure 4.46c shows the corresponding incremental subcircuit.

From Figure 4.46c, it is easy to see that the incremental change in the output voltagefor the 50-mV change in the input voltage is simply

vo = 0.

Similarly, the incremental change in the current is given by

id = 50 mV

R= 50 µA.

228d

e x a m p l e 5.14 s i m p l i f y i n g a n o t h e r l o g i ce x p r e s s i o n (a) Find the minimum sum-of-products representation for theboolean expression in Equation 5.8, namely

Output = A B C D + A B C D + A B C D. (5.30)

(b) Further, show that the expression in Equation 5.30 is equivalent to the logicexpression in the caption of Table 5.7, namely

AB + C + D.

As directed in part (a), we will simplify the expression in Equation 5.30 as follows:

Output = A B C D + A B C D + A B C D

= A B C D + A B C D + A B C D + A B C D

= (A B C D + A B C D) + (A B C D + A B C D)

= A C D(B + B) + B C D (A + A)

= A C D · 1 + B C D · 1

= A C D + B C D. (5.31)

To answer part (b), recall that we have previously shown that AB + C + D can be sim-plified to A C D + B C D (see Equation 5.29). Since the expressions in Equations 5.29and 5.31 are identical, it follows that AB + C + D and A B C D + A B C D + A B C Dare equivalent.

267a

e x a m p l e 5.16 y e t a n o t h e r i m p l e m e n t a t i o n u s i n gn o r s Let us derive an implementation based on two-input NOR gates for thefunction AB + C + D. Assume that both the true and complement version of eachof the inputs is available:

AB + C + D = A B + (C + D) (5.35)

= A + B + C + D + C + D (5.36)

= ((A + B) + ((C + D) + C + D)). (5.37)

Implementing each of the expressions within parentheses using two-input NOR gates,we get the circuit shown in Figure 5.24.

Notice that the algebraic simplification process was quite cumbersome. We can actu-ally perform the same transformation directly on a gate-level circuit with greater ease.Figure 5.25 shows how the original circuit for AB + C + D from one of the implemen-tations in Figure 5.18 can be transformed into a two-input NOR implementation. Thetransformations exploit the fact that two inverters (or circles) in series cancel each other.

A

C

B

D

F IGURE 5.24 NOR implemen-tation of AB + C + D.

A

C

B

D

A

C

B

D

A

C

B

D

A

C

B

D

F IGURE 5.25 NOR trans-formations for AB + C + D.

267b

6.11 ACT I VE PULLUPS

Large valued resistors are difficult to fabricate in VLSI technology. For example,R is usually on the order of a few tens of ohms for polysilicon, few hundredsof ohms for diffusion, and few hundredths of an ohm for metal. Fabricating a10-k resistor using polysilicon would require an area hundreds of times largerthan that of a minimum sized transistor. Fortunately, MOSFETs themselvesmake good high-valued resistors for the same area, the resistance RON of aminimum sized MOSFET is significantly higher than that of a resistance madeout of other materials, such as polysilicon.

Figure 6.55 shows an inverter constructed out of MOSFETs with Mpuserving as an active pullup. The pullup MOSFET has its drain tied to the powersupply connection, and thus the drain has a voltage VS applied with respect toground. To keep the pullup MOSFET permanently in its ON state, its gate isconnected to a second voltage VA, where VA is at least one threshold voltagehigher that the supply voltage. In other words,

VA > VS + VT.

F IGURE 6.55 Logic gate withactive pullup. In the circuit,VA > VS + VT , so that the pullupMOSFET is always in its ON state.

VS

vIN

vOUT

Mpu

Mpd

VS

vOUT

RONpu

VS

vOUT

RONpu

vIN = High vIN = LowRONpd

W

L-----

pu

W

L-----

pd

VA

321a

Let the W/L ratios of the pullup and the pulldown MOSFETs be (W/L)pu and(W/L)pd, respectively. Let the corresponding ON-state resistances (accordingto the SR model) be RONpu and RONpd. We also know that

RON ∝ L

W

where the constant of proportionality is Rn.25

Let us now choose the respective (W/L) ratios so that the inverter satisfiesthe relationship derived in Equation 6.6, and repeated below for convenience:

VSRON

RON + RL< VT

This relationship between the output low voltage of the inverter and the thresh-old voltage of a MOSFET is necessary for the inverter to be able to drive theMOSFET in another inverter into its OFF state. In the preceding equation, RLis the resistance of the pullup device, and RON is the resistance of the pulldowndevice.

With both an active pullup and an active pulldown,

VT > VS1

1 + RL

RON

(6.12)

> VS1

1 + (L/W)pu

(L/W)pd

(6.13)

where we have substituted the L/W ratios in place of the resistance values.

25. As mentioned earlier, the MOSFET displays resistive behavior between its drain and its sourceonly when the drain voltage is much smaller than the gate voltage (specifically, vDS vGS − VT).Furthermore, the resistance Rn, and therefore RON, depends on the value of the applied gatevoltage. We will see more appropriate models for MOSFETs in other regions of operation in laterchapters. But for now, let us go ahead and use the SR model with a single value for Rn to analyzethe active pullup.

321b

For our typical parameters: VS = 5 V and VT = 1 V. Therefore,we get

51

1 + (L/W)pu

(L/W)pd

< 1 (6.14)

5 < 1 +

(LW

)pu(

LW

)pd

(6.15)

4 <

(LW

)pu(

LW

)pd

. (6.16)

In other words, we can choose the size of the pullup so its (L/W) ratio is fourtimes that of the pulldown.

321c

e x a m p l e 6.9 s i z i n g p u l l u p d e v i c e s For a 5-V supply volt-age, suppose our static discipline prescribes a VOL = 0.5 V. How do we size the pullupMOSFET in Figure 6.56 relative to the pulldown MOSFET to meet the valid output

vOUT

VS

RONpuLW-----

pu

∝

RONpdLW-----

pd

∝vIN

VA

F IGURE 6.56 An inverter withan active pullup.

low threshold?

When the pulldown device is on, we know that the output voltage is given by

vOUT = VSRONpd

RONpd + RONpu.

To satisfy the static discipline, we must have VOL > vOUT when the input is high. Recallthat the on-state resistance is proportional to the ratio of the device gate length L andits width W. Thus we have,

VOL > vOUT (6.17)

> VSRONpd

RONpd + RONpu(6.18)

> VS

(L/W

)pd(

L/W)pd + (L/W

)pu

(6.19)

> 51

1 +(L/W

)pu(

L/W)pd

. (6.20)

For VOL = 0.5 V, it is easy to see that if we choose(L/W)pu

(L/W)pd> 9 we will satisfy the static

discipline. In other words, if both devices are of the same width W, the pullup devicemust be sized so its length is nine times that of the pulldown device.

321d

e x a m p l e 6.10 c o m b i n a t i o n a l l o g i c u s i n g m o s f e ts w i t c h e s Let us now rework some of our previous examples using all-MOSFETdesigns and the SR model. Assume that we need to design our gates such that they satisfya static discipline with the low output voltage threshold VOL = V−

T V, where VT is givento be 1 V. Let us design all-MOSFET circuits and let us attempt to make them as smallas possible. Assume that the area of the circuit is proportional to the area of the gates(W × L) of the individual MOSFETs. Let us also compute the power dissipated by thecircuits. Assume that Rn for the MOSFETs is 1 k.

Let us first consider the expression: AB + C + D. Figure 6.57 shows a compound gatecomprising only MOSFETs that implements this expression. This gate design replacesthe load resistor in Figure 6.23 with an active pullup. Our task is to determine the sizesof both the pulldown and the pullup MOSFETs so this gate satisfies the static disciplinefor VOL = 1−V. Note that the gate must satisfy the static discipline for any combinationof inputs.

As we have seen before, the key issue in designing a NMOS logic gate is to choose therelative values of the pullup and the pulldown resistances so that even the highest valuefor the gate’s output low voltage satisfies the VOL constraint. Since we are asked todesign the circuit that occupies the least area, and there are more pulldown transistorsthan pullups, let us start by choosing minimum-sized transistors ((L/W )pd = 1) for thepulldown circuit. Therefore the on resistance of an individual pulldown MOSFET is

RONpd = Rn

(L

W

)pd

= Rn.

The highest value for the output low voltage occurs when the pulldown circuit has itshighest resistance. Notice that the pulldown circuit has its largest on-state resistancefor an output low when A and B are on, and C and D are off. This largest pulldownresistance is given by the sum of the on-state resistances of the MOSFETs with the A

F IGURE 6.57 Transistor-levelimplementation of AB + C + Dusing an active pullup. In the circuit,VA > VS + VT , so that the activepullup is in its ON state at all times.

VS

OUT

A

C DBWL-----

pd

WL-----

pu

VA

321e

and B inputs. That is,

Rpdmax = 2RONpd = 2Rn.

To satisfy the static discipline, the output voltage of the gate for a logical 0 must be lessthan VOL for any combination of inputs that can result in a logical 0 at the gate’s output.In other words, the highest value for the low output voltage of the gate must be lessthan VOL, which is given to be V−

T .

Since the output voltage of the gate is given by

VSRONpd

RONpu + RONpd,

We can write the following constraint so that the gate satisfies the static discipline forVOL = V−

T :

VT > VSRONpd

RONpu + RONpd

> VS2Rn

RONpu + 2Rn

> VS2Rn

Rn

(LW

)pu

+ 2Rn

> VS2(

LW

)pu

+ 2.

For VS = 5 V and VT = 1 V, the previous constraint simplifies to(L

W

)pu

> 8.

In other words, the L/W ratio of the pullup must be chosen to be greater than 8. Thusthe resistance of the pullup is 8Rn.

Let us now compute the power dissipated by the circuit. The maximum amount ofpower is dissipated when the resistance of the pulldown circuit is a minimum. Thishappens when A = 1, B = 1, C = 1, and D = 1. Recalling that the resistances of eachof the pulldowns is Rn and that of the pullup is 8Rn,

Pmax = V2S

8Rn + 2Rn‖Rn‖Rn

= 3 × 10−3 W.

321f

We can also design a circuit for the expression (A + B)CD in like manner as depicted inFigure 6.58. In this design, the maximum on-state resistance of the pulldown circuit foran output low is achieved when both C and D is high and only one of A and B is high.The corresponding maximum on-state resistance of the pulldown (assuming minimumsized transistors) is 3Rn.

A B

C

D

VS

Out

W

L----

pd

W

L----

puVA

F IGURE 6.58 Transistor-level

implementation of (A + B)CDusing an active pullup. In the circuit,VA > VS + VT .

As before, the pullup must be designed to have four times the resistance of the pulldown.Since the pulldown circuit has resistance 3Rn, the L/W ratio of the pullup transistor mustbe chosen as

(L/W )pu = 4 × (L/W )pd = 4 × 3 = 12.

We can also calculate the maximum power dissipated by computing the minimumresistance in the current path. The minimum resistance occurs when all inputs are high.Thus the total resistance in the current path is given by

Rpu + Rpd = 12Rn + 2Rn + (Rn‖Rn) = 14.5Rn.

The corresponding power dissipation is26

Pmax = V2s

14.5Rn= 1.7 × 10−3 W.

26. We note that a milliwatt of power per gate would cause today’s million-gate circuits on a VLSIchip to dissipate a thousand watts of power! Because VLSI chips cannot dissipate more than fewtens of watts without esoteric packaging technologies, modern VLSI chips use another form oflogic called CMOS involving both n-channel and the complementary p-channel MOSFETs. Wewill study this technology in Chapter 11.

321g

e x a m p l e 7.18 b e t t e r b j t m o d e l s Since the base-emitter junc-tion of a BJT functions like a diode, we can build more accurate models for the BJTby using more sophisticated models for the BJT’s base-to-emitter diode. Figure 7.61shows a pair of models for the BJT that provide better accuracy than the ideal-diode-voltage-source model shown in Figure 7.49c. Notice that we are ignoring the presenceof the base-to-collector diode (shown in a faint outline form in Figures 7.61b and 7.61c)by assuming that the BJTs are constrained to operate in their active region (that is, weassume vCE > vBE −0.4). In this example, we will use each of these two models to com-pute vBE, iC, and iE for the BJT in the circuit shown in Figure 7.53. Assume RD = 10 ,VTH = 0.025 V, and Is = 10−12 A.

First, let us compute the parameters based on the model in Figure 7.61b. We will startby making our calculations assuming that the BJT is operating in its active region, andthen verify that the results satisfy the conditions for active region operation. Underactive-region operation, we can obtain iC directly from the value of iB as

iC = βiB = 1 mA.

The emitter current is the sum of the base and collector currents. Thus

iE = iC + iB = 1.01 mA.

We can now determine vBE by summing the source voltage and the voltage drop acrossRD as

vBE = 0.6 + iERD = 0.6101 V.

This completes our calculations based on the model in Figure 7.61b. To verify that theBJT is operating in its active region, we need to check that the following two conditionsare met: iB > 0 and vCE > vBE − 0.4 V. Substituting iB = 0.01 mA, vCE = 5 V, andvBE = 0.6101 V, we can see that both conditions are indeed met.

Next, let us compute the parameters based on the model in Figure 7.61c. As with theprevious model, we will start by making our calculations assuming that the BJT is oper-ating in its active region, and then verify that the results satisfy the conditions for activeregion operation. Under active-region operation, we can obtain iC from the value of iB as

iC = βiB = 1 mA.

The emitter current is the sum of the base and collector currents. Thus

iE = iC + iB = 1.01 mA.

381a

vCE

+

-

C

BβiB

E

B

C

E

iCiB

iEvBE

+

-

(a) (b)

vCE

+

-

iC

iB

iE

vBE

+

-

0.6 V+-

For V, iC = βiBOtherwise, iC = 0

RD

C

BβiB

E

(c)

vCE

+iC

iB

iE

vBE

+

For V, iC = βiBOtherwise, iC = 0

--

iE Is e

vBE

V TH---------

1–=

vCE vBE 0.4–> vCE vBE 0.4–>

F IGURE 7.61 More accuratemodels for a bipolar junctiontransistor. We can now determine vBE from

iE = Is

(e

vBEVTH − 1

).

Solving by trial and error, we find that iE = 1.01 mA results in vBE ≈ 0.52 V.

This completes our calculations based on the model in Figure 7.61c. The computedvalues once again confirm that the BJT is operating in its active region.

381b

9.4.1 S I N U S O I D A L I N P U T S *

Sinusoidal signals are an important class of inputs to electronic circuits. So, asa first example of specific inputs to the circuits shown in Figures 9.31 through9.34, consider the special cases of

I(t) =

0 t ≤ 0

I sin(ωt) t > 0(9.67)

V(t) =

0 t ≤ 0

V sin(ωt) t > 0.(9.68)

Note that both sources are zero for t ≤ 0, but nonzero for t > 0, so that theyeffectively turn on at t = 0. A sketch of I(t) is shown in Figure 9.35a.

To complete the analysis of the circuits, we substitute the correspond-ing source function from either Equation 9.67 or 9.68 into Equations 9.63through 9.66 and carry out the indicated integration or differentiation. Thisresults in

v(t) =

0 t ≤ 0IωC

(1 − cos(ωt)

)t > 0

(9.69)

t

I(t)

Io

-Io

πω----

2πω------

(a)

t

v(t)

πω----

2πω------

2Io

ωC--------

(b)

t

v(t)I(t)

πω----

2πω------

(c)

tπω----

2πω------

2Io2

ω2C----------

ωE (t)

(d)

F IGURE 9.35 The current I, thevoltage v, the power vI, and theenergy wE stored in the capacitor,for the circuit shown in Figure 9.31given the sinusoidal source currentfrom Equation 9.67.

482a

for the capacitor circuit shown in Figure 9.31,

i(t) =

0 t ≤ 0

ωCV cos(ωt) t > 0(9.70)

for the capacitor circuit shown in Figure 9.32,

i(t) =

0 t ≤ 0

VωL

(1 − cos(ωt)

)t > 0

(9.71)

for the inductor circuit shown in Figure 9.33, and

v(t) =

0 t ≤ 0

ωLI cos(ωt) t > 0(9.72)

for the inductor circuit shown in Figure 9.34. Note that for these equations tomake sense, the units of ωC must be conductance and the units of ωL must beresistance; they are. We will encounter these products again in future chapters.

A comparison of the circuit inputs given in Equations 9.67 and 9.68 tothe circuit responses given in Equations 9.69 through 9.72 shows that thesinusoidal components of the current and voltage in each circuit are π/2 radiansout of phase with each other. This is in keeping with the observation thatthe circuits perform integration or differentiation from current to voltage orvoltage to current. In the case of the capacitor circuits, the current leads thevoltage because the current must be present first to build up the charge towhich voltage is proportional. In the case of the inductor circuits, the voltageleads the current because the voltage must be present first to build up the fluxlinkage to which the current is proportional.

The operation of the circuits in Figures 9.31 through 9.34 demonstratesthat inductors and capacitors are capable of reversible energy storage. To seethis, let us examine the circuit shown in Figure 9.31 in detail; an examina-tion of the three remaining circuits would yield identical observations. For thiscircuit, the power delivered by the source to the capacitor is given by

v(t)I(t) =

0 t ≤ 0

I2ωC

sin(ωt)(1 − cos(ωt)

)t > 0.

(9.73)

482b

Integration of this power, or rate of energy delivery to the capacitor, yields

wE(t) =

0 t ≤ 0

I2ω2C

(34

− cos(ωt) + 14

cos(2ωt))

t > 0(9.74)

as the energy stored in the capacitor. The current I, the voltage v, the powervI into the capacitor, and the energy wE stored in the capacitor are all shownin Figure 9.35. From the figure we see that the power can be both positiveand negative indicating that energy can be delivered to and retrieved fromthe capacitor. In fact, during odd intervals of π/ω in time, energy is deliv-ered to the capacitor. It is then retrieved without loss during the following eveninterval of π/ω in time. Thus, ideal capacitors are lossless energy reservoirs.The same is true for inductors.

482c

9.4.4 RO L E R E V E R S A L *

In each example in this section, a single capacitor or inductor was driven by asource. When that element was driven by a current source its branch currentwas imposed, and its branch voltage evolved in response. Alternatively, whenthe element was driven by a voltage source, its branch voltage was imposed, andits branch current evolved in response. However, because the branch variablesof a capacitor are self-consistently related by Equations 9.9 and 9.12, their rolesas the sourced and the responding branch variable may be reversed. Similarly,because the branch variables of an inductor are related by Equations 9.28 and9.30, their roles may also be reversed. This allows us to use one circuit responseto derive its converse. Specifically, we will derive the circuit responses to impulseinputs using the role reversal argument.

As an example of role reversal consider the circuit shown in Figure 9.32with the source voltage V given by Equation 9.80. The current i that circulatesthrough its source and capacitor in response to the step in source voltage isthe current impulse given by Equation 9.86. Now suppose instead that it is thecurrent i in Equation 9.86 that is imposed by a source, as in Figure 9.31 withI ≡ i. What would be the voltage response v across the source and capacitor?The answer is that it would be V from Equation 9.80 so that v = V. This canbe verified by substituting i in Equation 9.86 for I in Equation 9.63 and carryingout the indicated integration with the help of Equation 9.82 to derive v. Thusthe current and voltage in Equations 9.86 and 9.80 are a self-consistent pair ofbranch variables for a capacitor. They can be either the source and response, orthe response and the source. In this way we are able to find the circuit responseto a current impulse from the circuit response to a voltage step.

In the same way, we can use Equations 9.90 and 9.91, which apply to thecircuit shown in Figure 9.34, to determine i in Figure 9.33 for the case in whichV is an impulse. For example, suppose that the voltage v in Equation 9.91 isimposed by the source in Figure 9.33 with V ≡ v. What would be the currentresponse i through the source and inductor? The answer is that it would beI from Equation 9.90 so that i = I. This can be verified by substituting v inEquation 9.91 for V in Equation 9.65 and carrying out the indicated integra-tion with the help of Equation 9.82 to derive i. Thus the current and voltagein Equations 9.90 and 9.91 are a self-consistent pair of branch variables for aninductor. They can be either the source and response, or the response and thesource. In this way we are able to find the circuit response to a voltage impulsefrom the circuit response to a current step.

489a

10.5.4 S O L U T I O N B Y I N T E G R A T I N G F A C T O R S *

Another approach to solution of first-order differential equations is via integrat-ing factors. To illustrate, we return to the simple RC circuit driven by a currentsource, Figure 10.2a. The corresponding differential equation, slightly rewrittenfrom Equation 10.2 is

dvC

dt+ vC

τ= 1

Ci(t). (10.103)

We now assume i(t) is some arbitrary input waveform, and that there is an initialcharge on the capacitor:

vC(t = 0−) = Vo. (10.104)

To solve Equation 10.103, we look for an integrating factor f such that theleft-hand side of the equation becomes the derivative of a product;

fdvC

dt+ fvC

τ= d

dt(fvC) (10.105)

= fdvC

dt+ vC

df

dt. (10.106)

Equating corresponding terms we find

f

τ= df

dt(10.107)

f = et/τ . (10.108)

After multiplying both sides of Equation 10.103 by this factor, we obtain

d

dt(vCet/τ ) = 1

Cet/τ i(t). (10.109)

Now integrate from zero to t, and use corresponding limits on both sides ofthe equation: ∫ vC(t)et/τ

vC(0)e0/τd(vCet/τ ) = 1

C

∫ t

0

(et′/τ)

i(t′)dt′ (10.110)

where t′ is a dummy variable of the integration. Performing the integration onthe left, and evaluating, we obtain

vC(t)et/τ − V0 = 1

C

∫ t

0

(et′/τ)

i(t′)dt′. (10.111)

544a

Hence we find an explicit closed form solution for vC(t):

vC(t) = V0e−t/τ + e−t/τ

C

∫ t

0

(et′/τ)

i(t′)dt′. (10.112)

Because the first term on the right depends only on the initial voltage on thecapacitor, this term must be the zero-input response. Similarly, the second termis the zero-state response. Thus Equation 10.112 validates our initial assumption(Section 10.5.3) that the total response is the sum of the ZIR and ZSR.

Equation 10.112 can be applied to any first-order linear system witharbitrary input waveform. Examples will be presented in the next section. Unfor-tunately, the extension to second- and higher-order systems is beyond the scopeof this text, so we will continue to rely on the homogeneous solution-particularsolution approach in dealing with such systems.

544b

e x a m p l e 10.3 s o l u t i o n b y i n t e g r a t i n g f a c t o r sWe can also solve Equation 10.114 by integrating factors. To do so, we note that theNorton equivalent source is vI/R. Then the ZSR, from Equation 10.112, is

vC = e−t/τ

C

∫ t

0

(et′/τ) S1t′

Rdt′. (10.131)

A helpful integral at this point is

∫xexdx = xex − ex.

So equating x to t′/τ , so that dx = dt′/τ we find

vC = S1τ e−t/τ[

t′

τet′/τ − et′/τ

]t

0(10.132)

= S1τ e−t/τ[

t

τet/τ − et/τ + 1

](10.133)

= S1(t − RC) + S1RCe−t/RC. (10.134)

This function is identical to that in Equation 10.124 and is plotted in Figure 10.33e.

550a

10.6.6 R C R E S P ON S E T O D E C A Y I N G E X PON EN T I A L *

To illustrate the application of Equation 10.148, suppose we now apply a shortdecaying exponential pulse to the RC circuit, as in Figure 10.47. Specifically weassume that the input driving signal is

vI = Ae−t/τ1 t > 0. (10.155)

If the ‘‘short pulse’’ concept is correct, and τ1 is much less that the circuit timeconstant RC = τ2, then the output response to this exponential pulse should

F IGURE 10.47 Response todecaying exponential pulse. t

t

vC

(a)

vC

+

-

CvI

R

vC

(c)

vI

t

Ae– t ⁄τ1

-Aτ1

RC – τ1------------------ e– t ⁄RC

--–Aτ1

RC – τ1----------------- e– t ⁄ τ1

(b)

+-

558a

be proportional to its area. The pulse area is

Area =∫ ∞

0Ae−t/τ1dt (10.156)

=[−Aτ1e−t/τ1

]∞0

(10.157)

= Aτ1. (10.158)

Hence the zero-state response of the circuit should be, from Equation 10.148,

vC Aτ1

τ2e−t/RC. (10.159)

To check this answer, we solve for the ZSR by using integrating factors. Thedifferential equation describing the circuit is

vI = RCdvC

dt+ vC. (10.160)

From Equation 10.112, assuming an exponential drive as given by Equa-tion 10.155, the ZSR is

vC = e−t/τ2

τ2

∫ t

0et′/τ2A

(e−t′/τ1

)dt′. (10.161)

The solution has two distinct forms, depending on the relative size of the twotime constants τ1 and τ2.

We first assume that the drive pulse does not have the same time constantas the circuit. Then, from Equation 10.161,

vC =Ae−t/τ2

τ2

1

1τ2

− 1τ1

e

t′τ2

− t′τ1

1

0

(10.162)

= A

1 − τ2/τ1

[e−t/τ1 − e−t/τ2

]. (10.163)

The first term of Equation 10.163 is the forced response to the exponentialinput, with a time dependence the same as the input, but scaled in magnitudeby a factor related to the circuit time constant. The second term is the naturalresponse, (the homogeneous solution) with a time dependence characteristic ofthe circuit rather than the drive.

This solution is completely general (except τ1 = RC). To match the ‘‘shortpulse’’ solution, we must assume that τ1 is much smaller than τ2 = RC. For this

558b

case, the two terms are shown in Figure 10.47b, and the complete responseis shown in 10.47c. If we make the pulse drive very short, then τ1 becomesnegligible compared to τ2, the first transient becomes shorter and shorter, andexcept very near t = 0 the capacitor voltage becomes

vC Aτ1

RCe−t/RC (10.164)

as we found from the area calculation.The results of this discussion can be generalized to state that whenever the

characteristic time of the input pulse is much shorter than the time constantsof a linear circuit, the capacitor voltages and inductor currents in the circuitrespond to the area of the input pulse, and are almost independent of the shapeof the pulse.

In solving Equation 10.161, we set aside a special case which is of someinterest in a broader context. The question is, does the circuit behave in somebizarre fashion if the drive pulse has the same time constant as the circuit? Onemight be led to think so from Equation 10.163, because for τ1 = RC, thedenominator goes to zero. To find the correct answer, assume τ2 = τ1 = τ inEquation 10.161 and solve:

vC = e−t/τ

τ

∫ t

0Adt′ (10.165)

= Ate−t/τ

τ. (10.166)

This waveform looks much like that shown in Figure 10.47c.

558c

e x a m p l e 12.5 g r a p h i c a l i n t e r p r e t a t i o n This examplestudies an interesting graphical interpretation of ωo = 1/

√LC and the characteristic

impedance√

L/C.

Figure 12.13 shows contours of constant ω ≡ 1/√

LC and constant√

L/C in the L Cplane over practical ranges for L and C. These contours are straight lines in the figureowing to the logarithmic scales of the figure. This figure is particularly useful for findingω and

√L/C for a given L and C, and vice versa, for example.

1 H

1 mH

1 mH

1 nH

1 pH1 pF 1 nF 1 mF 1 mF1 fF

10–4 Ω

10–3 Ω

0.01 Ω

0.1 Ω

1 Ω

10 Ω

100 Ω1000 Ω104 Ω105 Ω106 Ω107 Ω 102 rads

----------103 rads

----------104 rads

----------105 rads

----------106 rads

----------107 rads

--------

108 rads

--------

1010 rads

--------

1011 rads

--------

1013 rads

--------

C

L

1

LC------------ L

C----

. . .. . .

. . . . . .

F IGURE 12.13 Contours of constant ω ≡ 1/√LC and constant

√L/C in the L–C plane.

640a

12.4 UNDR I VEN , PARALLEL RLC C I RCU I T *

We will now analyze the undriven parallel RLC circuit shown in Figure 12.24,

vC C L

i L+

-

v

R

F IGURE 12.24 The parallelsecond-order RLC circuit shown inFigure 2.14a.

which is copied from Figure 2.14a. To analyze the behavior of this circuitwe can again employ the node method, and this analysis closely parallelsthat of Section 12.1. As in Figure 12.6, a ground node is already selectedin Figure 12.24, and the unknown node voltage v is already labeled. So, wemay again proceed immediately to Step 3 of the node method. Here, we writeKCL in terms of v for the node at which v is defined. This yields

Cdv(t)

dt+ 1

Rv(t) + 1

L

∫ t

−∞v(t)dt = 0. (12.81)

The first term in Equation 12.81 is the capacitor current, the second term is theresistor current, and the third term is the inductor current. Because the circuitcontains an inductor, Equation 12.81 contains a time integral. To remove thisintegral, we differentiate Equation 12.81 with respect to time, and also divideby C, to obtain

d2v(t)

dt2+ 1

RC

dv(t)

dt+ 1

LCv(t) = 0, (12.82)

which is easier to work with.To complete the node analysis, we complete Steps 4 and 5 by solving

Equation 12.82 for v. Then, we use v to determine the other branch variablesof interest, for example, iL and vC. Like Equation 12.4, Equation 12.82 isan ordinary second-order linear differential equation with constant coefficients.Since the circuit does not have a drive, its homogeneous solution is also thecomplete solution. Therefore, as with Equation 12.4, we expect its solution tobe a superposition of two terms of the form

Ae st.

The substitution of this candidate term into Equation 12.82 yields

A(

s 2 + 1

RCs + 1

LC

)e st = 0 (12.83)

from which it follows that

s 2 + 1

RCs + 1

LC= 0. (12.84)

Equation 12.84 is the characteristic equation of the circuit. To simplify Equa-tion 12.84, and to put it in a form that is more standard for the characteristic

654a

equation in second-order circuits, we write it as

s 2 + 2αs + ω2 = 0 (12.85)

where

α ≡ 1

2RC(12.86)

ω ≡√

1

LC; (12.87)

note that Equation 12.87 is the same as Equation 12.9. Equation 12.85 isa quadratic equation having two roots. Those roots are

s1 = −α +√

α2 − ω2 (12.88)

s2 = −α −√

α2 − ω2 . (12.89)

Therefore, the solution for v is a linear combination of the two functions e s1t

and e s2t, and takes the form

v(t) = A1e s1t + A2e s2t (12.90)

where A1 and A2 are as yet unknown constants that are equivalent to the twoconstants of integration encountered when integrating Equation 12.82 twice tofind v.

To complete the solution to Equation 12.82 we must again determine A1and A2 from initial conditions vC and iL specified at t = 0, To do so, note that

vC(t) = v(t). (12.91)

Further, from KCL applied to either node, that is, from Equation 12.81,

iL(t) = − 1

Rv(t) − C

dv

dt. (12.92)

Equations 12.91 and 12.92 can be solved to determine v and dv/dt in terms ofiL and vC. Doing so, and evaluating the result at t = 0, then yields

v(0) = vC(0) (12.93)

dv

dt(0) = − 1

CiL(0) − 1

RCvC(0). (12.94)

654b

Now, to find A1 and A2, we evaluate Equation 12.90 and its derivative att = 0, and set the results equal to Equations 12.93 and 12.94, respectively.This results in

v(0) = A1 + A2 = vC(0) (12.95)

dvdt

(0) = s1A1 + s2A2

= − 1C

iL(0) − 1RC

vC(0).(12.96)

Equations 12.95 and 12.96 can be jointly solved for A1 and A2 to obtain

A1 = (1 + RCs2)vC(0) + RiL(0)

RC(s2 − s1)= s1vC(0) − iL(0)/C

(s1 − s2)(12.97)

A2 = (1 + RCs1)vC(0) + RiL(0)

RC(s1 − s2)= s2vC(0) − iL(0)/C

(s2 − s1)(12.98)

where we have used the fact that both s1 and s2 satisfy Equation 12.84, and thefact that LCs1s2 = 1, to obtain the second equalities. Finally, Equations 12.97and 12.98 can now be substituted into Equation 12.90 to obtain

v(t) = s1vC(0) − iL(0)/C

(s1 − s2)e s1t + s2vC(0) − iL(0)/C

(s2 − s1)e s2t. (12.99)

Further, the substitution of Equation 12.99 into Equations 12.91 and 12.92yields

vC(t) = s1vC(0) − iL(0)/C

(s1 − s2)e s1t + s2vC(0) − iL(0)/C

(s2 − s1)e s2t (12.100)

iL(t) = −(

1 + RCs1R

)s1vC(0) − iL(0)/C

(s1 − s2)e s1t

−(

1 + RCs2R

)s2vC(0) − iL(0)/C

(s2 − s1)e s2t

= vC(0)/L − s2iL(0)

(s1 − s2)e s1t + vC(0)/L − s1iL(0)

(s2 − s1)e s2t (12.101)

as the states of the parallel circuit. To obtain the second equality inEquation 12.101 we have again used the fact that both s1 and s2 satisfy

654c

Equation 12.84, and the fact that LCs1s2 = 1. This completes the formalnode analysis of the circuit shown in Figure 12.24.

We will now close this subsection by examining the dynamic behavior ofvC and iL for the same three cases defined in Section 12.2. Those are the casesof under-damped, critically-damped, and over-damped dynamics. As we shallsee, the dynamics of the series circuit are essentially identical to those of theparallel circuit for all three cases, except for the details of the role of R. In theseries circuit, small R caused light damping while large R caused heavy damping.This role reverses for the parallel circuit because it is in the limit of large R thatFigure 12.24 reduces to Figure 12.6.

12.4.1 UND E R - D AM P E D D YN AM I C S

The case of under-damped dynamics is characterized by

α < ω

or, after substitution of Equations 12.86 and 12.87, by

2R >√

L/C.

As R becomes large, the corresponding resistor approaches an open circuit,and so the circuit shown in Figure 12.24 approaches the LC circuit shown inFigure 12.6. Therefore, we should expect the under-damped dynamics to beoscillatory in nature. As we shall see shortly, this is indeed the case.

With α < ω, the quantity inside the radicals in Equations 12.88 and 12.89is negative, and so the natural frequencies s1 and s2 are complex numbers. Tosimplify matters, let us again define ωd according to

ωd ≡√

ω2o − α2. (12.102)

With this definition, s1 and s2 from Equations 12.88 and 12.89 can bewritten as

s1 = −α + jωd (12.103)

s2 = −α − jωd. (12.104)

The real and imaginary parts of s1 and s2 are now more apparent.Since s1 and s2 are now complex, the exponentials in Equations 12.100

and 12.101 are also complex. Thus, iL and vC will exhibit both oscillatory anddecaying behavior. To see this, we substitute Equations 12.103 and 12.104 into

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Equations 12.100 and 12.101, and use the Euler relation to obtain

vC(t) = vC(0)e−αt cos(ωdt) −(

αCvC(0) + iL(0)

Cωd

)e−αt sin(ωdt)

=√

v 2C(0) +

(αCvC(0) + iL(0)

Cωd

)2

e−αt

× cos(

ωdt + tan−1(

αCvC(0) + iL(0)

CωdvC(0)

))(12.105)

iL(t) = iL(0)e−αt cos(ωdt) +(

vC(0) + αLiL(0)

Lωd

)e−αt sin(ωdt)

=√

i 2L (0) +

(vC(0) + αLiL(0)

Lωd

)2

e−αt

× sin(

ωdt + tan−1(

LωdiL(0)

vC(0) + αLiL(0)

)). (12.106)

Sketches of iL and vC are shown in Figure 12.25 for the special case of

iL(0) = 0.

As was the case for the series circuit, the states in the parallel circuit displayoscillatory and decaying behavior. It is also the case that Equations 12.105and 12.106 reduce to Equations 12.21 and 12.22, respectively, as the circuitdamping characterized by α vanishes. The difference here is that this occurs asR → ∞ because it is in this limit that Figure 12.24 reduces to Figure 12.6.

A comparison of Equations 12.105 and 12.106 with Equations 12.63 and12.64 shows that the under-damped dynamics of the parallel and series circuitsare quite similar. This is to be expected because their characteristic equations areidentical. It is for this reason that α, ω, ωd, and Q have the same interpretationsfor the two circuits. Our comments concerning stored energy also hold for bothcircuits. Therefore, we will not repeat the details here. Rather, we will identifythree important differences. The first difference, which has been mentionedalready, is the reversed role of R. A large R in the series circuit correspondsto a small R in the parallel circuit and vice versa. The second difference is theevaluation of the quality factor Q. While Equation 12.65 still holds for theparallel circuit, that is,

Q ≡ ω2α

, (12.107)

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| | | | | | | | | | | | | | | |

|

t

e-αt

0

vC vC(0)

π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd

|

t

0

i L

Io

π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd

F IGURE 12.25 Waveforms ofvC and iL in undriven, parallel RLCcircuit for the case of iL(0) = 0.

Equation 12.66 does not. Rather, for the parallel circuit shown in Figure 12.24,the substitution of Equations 12.86 and 12.87 into Equation 12.65 yields

Q = 1

R

√L

C(12.108)

or

Q = ωoL

R. (12.109)

654f

The third difference is the role of φ in Figure 12.17. For the parallel circuit,assuming iL(0) = 0 in Equations 12.105 and 12.106, vC is advanced withrespect to iL by quadrature plus the additional angle φ, where φ = tan−1(α/ωd).

12.4.2 O V E R - D AM P E D D YN AM I C S

As with the case of the series circuit, the case of over-damped dynamics ischaracterized by

α > ω

or, after substitution of Equations 12.86 and 12.87, by

2R <√

L/C.

In this case, the quantity inside the radicals in Equations 12.88 and 12.89 ispositive, and so both s1 and s2 are real. For this reason, the dynamic behaviorof iL and vC, as expressed by Equations 12.100 and 12.101, does not exhibitoscillation. Rather, it involves two real exponential functions that decay atdifferent rates, as the two equations show. The expressions for vC and iL forthe case of iL(0) = 0 with over-damping are obtained from Equations 12.100and 12.101, and are shown here:

vC(t) = s1vC(0)

(s1 − s2)e s1t + s2vC(0)

(s2 − s1)e s2t (12.110)

iL(t) = vC(0)

L(s1 − s2)e s1t + vC(0)

L(s2 − s1)e s2t. (12.111)

Since α > ω for over-damped circuits, note that s1 and s2 are both real in thesetwo equations.

As R becomes small, in particular smaller than 1/2√

L/C, it becomes asignificant short circuit across the capacitor and inductor. In this way it divertsthe oscillating current that the capacitor and inductor share for larger values of R.As a consequence, the energy exchange between the capacitor and inductor isinterrupted, and the circuit ceases to oscillate. Instead, its behavior is morelike that of an independent capacitor and an independent inductor dischargingthrough the resistor. To see this, let us determine the asymptotic values of s1and s2 as R becomes small and hence as α becomes large. They are

s1 = −α +√

α2 − ω2 = α

−1 +

√1 −

(ωα

)2 ≈ α

−ω22α2

= −R

L

(12.112)

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s2 = −α −√

α2 − ω2 = α

−1 −

√1 −

(ωα

)2 ≈ −2α = −1

RC. (12.113)

As expected the corresponding time constants approach RC and L/R, thetime constants of an independent capacitor-resistor circuit and an independentinductor-resistor circuit. Note that, for over-damped dynamics, α > ω fromwhich it follows that RC is the faster time constant and L/R is the slower timeconstant.

12.4.3 C R I T I C A L L Y - D AM P E D D YN AM I C S

The case of critically-damped dynamics is characterized by

α = ω.

In this case, it follows from Equations 12.88 and 12.89 that

s1 = s2 = −α

and that the characteristic equation, Equation 12.85, has a repeated root.Because of this, e s1t and e s2t are no longer independent functions, and so thegeneral solution for v is no longer the superposition of these two functions asgiven by Equation 12.90. Rather, it is again the superposition of the repeatedexponential function

e s1t = e s2t = e−αt and te−αt.

From this observation, and Equations 12.91 and 12.92, it follows that vC andiL will exhibit similar behavior.

Perhaps the easiest way to determine vC and iL for the case of criticaldamping is to evaluate Equations 12.105 and 12.106 under the conditions ofthat case. To do so, observe from Equation 12.102 that, for critical dampingω = α, and so ωd = 0. Therefore, we can obtain vC and iL for the caseof critical-damping by evaluating Equations 12.105 and 12.106 in the limitωd → 0. This results in

vC(t) = vC(0)e−αt − αCvC(0) + iL(0)

Cte−αt (12.114)

iL(t) = iL(0)e−αt + vC(0) + αLiL(0)

Lte−αt. (12.115)

From Equations 12.114 and 12.115 we see that vC and iL contain both thedecaying exponential function e−αt and the function te−αt, as expected.

654h

12.6 DR I VEN , PARALLEL RLC C I RCU I T *

Consider now the circuit shown in Figure 12.50. As in previous sections ofthis chapter, we will analyze the behavior of this circuit using the node methodbeginning at Step 3. In doing so, we will follow the analysis presented inSection 12.4 very closely.

We begin by completing Step 3, of the node method. To do so, we writeKCL in terms of vC for the node at which vC is defined to obtain

CdvC(t)

dt+ 1

RvC(t) + 1

L

∫ t

−∞vC(t)dt = iIN(t), (12.198)

which upon differentiation and division by C becomes

d2vC(t)

dt2+ 1

RC

dvC(t)

dt+ 1

LCvC(t) = 1

C

diIN(t)

dt. (12.199)

Unlike Equations 12.4, 12.82 and 12.40, Equation 12.199 is an inhomogeneousdifferential equation because it is driven by the external signal iIN. Unfortunately,iIN enters Equation 12.199 through a derivative, which poses an unnecessarycomplication. To eliminate this complication, we substitute the constitutive lawfor the inductor,

vC(t) = LdiL(t)

dt, (12.200)

into Equation 12.198 and divide by LC. This yields

d2iL(t)

dt2+ 1

RC

diL(t)

dt+ 1

LCiL(t) = 1

LCiIN(t), (12.201)

which is easier to work with.Equation 12.201 is an inhomogeneous differential equation, which unlike

our previous undriven examples (for example, Equation 12.4 for the undriven

F IGURE 12.50 The parallelsecond-order circuit with a resistor,capacitor, inductor, and currentsource.

iIN

iL

vC

vC

+

-C LR

678a

LC circuit) has an additional term for the input drive. Furthermore, notice theterm proportional to diL/dt. As we saw in Section 12.5, this term modifiesthe homogeneous response to include damping. Therefore we now expect theoscillations in the step and impulse responses to decay in time.

To complete the node analysis, we complete Steps 4 and 5 by solvingEquation 12.201 for iL, and using it to determine vC and any other variables ofinterest. To do so we employ our usual method of solving differential equations:

1. Find the homogeneous solution iLH(t).

2. Find the particular solution iLP(t).

3. The total solution is then the sum of the homogeneous solution and theparticular solution as follows:

iL(t) = iLH(t) + iLP(t).

Use the initial conditions to solve for the remaining constants.The homogeneous solution iLH(t) to Equation 12.201 is obtained by solving

the differential equation with the drive iIN ≡ 0. With iIN ≡ 0, the circuitshown in Figure 12.50 is identical to the parallel, undriven RLC circuit shownin Figure 12.24, and so the two circuits have the same homogeneous equation.The homogeneous equation in terms of the current is given by

d2iLH(t)

dt2+ 1

RC

diLH(t)

dt+ 1

LCiLH(t) = 0. (12.202)

Note the similarity between this homogeneous equation and Equation 12.4for the undriven, parallel RLC circuit. Following the solution (Equation 12.10) ofthe homogeneous equation for the undriven, parallel RLC circuit, we can writethe form of the homogeneous solution for our driven, parallel RLC circuit as

iLH(t) = K1e s1t + K2e s2t (12.203)

where K1 and K2 are as yet unknown constants that will be determined fromthe initial conditions after the total solution has been formed. s1 and s2, theroots of the characteristic equation,

s 2 + 2αs + ω2 = 0 (12.204)

α ≡ 1

2RC(12.205)

ω ≡√

1

LC. (12.206)

678b

The roots are given by

s1 = −α +√

α2 − ω2 (12.207)

s2 = −α −√

α2 − ω2 . (12.208)

As observed with other second-order circuits, the circuit exhibits under-damped,over-damped, or critically-damped behavior depending on the relative values ofα and ω:

α < ω ⇒ under-damped dynamics;α = ω ⇒ critically-damped dynamics;α > ω ⇒ over-damped dynamics.

For brevity, the rest of the section will assume that

α < ω

so that the circuit displays under-damped dynamics. For the under-dampedcase, since s1 and s2 are now complex, they can be written explicitly in complexform as

s1 = −α + jωd

s2 = −α − jωd (12.209)

where

ωd ≡√

ω2 − α2. (12.210)

As we did with the series RLC circuit, we shall rewrite the homogeneoussolution in Equation 12.121 into a more intuitive form using the Euler relationas follows:

iLH(t) = A1e−αt cos(ωdt) + A2e−αt sin(ωdt) (12.211)

where A1 and A2 are unknown constants we will evaluate later depending onthe initial conditions of the circuit.

Next, we need to find iLP(t). Knowing it, we can write the total solution as

iL(t) = iLP(t) + iLH(t) = iLP(t) + A1e−αt cos(ωdt) + A2e−αt sin(ωdt).

(12.212)

At this point, only iLP, and A1 and A2, remain as unknowns.We will now proceed to find the iLP, and then A1 and A2. iLP depends

on the input drive. We will find iLP for two cases of iIN, namely a step and

678c

an impulse. That is, we will proceed to find the step response and the impulseresponse of the circuit. To simplify matters, we will assume that the circuit isunder-damped, that both the step and the impulse occur at t = 0, and that thecircuit is initially at rest prior to that time. The latter assumption implies thatwe are seeking the zero-state response for which

iL(0) = 0 (12.213)

and

vC(0) = 0. (12.214)

The zero-state response is the response of the circuit for zero initial state.Equations 12.213 and 12.214 provide the initial conditions for the solutionof Equation 12.201 after the step and impulse occur, that is, for t > 0.

12.6.1 S T E P R E S P ON S E

Let iIN be the current step given by

iIN(t) = Iu(t) (12.215)

and shown in Figure 12.51. With the substitution of Equation 12.215, t

iIN

0

Io

F IGURE 12.51 A current stepinput.

Equation 12.201 becomes

d2iL(t)

dt2+ 1

RC

diL(t)

dt+ 1

LCiL(t) = 1

LCI (12.216)

for t > 0. Any function that satisfies Equation 12.216 for t > 0 is an acceptableiLP. One such function is

iLP(t) = I. (12.217)

Thus, we have the particular solution for a step input.The total solution is given by summing the homogeneous solution (Equa-tion 12.211) and the particular solution (Equation 12.217) as

iL(t) = I + A1e−αt cos(ωdt) + A2e−αt sin(ωdt), (12.218)

again for t > 0. Additionally, the substitution of Equation 12.218 intoEquation 12.200 yields

vC(t) = (ωdLA2 − αLA1)e−αt cos(ωdt) − (ωdLA1 + αLA2)e−αt sin(ωdt),

(12.219)

also for t > 0. Now only A1 and A2 remain as unknowns.

678d

In Chapter 9, we saw that the voltage across a capacitor is continuousunless the current through it contains an impulse. We also saw that the cur-rent through an inductor is continuous unless the voltage across it contains animpulse. Since iIN contains no impulses, we can therefore assume that both vCand iL are continuous across the step at t = 0. Consequently, since both statesare zero for t ≤ 0, Equations 12.218 and 12.219 must both evaluate to zero ast → 0. This observation allows us to use the initial conditions to determine A1and A2. Evaluation of both equations as t → 0, followed by the substitution ofthe initial conditions, yields

iL(0) = I + A1 = 0 (12.220)

vC(0) = ωdLA2 − αLA1 = 0. (12.221)

Equations 12.220 and 12.221 can be solved to yield

A1 = −I (12.222)

A2 = − α

ωdI. (12.223)

Finally, the substitution of Equations 12.222 and 12.223 into Equations 12.218and 12.219 yields

iL(t) = I(

1 − ωωd

e−αt cos(

ωdt − tan−1(

α

ωd

)))u(t) (12.224)

vC(t) = IωdC

e−αt sin(ωdt)u(t); (12.225)

Equations 12.210 and 12.206 have also been used to simplify the results.Note that the unit step function u has been introduced into Equations 12.224and 12.225 so that they are valid for all time. The validity of Equations12.224 and 12.225 can be demonstrated by observing that they satisfy theinitial conditions, and Equations 12.201 and 12.200, respectively, for all time.Because they do, our assumption that the states are continuous at t = 0 isjustified.

Figure 12.52 shows iL and vC as given by Equations 12.224 and 12.225.As expected, the ringing in both states now decays as t → ∞. This decay iswell characterized by the quality factor Q, as defined in Equation 12.66 anddiscussed shortly thereafter. In fact, because the circuits shown in Figures 12.24and 12.50 have the same homogeneous response, the entire discussion of α,ωd, and ω given in Section 12.4 applies here as well. In fact, the series andparallel circuits are duals. This can be observed by comparing the evolution oftheir branch variables. For example, like the capacitor voltage vC in the seriescircuit, iL undergoes nearly a two-fold overshoot during the initial transient.

678e

|

t

0

e-αt

vC

π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd

t

0

i L

Io

π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd

F IGURE 12.52 iL and vC for theparallel RLC circuit shown inFigure 12.50 for the case of a stepinput through iIN.

Another observation concerns the short-time behavior of the circuit. Wehave seen in Chapter 10 that the transient behavior of an uncharged capacitoris to act as a short circuit during the early part of a transient, while the cor-responding transient behavior of an uncharged inductor is to act as an opencircuit. This behavior is observed in Figure 12.52 since iIN is carried entirely

678f

by the capacitor (and iL is 0) at the start of the transient, and vC ramps upcorrespondingly.

A related observation concerns the long-time behavior of the circuit. Wehave also seen in Chapter 10 that the transient behavior of a capacitor is toact as an open circuit as t → ∞, while the corresponding transient behaviorof an inductor is to act as a short circuit. This behavior is also observed inFigure 12.52, since iIN is carried entirely by iL as t → ∞.

We also note the overshoot of iL above the input current step of I duringthe transient. Although the average value of iL is close to I during the transient,the peak value is closer to 2I.

Finally, note that as t → ∞, iIN is carried entirely by the inductor sinceiL → I. This is consistent with the relative long-time transient behavior of theinductor, resistor, and capacitor.

12.6.2 I M P U L S E R E S P ON S E

Let iIN be the impulse given by

iIN = Qδ(t) (12.226)

as shown in Figure 12.53. Because iIN is an impulse, it vanishes for t > 0.

t0

iIN

Qo

F IGURE 12.53 The currentimpulse iIN.

Therefore, Equation 12.201 reduces to a homogeneous equation for t > 0, andso the simplest acceptable particular solution is

iLP(t) = 0. (12.227)

The substitution of Equation 12.227 into Equation 12.212 now yields

iL(t) = A1e−αt cos(ωdt) + A2e−αt sin(ωdt) (12.228)

again for t > 0. Additionally, we can obtain vC(t) by using

vC(t) = LdiL(t)

dt

as

vC(t) = (LA2ωd − LαA1)e−αt cos(ωdt) − (LA1ωd + LαA2)e−αt sin(ωdt)

(12.229)

also for t > 0. Now only A1 and A2 remain as unknowns.From this discussion, it is apparent that the role of the impulse in iIN is to

establish the initial conditions for a subsequent homogeneous response. This,

678g

incidentally, might explain how the circuit shown in Figure 12.24 began itsoperation.

As mentioned earlier during our discussion of the step response, the tran-sient behavior of an uncharged capacitor is to act as a short circuit duringthe early part of a transient, while the corresponding transient behavior of anuncharged inductor is to act as an open circuit. Because of this the impulse iniIN passes entirely through the capacitor while iL remains zero at t = 0. Animportant consequence of this is that the charge Q delivered by iIN is deliveredentirely to the capacitor, and so vC steps to Q/C at t = 0. This establishes theinitial conditions after the impulse needed to determine A1 and A2. The evalu-ation of Equations 12.228 and 12.229 as t → 0, followed by the substitutionof these initial conditions (vC(0) = Q/C and iL(0) = 0), yields

iL(0) = A1 = 0 (12.230)

vC(0) = ωLA2 = QC

. (12.231)

Equations 12.230 and 12.231 can be rearranged to yield

A1 = 0 (12.232)

A2 = QLCωd

. (12.233)

Finally, the substitution of Equations 12.232 and 12.233 into Equations 12.228and 12.229 yields

iL(t) = Qω2o

ωde−αt sin(ωdt) (12.234)

vC(t) = QC

ωωd

e−αt cos(

ωdt + tan−1(

α

ωd

))u(t), (12.235)

where the unit step function u has been introduced into Equations 12.234 and12.235 so they are valid for all time.

Note that our solution in Equation 12.234 satisfies the initial conditionsestablished by the impulse, and that it satisfies Equation 12.201. Because it does,it justifies our interpretation of the circuit behavior at t = 0. The waveforms forvC and iL are as shown in Figure 12.54.

It is interesting to note that the impulse response of the circuit can also beobtained from the step response. The circuit shown in Figure 12.50 is a linearcircuit. Therefore, since the impulse iIN given in Equation 12.226 is a scaledderivative of the step iIN given in Equation 12.215, it follows that the impulseresponse is the same scaled derivative of the step response. (See Section 10.6.2

678h

F IGURE 12.54 Waveforms of iLand vC for the parallel RLC circuitfor a short pulse input.

|

t

0

e-αt

vC

Qo/C

π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd

t

0

e-αt

i L

π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd

for a more detailed discussion on the use of linearity to obtain responses tothe derivative or the integral of an input, once the response to the input isknown.)

To be more specific, iIN as given in Equation 12.226, can be constructedby applying (Q/I)d/dt to iIN as given in Equation 12.215. In other words,

Qδ(t) = (Q/I)d

dtIu(t).

Therefore, the same operator may be applied to Equations 12.234 and 12.235to determine iL and vC respectively, for the impulse response. Thus, we can

678i

obtain the impulse response by differentiating the step response. Thus, applyingthe operator (Q/I)d/dt to the step response, we obtain

iL(t) = QI

d

dt

(I(

1 − ωωd

e−αt cos(

ωdt − tan−1(

α

ωd

)))u(t))

= ωQe−αt sin(

ωdt − tan−1(

α

ωd

))u(t)

+ αωQωd

e−αt cos(

ωdt − tan−1(

α

ωd

))u(t)

+ Q(

1 − ωωd

e−αt cos(

ωdt − tan−1(

α

ωd

)))δ(t)

= Qω2ωd

e−αt sin(ωdt)u(t) (12.236)

vC(t) = QI

d

dt

(I

ωdCe−αt sin(ωdt)u(t)

)

= QC

e−αt cos(ωdt)u(t) − αQωdC

e−αt sin(ωdt)u(t) + QωdC

e−αt sin(ωdt)δ(t)

= QC

ωωd

e−αt cos(

ωdt + tan−1(

α

ωd

))u(t) (12.237)

as the impulse response of the circuit. Note that terms involving the impulseδ vanish in Equations 12.236 and 12.237 because δ is itself zero everywhereexcept t = 0, and the coefficients of the impulse are both zero at t = 0.

From this experience with the impulse, we can see that the impulse responseof the circuit is essentially a homogeneous response. Thus this response isidentical to that studied in Section 12.4. In fact, the role of the impulse is toestablish initial conditions for the subsequent homogeneous response. As weargued in Section 12.6, the current impulse passes entirely through the capacitordelivering its charge in the process. Therefore, vC steps to Q/C as iL remainszero. As a result, for t > 0, the impulse response described by Equations12.236 and 12.237 are identical to Equations 12.105 and 12.106, respectively,with vC(0) replaced by Q/C, and iL(0) replaced by zero. Therefore, the entirediscussion of the circuit shown in Figure 12.24 is applicable. Not surprisingly,note that vC and iL for the impulse as shown in Figure 12.54 are the same asthose in Figure 12.25 with vC(0) replaced by Q/C.

678j

12.10 STATE - SPACE ANALYS I S *

A state-variable analysis naturally results in a set of coupled first-order differ-ential equations. The results of a node analysis can also be expressed in thisway. Therefore, it is worth exploring the direct solution of coupled first-orderdifferential equations. In the case of a state-variable analysis, this approach tosolving the equations eliminates the need to perform their back substitution inorder to obtain a single high-order differential equation.

When working with a set of coupled first-order differential equations itis common to present them in the vector format referred to as a state-spaceformat, and to solve them with the corresponding mathematical mechanics.We will refer to this method of solution as a state-space analysis of the dif-ferential equations. It is beyond our scope to present a detailed treatment ofstate space analysis.10 Rather, we will summarize its mechanics through anexample.

To illustrate the mechanics of a state-space analysis, consider again thecircuit shown in Figure 12.50. In Section 12.9 we completed a state-variableanalysis of this circuit. The resulting state equations are given in Equations12.253 and 12.254. Those equations may be summarized in state-space formataccording to

d

dt

vC(t)

iL(t)

=

− 1

RC− 1

C1L

0

vC(t)

iL(t)

+

1

C

0

[iIN(t)] . (12.255)

Equation 12.255 is an example of the more general linear time-invariant state-space format

dx(t)

dt= Ax(t) + Bz(t). (12.256)

Here, x is referred to as the state vector, z is referred to as the input vector, Ais referred to as the state matrix, and B is referred to as the input matrix. In thecase of Equation 12.255,

x(t) =[

vC(t)

iL(t)

](12.257)

z(t) = iIN(t) (12.258)

10. For a detailed treatment of this analysis, see G. Strang, Linear Algebra and Its Applications,Third Edition, Chapter 5, Academic Press; or Finizio and Ladas, Ordinary Differential Equations,with Modern Applications, Second Edition, Section 3.3.

691a

A = − 1

RC− 1

C1L

0

(12.259)

B =[ 1

C

0

]. (12.260)

It is interesting to note that the results of a node analysis can also be expressed instate-space format. This is important at least because most commercial numer-ical analysis packages focus on the solution of differential equations presentedin this format. The circuit shown in Figure 12.50 was analyzed by the nodemethod in Section 12.6, and the resulting differential equation is given in Equa-tion 12.201. To put Equation 12.201, which is of order two, into state-spaceformat, we use iL and diL/dt as the two states within x, and write

d

dt

[iL(t)diL(t)

dt

]=[

0 1

− 1LC

− 1RC

][iL(t)diL(t)

dt

]+[

01

LC

][iIN(t)] . (12.261)

Thus, the results of both a state-variable analysis and a node analysis can be putinto the standard state-space format. However, note that Equations 12.255and 12.261 have different values for x, A and B. Because Equations 12.255 and12.261 describe the dynamics of the same circuit, it is also apparent that thereexists more than one state-space representation of the dynamics of a givencircuit.

Since Equations 12.255 and 12.261 describe the dynamics of the same cir-cuit, their solutions will ultimately yield the same branch variables. Therefore,for the sake of brevity, we will now consider the state-space analysis of onlyEquation 12.255; the analysis of Equation 12.261 proceeds in an identical man-ner. To be specific about the solution of Equation 12.255 we will consider itsresponse to a step input at t = 0. That is, we will assume that

iIN(t) = Iu(t) (12.262)

as shown in Figure 12.51. To simplify matters, we will also assume that thecircuit is at rest prior to the step. That is, we will assume that both vC and iL arezero for t ≤ 0. This information provides the initial conditions for the solutionof Equation 12.255 after the step occurs, that is, for t > 0. To solve Equa-tion 12.255 we now proceed essentially as we did in the earlier sections of thischapter. That is, we break the solution into two parts, namely a particular solu-tion, xP, and a homogeneous solution, xH. The particular solution will satisfyEquation 12.255 without regard for initial conditions, and the homogeneoussolution will match the initial conditions.

691b

Consider first the homogeneous solution. In general, the homogeneoussolution is the solution to Equation 12.256 with z ≡ 0. Therefore, xH satisfies

dxH(t)

dt= AxH(t). (12.263)

Since Equation 12.263 represents a set of ordinary first-order homogeneouslinear differential equations with constant coefficients, we expect its solution tobe a superposition of terms of the form re st where r is a constant vector havingthe same dimension as x. The substitution of this candidate term into Equation12.263 yields

(sI − A)re st = 0 (12.264)

where I is the identity matrix of appropriate dimension. Since e st is never zerofor finite st, it follows that

(sI − A)r = 0. (12.265)

Further, since r = 0 is a trivial solution that leads to x = 0, we are interestedonly in solutions to Equation 12.265 for which r = 0. For Equation 12.265 tobe satisfied for a nonzero r, the matrix (sI − A) must be singular, hence

det(sI − A) = 0. (12.266)

Equation 12.266 is a polynomial in s, referred to as the characteristic equationof A, and its roots are the eigenvalues of A. For each root, there is a corre-sponding r that is the corresponding right eigenvector of A.11 To determineeach eigenvector, the corresponding root of Equation 12.266 is substitutedinto Equation 12.265, and the resulting equation is solved for r to within anarbitrary scale factor.

With the substitution of Equation 12.259, Equation 12.266 becomes

det(sI − A) = det

s + 1

RC1C

− 1L

s

= s 2 + 1

RCs + 1

LC= 0, (12.267)

which is the same as Equation 12.84. Thus, we see that the characteristicequation of A is the same as the characteristic equation of the circuit, and that

11. Here, we ignore the degenerate case in which repeated eigenvalues share a single eigenvector.

691c

the eigenvalues of A are the natural frequencies of the circuit. Equation 12.267has two roots and they are given by

s1 = −α +√

α2 − ω2 (12.268)

s2 = −α −√

α2 − ω2 (12.269)

α ≡ 1

2RC(12.270)

ω ≡ 1√LC

(12.271)

just as given in Equations 12.125 and 12.126. This is expected because thehomogeneous version of the circuit shown in Figure 12.50 is the circuit shownin Figure 12.24. Finally, the corresponding eigenvectors, determined fromEquation 12.265 for each eigenvalue, are

r1 =[

11

s1L

](12.272)

r2 =[

11

s2L

]. (12.273)

With these results we can now assemble the homogeneous solution of Equation12.255. It is given by

xH(t) = A1r1e s1t + A2r2e s2t = A1

[11

s1L

]e s1t + A2

[11

s2L

]e s2t (12.274)

where A1 and A2 are two coefficients that depend on initial conditions.Consider now the particular solution. In general, it is the solution to Equa-

tion 12.256 without regard for the initial conditions. Thus, any function xP thatsatisfies

dxP(t)

dt= AxP(t) + Bz(t) (12.275)

is an acceptable particular solution. To treat the general case of the step input,we let

z(t) = Zu(t). (12.276)

The substitution of Equation 12.276 into Equation 12.275 yields

dxP(t)

dt= AxP(t) + BZ (12.277)

691d

for t > 0. Assuming that A−1 exists, one solution to Equation 12.277 is

xP(t) = −A−1BZ, (12.278)

again for t > 0. With the substitution of Equations 12.262 and 12.276,Equation 12.258 becomes

Z = I. (12.279)

Then, with the substitution of Equations 12.259, 12.260, and 12.279, Equa-tion Equation 12.278 becomes

xP(t) = − − 1

RC− 1

C1L

0

−1 1

C

0

I

= −[

0 L

−C −LR

][1C0

]I =

[0

I

], (12.280)

also for t > 0.We can now combine the particular and homogeneous solutions with the

initial conditions to solve Equation 12.255. To begin, the superposition ofEquations 12.274 and 12.280 yields

[vC(t)

iL(t)

]= x(t) = xP(t) + xH(t)

=[

0

I

]+ A1

[11

s1L

]e s1t + A2

[11

s2L

]e s2t. (12.281)

Now, A1 and A2 are the only unknowns. To find A1 and A2, we use the initialconditions. Since iIN contains no impulses, we can assume that both vC and iLare continuous at t = 0. Consequently, since both states are zero for t ≤ 0,Equation 12.281 must evaluate to zero as t → 0. This yields

[vC(0)

iL(0)

]=[

0

I

]+ A1

[11

s1L

]+ A2

[11

s2L

]=[

0

0

]. (12.282)

The two rows of Equation 12.282 are two equations that can be solved forA1 and A2. Doing so yields

A1 = s1s2LIs1 − s2

= IC(s1 − s2)

(12.283)

691e

A2 = s1s2LIs2 − s1

= IC(s2 − s1)

; (12.284)

note that the second equalities in Equations 12.283 and 12.284 follow fromthe substitution of Equations 12.268 and 12.269. Finally, the substitution ofEquations 12.283 and 12.284 into Equation 12.281 yields

[vC(t)

iL(t)

]=[

0

I

]u(t) + I

C(s1 − s2)

[11

s1L

]e s1tu(t) + I

C(s2 − s1)

[11

s2L

]e s2tu(t)

(12.285)as the solution of Equation 12.255. Note that the unit step function u has beenintroduced into Equation 12.285 to extend the range of its validity. With alittle effort it can be shown that the two rows of Equation 12.285 are identicalto Equations 12.224 and 12.225. This is to be expected since both sets ofequations are the results of analyses of the same circuit.

12.10.1 NUME R I C A L S O L U T I O N *

The state equation (specifically, Equations 12.255 and in a more general form,Equation 12.256) can also be solved using numeric methods. Our goal here is todemonstrate that the initial state contains all the information that is necessaryto determine the entire future behavior of the system given the subsequentinput. To help our intuition, we will describe an extremely simple method here.However, we note that other more efficient, but less intuitive, methods areemployed in practice.

Suppose that the input signal vector z(t) is known for all time t ≥ t0. Alsosuppose that the initial value of the state vector at time t = t0 (denoted as x(t0)and called the initial state) is also known. Then the slope of the state vector(that is, dx/dt) at time t0 can also be found from Equation 12.256 as follows:

dx

dt(t0) = Ax(t0) + Bz(t0). (12.286)

From this slope and the initial state x(t0), the value of the state vector at timet0 + t can now be estimated by standard numerical methods. Using Euler’smethod, for example, we can approximate the value of the state vector at time

t = t0 + t

as

x(t0 + t) = x(t0) + dx

dt(t0)t

= x(t0) + Ax(t0)t + Bz(t0)t. (12.287)

691f

Proceeding in the same manner, the value of x at time

t = t0 + 2t

can then be determined from the value of x(t0 +t) and z(t0 +t). Subsequentvalues of x(t) can be determined using the same process. By choosing smallenough values of t, a computer can determine the waveform for the x(t)vector to an arbitrary degree of accuracy. This process illustrates the fact thatthe initial state contains all the information that is necessary to determine theentire future behavior of the system from the initial state and the subsequentinput.

Notice the similarity between the numerical solution process for thesecond-order system (Equations 12.256 and 12.287) and the first-order sys-tem (Equations 10.82 and 10.83). The major difference is that we are dealingwith vectors and vector-matrix operations in the second-order system, whilethe first-order system dealt with scalar operations. Higher-order systems withmany capacitors and inductors will result in a larger set of first-order state equa-tions, which can be gathered into a single-vector state equation that is identicalin form to Equation 12.256.

691g

12.11 H IGHER -ORDER C I RCU I T S *

To close this chapter, we briefly consider the analysis of circuits having an orderhigher than two. The important message here is that the methods of analysisdeveloped earlier in this chapter for second-order circuits are perfectly applica-ble to the analysis of higher-order circuits. We will illustrate this through theanalysis of the circuit shown in Figure 12.63. Since the circuit has two inde-pendent capacitors and two independent inductors, it is a fourth-order circuit.Despite this, it readily submits to both a node analysis with the node voltagesas the primary unknowns, and a state-variable analysis with the states as theprimary unknowns.

Consider first the node analysis of the circuit shown in Figure 12.63, carriedout using v1 and v2 and as the two unknown node voltages. To begin, we writeKCL at Nodes #1 and #2 in terms of these voltages. This yields

C1dv1(t)

dt+ 1

R(v1(t) − v2(t)) + 1

L1

∫ t

−∞(v1(t) − vIN(t))dt = 0 (12.288)

for Node #1, and

C2

(dv2(t)

dt− dvIN(t)

dt

)+ 1

R(v2(t)−v1(t))+ 1

L2

∫ t

−∞v2(t)dt− iIN = 0 (12.289)

for Node #2. To treat these equations simultaneously, we use Equa-tion 12.288 to determine v2 in terms of v1, and then substitute the result

R

+

-

L1

C1 L2

C2

iIN

vIN v1 v2

iL1

iL2+

+

-

-

vC1

vC2

vIN

Node 1 Node 2

F IGURE 12.63 A fourth-ordercircuit.

691h

into Equation 12.289. This yields

v2(t) = RC1dv1(t)

dt+ v1(t) + R

L1

∫ t

−∞(v1(t) − vIN(t)(t))dt (12.290)

d4v1(t)

dt4+(

1

RC1+ 1

RC2

)d3v1(t)

dt3+(

1

L1C1+ 1

L2C2

)d2v1(t)

dt2

+(

1

RC1L2C2+ 1

RC2L1C1

)dv1(t)

dt+(

1

L1C1L2C2

)v1(t) =

(1

RC1

)d3vIN(t)

dt3+(

1

L1C1

)d2vIN(t)

dt2+(

1

RC2L1C1

)dvIN(t)

dt+

(1

L1C1L2C2

)vIN(t) +

(1

RC1C2

)d2iIN(t)

dt.

(12.291)

Note that in deriving Equation 12.291 we differentiated Equation 12.289 twiceand divided it by RC1C2 prior to the substitution of Equation 12.290. Finally,to complete the node analysis, we solve Equation 12.291 for v1, substitute theresult into Equation 12.290 to determine v2, and then use the two node voltagesto determine any other branch variables of interest. For brevity, however, wewill not carry out these remaining steps. Instead, we note that to do so requiresinitial conditions for v1, and its first, second, and third derivatives. Most likely,this information will be determined from the state variables specified at theinitial time, which takes additional work.

Consider next a state-variable analysis of the circuit shown in Figure 12.63.To carry out this analysis we determine the state equation for each capacitorand inductor. This yields,

C1dvC1(t)

dt= iC1(t) = 1

R(vIN(t) − vC1(t) − vC2(t)) + iL1(t) (12.292)

C2dvC2(t)

dt= iC2(t) = 1

R(vIN(t) − vC1(t) − vC2(t)) + iL2(t) − iIN(t) (12.293)

L1diL1(t)

dt= vL1(t) = vIN(t) − vC1(t) (12.294)

L2diL2(t)

dt= vL2(t) = vIN(t) − vC2(t). (12.295)

691i

These equations may be summarized in state-space form as

d

dt

vC1(t)

vC2(t)

iL1(t)

iL2(t)

=

− 1RC1

− 1RC1

1C1

0

− 1RC2

− 1RC2

0 1C2

− 1L1

0 0 0

0 − 1L2

0 0

vC1(t)

vC2(t)

iL1(t)

iL2(t)

+

1RC1

0

1RC2

1C2

1L1

0

1L2

0

[

vIN(t)

iIN(t)

]. (12.296)

Finally, to complete the state-variable analysis, we solve Equation 12.296 for thestates, and then use them to determine any other branch variables of interest.For brevity, however, we will not carry out these remaining steps. Instead, wenote that to do so requires an initial condition for each state.

To close this section, it is again worth mentioning that both analyses predictthe same behavior for the circuit shown in Figure 12.63. The only differenceis that they do so in terms of different sets of variables, and through differ-ent mathematical mechanics. Thus, the important message here is that bothanalyses are applicable to higher-order systems.

691j

13.4.3 T H E BOD E P L O T : S K E T CH I N G T H EF R E QU ENC Y R E S P ON S E O F G EN E R A LF UNC T I O N S *

Sections 13.4.1 and 13.4.2 demonstrated the ease with which we can sketchthe frequency response of simple circuits by observing their behavior at lowfrequencies and high frequencies. Things get more complicated for a networkwith several inductors or capacitors. This section discusses a simple and intu-itive method called Bode plots for sketching the frequency response of moregeneral circuits. The Bode method uses the insight gained from Sections 13.4.1and 13.4.2 that the frequency response plots can be closely approximated bystraight line segments derived from the asymptotic behavior of the transferfunctions.

The method proceeds as follows: First, write the relationship (Equa-tion 13.46, for example) in the form of a system function, the ratio of thecomplex amplitude of the response to the complex amplitude of the input:

H(s) = Response

Input. (13.91)

In general, the system function H(s) will be the ratio of two polynomials:

H(s) = amsm + am−1sm−1 + · · · + a1s + a0

bnsn + bn−1sn−1 + · · · + b1s + b0(13.92)

where the coefficients ai and bi are real numbers since our circuit parametersare real numbers. We saw one example of this in Equation 13.64. We canfactor the numerator and denominator polynomials and write

H(s) = K1(s − z1)(s − z2) · · · (s − zm)

(s − p1)(s − p2) · · · (s − pn)(13.93)

where K1 is a constant and z1, z2, . . . , zm are the roots of the numer-ator polynomial, and p1, p2, . . . , pn are the roots of the denominatorpolynomial.9

9. Because the system function goes to zero when s = zi, the roots of the numerator, z1, z2, . . . , zm,are called the zeros, definition of the system function. Similarly, the roots of the denominator,p1, p2, . . . , pn are called the poles of the system function. The system function goes to infinity whens takes on the value of one of the poles (in other words, when s = pi). When one or more of thez′is or p′

is is zero, the system is said to have zeros or poles at the origin. The poles and zeros of asystem function are important system parameters because they characterize the general behavior

741a

In general, some of the roots of the numerator or the denominator polyno-mials can be zero. Furthermore, the roots of the numerator and denominatorpolynomials can also be complex. If any of the roots are complex, then theymust appear in complex conjugate pairs, so that the overall system functionremains real. We will rewrite Equation 13.93 into the following standard formto reflect these facts:

H(s) = Kosl(s + a1)(s + a2) · · · (s2 + 2α1s + ω21

) · · ·(s + a3)(s + a4) · · · (s2 + 2α2s + ω2

2

) · · · . (13.94)

In Equation 13.94, we have combined complex conjugate pairs into quadraticterms of the form (s2 +2αs+ω2). Thus all the remaining ai values are real. Thesl term, where l can be positive or negative, reflects the case where the roots inEquation 13.93 are zero.

We will now show that it is possible to sketch without formal calculationthe general shape of H(s) as a function of frequency. More precisely, we canmake an approximate sketch of the magnitude and phase of H(s) as a func-tion of the input frequency ω. The resulting pair of graphics representing anapproximate sketch of the frequency response is called a Bode plot, in honorof the Bell Laboratories engineer who devised it to study stability in feedbackamplifiers.10

The Bode plot is an approximation of the frequency response and accord-ingly has two parts: a sketch of the log magnitude of H( jω) versus logω and asketch of the angle of H( jω) versus logω. These coordinates are chosen becausethey facilitate straightforward construction of the frequency response graphseven for complicated functions without the use of a computer. Taking themagnitude and log on both sides of Equation 13.94,

log|H(s)| = log Ko+log |s| + log |s| + · · · (l terms)+log |s + a1| + log |s + a2| + · · · − log |s + a3| − log |s + a4| + · · ·log |s2 + 2α1s + ω2

1| + · · · − log |s2 + 2α2s + ω22| + · · · (13.95)

of the system. A detailed discussion of system analysis using poles and zeros is beyond the scopeof this book.

10. Bode, H.W., Network Analysis and Feedback Amplifier Designs, Van Nostrand, New York,1945, Chapter 15.

741b

and for the phase

∠H(s) = ∠Ko+∠s + ∠s + · · · (l terms)+∠(s + a1) + ∠(s + a2) + · · · − ∠(s + a3) − ∠(s + a4) − · · ·+ ∠(s2 + 2α1s + ω2

1) + · · · − ∠(s2 + 2α2s + ω22) − · · · (13.96)

Notice that there are four types of terms in the magnitude and phase equations:

1. The Ko constant term,

2. the s terms,

3. terms of the form (s + a), and

4. quadratic terms of the form (s2 + 2αs + ω2), which have complex roots.

This gives us a simple way of approximating the magnitude and phase curvesof the frequency response plot. First, draw the individual magnitude and anglecurves for each of the four types of terms in the numerator and denominatorof Equation 13.94. Then, construct the overall magnitude and phase plots bysimply adding together the individual curves.

Let us now address each of the four terms:

1. The Ko constant term.We saw how to draw the frequency response of constant terms inSection 13.4.1. Essentially constant terms result in horizontal lines on themagnitude plot and have a phase of zero.

2. The s terms.Terms of the form s and 1/s (if l is negative) were also plotted inSection 13.4.1. We saw that each of these terms result in lines of +1 or−1 slope on the log magnitude plot and contribute to a phase of 90 or−90, respectively.

3. Terms of the form (s + a).Section 13.4.2 addressed terms of the form (s + a). We showed that themagnitude part of the frequency response of these terms is approximatedby two straight lines corresponding to the low and high frequencyasymptotes meeting at the break frequency a. Accordingly, Bode plotsresult in a series of straight line segments attached together at the breakfrequencies.

The phase plot also uses low- and high-frequency asymptotes and passesthrough 45 at the break frequency a. For more accuracy, the phase curvecan be approximated by a straight line that passes through 45 at the

741c

break frequency a, and meets the low- and high-frequency asymptotes at0.1 times the break frequency (0.1a) and 10 times the break frequency(10a), respectively.

4. Quadratic terms of the form (s2 + 2αs + ω2) with complex roots.Although not as straightforward, it is possible to sketch frequencyresponse plots for system functions of the form (s2 + 2αs + ω2), wherethe roots are complex. However, we will defer a further discussion onplotting Bode plots for complex roots to Section 14.4. For now, we willfocus on real roots.

741d

e x a m p l e 13 .5 b o d e p l o t f o r s e r i e s r l c i r c u i t Letus sketch the Bode plot for the RL circuit of Figure 13.11. From Equation 13.47, thesystem function here is a voltage ratio:

H( jω) = Vo

Vi= R/L

jω + R/L. (13.97)

To make the example specific, let us assume that the time constant L/R has a value of50 msec. Thus the break frequency is at

a = R

L= 20 rad/s

and the system function becomes

H( jω) = 20

jω + 20. (13.98)

The system function has two terms: a constant term and a term of the form (s + a).Figures 13.26 and 13.27 show the construction of the magnitude and phase plots,respectively. The dashed lines in Figures 13.26c and 13.27c form the composite Bodeplot, and are obtained by simple subtraction of Figures 13.26b from Figure 13.27a. Forreference, the solid lines show the true magnitude and phase functions. Note that at thebreak frequency, the true magnitude is given by:

|H( jω)| = 1/1.41 (13.99)

= 0.707.

The principal advantage of the Bode plot is that the composite magnitude asymptotesfor system functions that can be written in the form of Equation 13.94 are alwayslines of integer slope in log space. Further, any system function that can be written asa ratio of polynomials in ω (regardless of whether the roots are real or complex) mustapproach at both low and high frequencies ( jω)n, where n is some integer. Hence themagnitude asymptotes on Bode plots for both small and large ω must be straight linesof integer slope in log space, and the phase must approach a multiple of 90.

742a

0.01

0.10

1.00

10.00

100.00

(a)

-1

0

1

1000.00

|R/L

| log

sca

le

log

|R/L

2

3

10-1 100 101 102 103

ω

0.01

1000.00

(b)

3

10-1 100 101 102 103

ω

0.10

1.00

10.00

100.00

-1

0

1

2

|jω

+ R

/L| l

og s

cale

log

|jω +

R/

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||0.01

|

(c)

|||

|||||0.10

||

||||

|||1.00

||

||||

|||10.00

||

||||

|||100.00

||

||||

|||1000.00

|H| l

og s

cale

log

|H|

-1

0

1

2

3

10-1 100 101 102 103

ω

F IGURE 13.26 Magnitude curveof the Bode plot for RL circuit:(a) the magnitude curve for R/L;(b) the magnitude curve forjω + R/L; (c) the compositemagnitude curve obtained bysubtracting (b) from (a).

742b

F IGURE 13.27 Phase curve ofthe Bode plot for RL circuit: (a) thephase curve curve for R/L; (b) thephase curve for jω + R/L; (c) thecomposite phase curve obtained bysubtracting (b) from (a).

-90-70-50-30-101030507090

<R

/L

(a)

10-1 100 101 102 103

ω

-90-70-50-30-101030507090

(b)

10-1 100 101 102 103

ω

<R

/L +

jω

vv

-90

-70

-50

-30

-10

10

30

50

70

90

<H

(c)

10-1 100 101 102 103

ω

742c

e x a m p l e 13 .6 a n o t h e r b o d e p l o t e x a m p l e Toillustrate the Bode method for more general transfer functions, let us sketch the Bodeplot for the following transfer function:

H( jω) = 0.025(1000 + jω)

100 + jω. (13.100)

The specific circuit that results in this transfer function is not relevant to us right now,but will be discussed later in Section 13.6.

The system function has three terms: a constant term, and two terms of the form (s+a).The Bode construction of the magnitude curve of the frequency response for the abovetransfer function is shown in Figure 13.28. The corresponding phase construction isshown in Figure 13.29. For reference, the actual frequency response generated using acomputer is shown using solid curves.

742d

F IGURE 13.28 Construction ofthe magnitude curve of the Bodeplot. The composite magnitudecurve for the transfer function isobtained by subtracting themagnitude curve of (1000 + jω)from the sum of the magnitudecurves of 0.025 and (100 + jω).

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |||

||||

||||

|||

|||||

||

||||

||||

|||

|||||

||

||||

||||

|||

|||||

|

|0.0

25|

4

3

2

1

0

-1

-2

100 101 102 103 10410-2

10-1

100

101

102

103

104

ω

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |||

||||

||||

|||

|||||

||

||||

||||

|||

|||||

||

||||

||||

|||

|||||

| 4

3

2

1

0

-1

-2

100 101

102 103 10410-2

10-1

100

101

102

103

104

ω

| 10

00 +

jω |

4

3

2

1

0

-1

-2

100 101 102 103 10410-2

10-1

100

101

102

103

104

ω

| 10

0 +

jω |

|H| 4

3

2

1

0

-1

-2

100 101 102 103 10410-2

10-1

100

101

102

103

104

ω

742e

-90

-60

-30

0

30

60

90

<0.

025

100 101 102 103 104

ω

|-90

-60

-30

0

30

60

90

100 101 102 103 104

ω

<10

00 +

jω

-90

-60

-30

0

30

60

90

100 101 102 103 104

ω

<10

0 +

jω

-90

-60

-30

0

30

60

90

<H

100 101 102 103 104

ω

F IGURE 13.29 Construction ofthe phase curve of the Bode plot.

742f

e x a m p l e 13 .7 m a x i m i z i n g p o w e r t r a n s f e r u s i n ga t r a n s f o r m e r One use of the transformer discussed in Section 9.3.4 is tomatch impedances between two halves of a circuit, and in doing so to maximize thepower transfered from a source to a load. For example, consider connecting a sourcehaving a 1-V-peak and 50- Thévenin equivalent operating in the sinusoidal steady stateto a 1800- load as shown in Figure 13.56.

In the case of this direct connection, the voltage across the load is

1800

18501 V sin(ωt),

and so the time average power delivered to the load is approximately 0.26 mW; notethat the time average of sin2(ωt) is 0.5.

Next, consider the circuit shown in Figure 13.57. In this circuit, an ideal transformerhaving N1 primary turns and N2 secondary turns is inserted between the source andload; with help from Figure 9.30, an equivalent model of this circuit is shown inFigure 13.58.

F IGURE 13.56 A sourceconnected directly to a load.

+

-

Source Load

50 Ω

RL = 1800 Ω1 Vsin (ωt)

F IGURE 13.57 A sourceconnected to a load through atransformer.

+

- N2N11 V sin (ωt) 1800 Ω

50 Ω

764a

+

-

+

-

v1

+

-

v2

i2i1

N2

N1-----

-

+N2

N1------ i2

1800 Ω1 V sin (ωt)

50 Ω

v1

F IGURE 13.58 An equivalentcircuit model of the circuit inFigure 13.57.

To analyze this new circuit, consider first the secondary side of the transformer. There,

i2 = −N2

N1

v1

RL, (13.175)

and so at the primary side of the transformer,

i1 = −N2

N1i2 = N2

2

N21

v1

RL. (13.176)

Thus, as viewed from the primary side of the transformer, the transformer and resistortogether behave as a resistor having resistance

(N1/N2)2RL.

In other words, the transformer has transformed the resistance of the load resistor bythe ratio of (N1/N2)2. It is straightforward to show that any secondary-side impedanceis transformed to the primary side by the same ratio. Similarly, a primary-sideimpedance is transformed to the secondary side by a ratio of (N2/N1)2.

Let us now determine the ratio N2/N1 that maximizes the power delivered to the load.To do so, we use the circuit in Figure 13.59, in which the transformer and load resistor

+

-

N1

N2------

2

1800 Ω

+

-

v1

i1

1 V sin (ωt)

50 Ω

F IGURE 13.59 An equivalentcircuit model with the transformerand load resistor replaced by theeffective load resistor.

764b

are replaced by the effective load resistor having resistance (N1/N2)2 1800 . In thiscase, the voltage across the effective load resistor is

1800N21/N2

2

50 + 1800N21/N2

2

1 V sin(ωt),

and the average power delivered to the effective load resistor is

0.51800N2

1/N22

(50 + 1800N21/N2

2)2W.

Since the power into the primary side of an ideal transformer instantaneously exits thesecondary side of the transformer, this is the power delivered to the actual load. Thispower is maximized for

50 = 1800N21/N2

2,

or N2/N1 = 6, in which case the resistance of the effective load resistor is 50 , andthe power delivered to the load resistor is 2.5 mW.

Thus, to achieve maximum power transfer, the resistance of the load must match thatof the source, and the ideal transformer performs this matching.

764c

e x a m p l e 13 .8 n o n - i d e a l t r a n s f o r m e r s Real transform-ers are never ideal, and at times their nonidealities are important. Such nonidealitiesinclude the resistance of the coils, the leakage inductance of the coils and the magne-tizing inductance of the core. These non-idealities can be added to the model shownin Figure 9.29 to arrive at the model shown in Figure 13.60; note that the transformersymbol in Figure 13.60 represents the original ideal transformer from Figure 9.29.

In Figure 13.60, R1 and R2 represent the resistances of the two coils, and LL1 and LL2

represent the leakage inductances of the two coils. The inductance L0 represents themagnetizing inductance of the core given a single-turn coil, and so must be multipliedby N2

1 if placed on the primary side of the ideal transformer, or by N22 if placed on the

secondary side of the ideal transformer. In either case, it represents the effect of thenon-infinite permeability of the core.

Let us now examine the effect of the magnetizing inductance on the results ofExample 13.7. Consider the case of N1 = 100, N2 = 600, and L0 = 8 µH, asmight be the case for a small-signal transformer. This case is shown in Figure 13.61.

Following the results of Example 13.7, we can replace the combination of the idealtransformer and the 1800- load resistor with a 50- resistor, and compute themagnitude of v1 to be

|v1| =∣∣∣∣ ( jω 80 mH)‖(50 )

50 + ( jω 80 mH)‖(50 )

∣∣∣∣ 1V =∣∣∣∣∣ ω√

4ω2 + (625 rad/s)2

∣∣∣∣∣ 1V.

LL2

N2N1

Ideal Transformer

R2LL1R1

N12L0

F IGURE 13.60 A non-idealtransformer.

N2N12L0

+

-

v1

+

-

v2= 600

N1= 100= 80 mH

+-1 V sin (ωt) 1800 Ω

50 Ω

F IGURE 13.61 Power transferwith a non-ideal transformer.

764d

Thus, for ω 312.5 rad/s, that is, for source frequencies well above 50 Hz, the voltagemagnitude across the transformer primary is approximately 0.5 V peak. In this case,the maximum power is transfered to the resistor load. However, as the frequency goesbelow 50 Hz, the inductor behaves like a relative short circuit in comparison to the50- resistance of the transformed load resistor, and so the magnitude of v1 drops.The magnitude of v2 and the power delivered to the load drops accordingly. In general,the time-average power delivered to the load resistor is that which flows into the primaryof the ideal transformer, namely:

ω2

4ω2 + (625 rad/s)210 mW.

764e

14.4 THE BODE PLOT FOR RESONANTFUNCT IONS *

In this section, we will extend the Bode method for plotting approximate fre-quency responses (Section 13.4.3) to resonant system functions. Recall thata Bode plot is an approximate sketch of the frequency response, which can bedrawn by intuition without the use of a computer. Section 13.4.3 discusseda simple and intuitive method for sketching the Bode plots for general circuits.The method is based on the intuition that a general system function can bewritten in the form shown in Equation 13.94, which contains four types ofterms:

1. A constant term,

2. s terms,

3. real terms of the form (s + a), and

4. quadratic terms of the form (s2 + 2αs + ω2o) with complex roots.

The Bode method proceeded by drawing the individual magnitude and anglecurves for each of the four types of terms in the numerator and denominatorof Equation 13.94. The magnitude curves are drawn on log-log scales and thephase curves on log-linear scales. Observing that log-magnitudes and phasesadd (Equations 13.95 and 13.96), the method concluded by constructing theoverall magnitude and phase plots by simply adding together the individualcurves.

Section 13.4.3 discussed how the real terms (types 1, 2, and 3) could beplotted. This section discusses how we can plot type 4 terms, namely, quadraticterms with complex roots. Once we know how to sketch the plots for eachof the four types of terms, we can then sketch any general system function bysuperposition (see Section 13.4.3).

The Bode plot for a quadratic term with complex roots is easily drawn fromthe insight gained in Section 14.2. There we showed that the low- and high-frequency magnitude and phase asymptotes of second-order system functionsyielded insight into the general form of response. It turns out that for a quadraticterm of the form (s2 + 2αs + ω2

o), the low- and high-frequency asymptotes canbe combined to yield a good approximation of the actual curve.

Accordingly, the following is a procedure for sketching the form of thefrequency response for a quadratic term of the form s2 + 2αs + ω2

o , which hascomplex roots:

Magnitude Plot

1. Sketch the low-frequency asymptote. For our quadratic term, thelow-frequency asymptote is given by the horizontal line:

|H( jω)| ≈ ω2o .

808a

(a) (b)

Frequency (rad/s)

|H

|

102 103 104 105 610106

107

108

109

1010

-100

102030405060708090

100110120130140150160170180

Frequency (rad/s)

<H

(de

gree

s)

O

102 103 104 105 610

F IGURE 14.28 Sketching thefrequency response of theresonant function s2 + 2αs + ω2

o .

2. Sketch the high-frequency asymptote. The high-frequency asymptoteis given by:

|H( jω)| ≈ ω2.

This asymptote appears as a line of slope 2 in log-log scales.Figure 14.28a shows these two asymptotes in dashed lines, assuming

ωo = 104

α = 500.

For comparison, the actual magnitude is also shown as a solid curve.The two straight line asymptotes intersecting at ωo are a goodapproximation of the magnitude curve.It is also clear from Figure 14.28a that our approximation and theactual curve differ in the vicinity of ωo, and amount by which theydiffer relates to the peakiness of the curve, which in turn relates to thevalue of Q. For ωo = 104 and α = 500,

Q = ωo

2α= 10.

Figure 14.29 plots the frequency response for several values of Q(keeping ωo constant). It is easy to see that the difference between the

808b

(a) (b)

|

Frequency (rad/s)

|H

|

Q20

10

52

1

0.5

102 103 104 105 106106

107

108

109

1010

-10

|0102030405060708090

100110120130140150160170180

Frequency (rad/s)

<H

(de

gree

s)

O

Q 0.5 1 2 51020

102 103 104 105 610

F IGURE 14.29 Frequencyresponse of s2 + 2αs + ω2

o fordifferent values of Q.

actual magnitude (solid curves) and the approximate value from theBode splot (dashed curve) at ωo becomes substantial for large valuesof Q. The exact difference is computed in Equation 14.74.

Phase Plot

1. Sketch the low-frequency asymptote. The low-frequency asymptoteis given by:

∠H( jω) ≈= 0.

2. Sketch the high-frequency asymptote. The high-frequency asymptoteis given by:

∠H( jω) ≈= 180.

3. Mark ∠H( jωo) = 90, the angle of the system function at thefrequency ωo.

4. Draw a smooth line starting with the low-frequency asymptote,passing through 90 at ωo, and finishing off at the high-frequencyasymptote.Figure 14.28b shows these two asymptotes in dashed lines. Forcomparison, the actual phase curve is also shown as a solid line.

808c

e x a m p l e 14.6 b o d e p l o t e x a m p l e Let us sketch the frequencyresponse of the admittance of the second-order circuit in Figure 14.25 using the Bodemethod.

From Equation 14.66, the desired system function is

H(s) = IzVz

= s2 + s RL

+ 1LC

sC

+ RLC

.

For

L = 1 mH

C = 10 µF

R = 1

we get

ωo = 104 rad/s,

and

Q = 10.

Since Q > 0.5, the roots of the characteristic equation are complex and the circuit isresonant.

Substituting the numerical quantities into our system function, we get

H(s) = s2 + 1000s + 108

105(s + 103).

The system function has three terms: a constant term, a term of the form (s + a), anda quadratic term of the form (s2 + 2αs + ω2

o). The Bode construction of the magni-tude curve of the frequency response for the preceding transfer function is shown inFigure 14.30. The corresponding phase construction is shown in Figure 14.31. For ref-erence, the actual frequency response generated using a computer is shown using solidcurves.

808d

121086420-2

102 103 104 105 10610-2100102104106108

10101012

ω

|105 |

121086420-2

102 103 104 105 10610-2100102104106108

10101012

ω

|s2

+ 1

000s

+ 1

08 |

121086420-2

102 103 104 105 10610-2100102104106108

10101012

ω

|s +

103 |

|H| 1

0

-1

-2

102 103 104 105 106

10-2

10-1

100

101

ω

F IGURE 14.30 Construction of the magnitude curve of the Bode plot. The composite magnitude curve for the transfer function isobtained by subtracting the sum of the magnitude curves of 105 and (s + 103) from the magnitude curve of (s2 + 1000s + 108).

-90-60-30

|0306090

120150180

101 102 103 104 105 106

ω

<10

5

|-90-60-30

|0306090

120150180

101 102 103 104 105 106

ω

<s

+ 1

03

-90-60-30

0306090

120150180

101 102 103 104 105 106

ω

<s2

+ 1

000s

+ 1

08

|-90-60-30

0306090

120150180

<H

101 102 103 104 105 106

ω

F IGURE 14.31 Construction of the phase curve of the Bode plot.

808e

15.4.4 G EN E R A L I Z A T I O N ON I N P U T R E S I S T A N C E *

It is obviously of some importance to the circuit designer to know whetherfeedback is going to increase or decrease the effective input resistance of a circuit.We can generalize from the two circuits we have examined to state that the effectof feedback on input resistance depends on the circuit topology. If the sourcecurrent and the current through the feedback resistor and the current throughthe Op Amp input resistor ri all sum at a common node as in Figure 15.12,then the effective input resistance is very low, as shown in Equations 15.36 and15.38. (Remember, here we are referring to Ri, the resistance of the Op Ampcircuit to the right of Rs.) Equation 15.36 is in fact a general result: The inputconductance for any feedback circuit with this input topology (neglecting ri) isthe conductance without feedback, here 1/(Rf + rt), multiplied by 1 + A.

If, on the other hand, the source and the Op Amp input resistor are in series,forming a loop with the feedback resistor, as in Figure 15.14, the effective inputresistance of the circuit will be very high. In a word, if at the Op Amp input wesum currents at a node, the circuit input resistance is low, if we sum voltages ina loop, the input resistance is high.

855a

15.6.5 S A L L E N - K E Y F I L T E R

This section introduces a lowpass filter called the Sallen-Key filter. Its circuit andimpedance model are shown in Figure 15.25.

Let us focus on sinusoidal inputs and use the impedance method to obtainits input-output relationship. First, notice that the portion of the circuit withinthe dashed box is a non-inverting connection of the Op Amp with gain:

G = 1 + R1

R2. (15.94)

+

-

C

C

RR

R1R2

vi

vov2

v1

(a) Circuit

+

-

Vi

VoV2

V1

(b) Impedance model

1/Cs

R

R1

R2

1/C

s

R

F IGURE 15.25 The Sallen-Keycircuit.

866a

Thus, for the purpose of analysis, we can replace the circuit within the dashedbox with an amplifier whose gain is G. Therefore, we can write

Vo = GV1. (15.95)

Applying KCL for node V1

V2 − V1

R= V1

1/Cs,

which simplifies to:

V2 = (RCs + 1)V1.

Substituting for V1 in terms of Vo from Equation 15.95, we get

V2 = RCs + 1

GVo. (15.96)

Now, KCL for node V2 yields,

Vi − V2

R= V2 − V1

R+ V2 − Vo

1/Cs. (15.97)

Substituting for V1 and V2 in terms of Vo from Equations 15.95 and 15.96,we get

Vi − RCs+1G

Vo

R=(

RCs+1G

)Vo − 1

GVo

R+(

RCs+1G

)Vo − Vo

1Cs

. (15.98)

We can simplify Equation 15.98 and obtain the following expression relatingthe output voltage to the input voltage:

H(s) = Vo(s)

Vi(s)= G

R2C2s2 + RCs(3 − G) + 1. (15.99)

As a specific example, let us draw the frequency response for the filter trans-fer function for RC = 1 and R1 = R2. For these values, G = 2 and the

866b

-1.5 -1 -0.5 0 0.5-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Real Axis

Imag

Axi

s

F IGURE 15.26 Pole-zero plot ofthe Sallen-Key filter.

transfer function is given by:

H(s) = 2

s2 + s + 1(15.100)

or, factoring the denominator,

H(s) = 2

(s + 1/2 + j√

3/4)(s + 1/2 − j√

3/4). (15.101)

The transfer function represents a second-order filter. The expression in thedenominator has a pair of complex conjugate roots: −1/2 + j

√3/4 and

−1/2 − j√

3/4. In terms of the pole-zero nomenclature introduced inSection 13.4.3, the transfer function has two poles and no zeros. The polesare a complex conjugate pair located at −1/2 + j

√3/4 and −1/2 − j

√3/4.

Figure 15.26 depicts the pole locations using X’s in the complex plane. (Whenzeros exist, their locations are depicted using circles.)

We can now plot the frequency response as shown in Figure 15.27 bysubstituting s = jω in the transfer function:

H( jω) = 2

( jω)2 + jω + 1(15.102)

866c

F IGURE 15.27 Frequencyresponse for the Sallen-Key filter.

10-1 100 101 -200

-150

-100

-50

0

Frequency (radians)

Pha

se (

degr

ees)

10-1 100 10110-2

10-1

100

101

Frequency (radians)

Mag

nitu

de

or, in terms of the factored transfer function,

H( jω) = 2

( jω + 1/2 + j√

3/4)( jω + 1/2 − j√

3/4). (15.103)

As before, the frequency response in Figure 15.27 plots the magnitude and thephase of H( jω) versus the frequency ω.

866d

15.9 TWO -PORTS *

It should be obvious by now that circuits with dependent sources can performmuch more interesting and useful signal processing than those constructedsolely from two-terminal resistive elements. But inclusion of dependent sourceshas brought about a modest increase in circuit complexity, so it is useful atthis point to generalize some of the concepts introduced in previous chapters.In particular, let us examine how to generalize the Thévenin calculations tothree-terminal or four-terminal systems.

We start with a linear network containing resistors, voltage sources, andcurrent sources as we did in Figure 3.55, but now we assume two pairs ofexternal terminals, as shown in Figure 15.36. This network is called a two-port,

i1

v1

i2

v2

+

-

+

-

+-

F IGURE 15.36 Linear two-portnetwork.

or a two-terminal-pair network. For the purposes of the present discussion, itdoesn’t matter whether the two negative leads are tied together or go to somecommon ground, or both terminal pairs are floating with respect to ground.We wish to find a two-port Thévenin equivalent of this network. The deriva-tion is a simple extension of the method in Section 3.6.1. We apply currentsources at each of the ports, as in Figure 15.37a, then solve the problem bysuperposition. We first set all the independent sources, both internal and exter-nal, to zero except i2, and measure the resulting v2a as in the subcircuit ofFigure 15.37b. Because there is nothing left of the network except resistors (andpossibly dependent sources), v2a must be linearly dependent on i2 without off-sets. In other words, the ratio v2a/i2 is a pure resistance, a Thévenin-equivalentoutput resistance:

RThout = v2a

i2. (15.114)

Then we set i1 and i2 to zero, leave the internal sources active, as inFigure 15.37c, and measure v2b = v2oc, (this is what we previously calledthe open-circuit voltage). Finally we set i2 and the internal sources to zero,leaving i1 active, and measure v2c, which must be linearly dependent on i1, andhence can be written as

v2c = i1R21. (15.115)

This is clearly a dependent source relationship: an output voltage dependent onan input current. Now by superposition, the total output voltage is the sum ofthese three terms:

v2 = i1R21 + i2RThout + v2oc. (15.116)

A completely analogous argument yields for the input terminals:

v1 = i1RThin + i2R12 + v1oc (15.117)

872a

F IGURE 15.37 Two-portcalculations.

i1 v1 i2v2

+

-

+

-

i1 = 0

V = 0 i2v2a

+

-I = 0

RThout =v2a

i2-------

(a)

(b)

i1v2c

+

-

(d)

V = 0

I = 0

-------v2c

i1R21 =

+-

i1 = 0 v2b

+

-

+

-

(c)

+-

872b

i1v1a

i2 = 0

+

-

i2 = 0V1b = v1oc

RThin =v1a

i1-------

(a)

(b)

I = 0

V = 0

+

-

i2v1c

+

-

(c)

V = 0

I = 0

R12 =v1c

i2-------

+- F IGURE 15.38 Two-port input

calculations.

where RThin, v1oc, and R12 are measured or calculated using the subcircuits inFigures 15.38a, 15.38b, and 15.38c, respectively.

Equations 15.116 and 15.117 taken together, are a complete representa-tion of the network as viewed from the two terminal pairs or two ports. It iscommon practice in linear network theory to assume that there are no indepen-dent sources inside the network. In this case a rather simple generalization of theThévenin equivalent circuit emerges. Equations 15.116 and 15.117 simplify to

v1 = i1RThin + i2R12 (15.118)

v2 = i1R21 + i2RThout (15.119)

872c

and a simple circuit interpretation is now apparent. The term i2R12 in the equa-tion for the input port, Equation 15.118, is a voltage, dependent on the currentat the output. That is, it is a dependent voltage source, under the control of i2.The first term in Equation 15.118 is the Thévenin input resistance. Hence theequation can be represented in circuit form by the left half of Figure 15.39a. Theexpression for the output port, Equation 15.119 has similar structure, exceptthe role of input and output variables have been reversed. Hence the right halfof Figure 15.39a. The circuits and equations for calculating the four parameters(called z parameters in linear network theory) are given in Figures 15.37b and15.37d, and Figures 15.38a and 15.38c.

If we had chosen to drive the two-port with two voltage sources, ratherthan two current sources as in Figure 15.37, then from Section 3.6.2, the two-port version of the Norton equivalent would have emerged. The equationsanalogous to Equations 15.118 and 15.119 are

i1 = yinv1 + y12v2 (15.120)

i2 = y21v1 + youtv2 (15.121)

F IGURE 15.39 z and yparameter models.

+

-

i2R12v1

i1 Rthin

+

-

i1R21 v2

i2Rthout

(a) z parameter model

+

-

yinv1

i1

+

-

v 2

i2

yout

y21v1

y12v2

(b) y parameter model

+

-

+

-

872d

where the Y terms are conductances for resistive circuits. The circuit equivalent,called the y parameter model, is shown in Figure 15.39b. The expressionsfor each of the y parameters are readily derivable from Equations 15.120and 15.121, or from first principles, as in Figures 15.37 and 15.38, or by alinear transformation on the z parameters.

Two other representations, the g parameters and the h parameters, arise ifone excites the two-port with a voltage source at one port and a current sourceat the other. All four representations are related by linear transformations.

It is helpful to re-examine the calculation of Op Amp input and outputresistance in Section 15.4 from the more general two-port point of view of thissection. Because in Figures 15.11 and 15.12 we used a test voltage source atthe input and a test current source at the output, we in fact were calculatingthe g-parameters, defined in Figure 15.40a. To complete the calculation, weassume that in the Op Amp circuit, Figure 15.12, the reverse signal flow throughthe circuit is negligibly small. Hence g12 in Figure 15.40a is zero. Also, fromFigure 15.12 the forward dependent source g21 is approximately A, if we neglectthe drop in rt caused by current through Rf. On this basis the g-parameter rep-resentation for the inverting Op Amp connection is as shown in Figure 15.40b,assuming Rs is external to this model.

It is now (finally) possible to justify the omission of the ±12 V powersupplies in all calculations in this chapter. In terms of a two-port model, the

+

-

g12i2v1

i1

g11

+

-

g21v1 v2

i2g22

(a) g parameters

1/Ri

v++

-

voA(v+ - v-)

(b)

v2 = g21v1 + g22i2i1 = g11v1 + g12i2

v-

R o

+

-

+

-

F IGURE 15.40 g parametermodel for inverting Op Amp.

872e

power supplies would produce no measurable voltage or current at either theinput or the output of the circuit, because of the balanced nature of the circuit inthe active region. Hence inclusion of the power supplies would not change themodel parameters we have just derived, so it is correct to neglect these suppliesin all Op Amp active-region calculations.

872f

16.4.3 A SW I T C H E D POWER S U P P L Y U S I N G A D I O D E

In this example, we will analyze the behavior of the diode-based switched powersupply circuit shown in Figure 16.15. Notice that this circuit is similar to that inFigure 12.41, with the switch S2 replaced with a diode. As before, the purpose ofthe circuit is to convert the DC input voltage V to a different DC output voltagevOUT. The MOSFET in the circuit operates as a switch, and the square-waveinput to the MOSFET is shown in Figure 16.16. As before, we are interested indetermining the behavior of vOUT over time. As we will see shortly, the diodein the circuit also acts a switch, and results in an output waveform that is largelythe same as that of the circuit in Figure 12.41.

We will assume that the switch S1 has zero resistance associated with itsON state, and that the diode is ideal, so that the model in Figure 16.6 applies.Specifically, this means that the diode turns on and behaves like a short circuitwhen a positive current (iD) flows through it. The diode turns off and behaveslike an open circuit when the voltage (vD) across it is negative.

When the switch S1 is closed, it shorts the terminal connecting the diodeand the inductor to ground. Assuming that vOUT is non-negative, the diodebeing reverse biased is off. The DC voltage V appears directly across the inductoras illustrated in Figure 16.17, and the inductor current iL ramps up. Since S1 isthe on for time T, the inductor current builds up to

iL = VT

L(16.34)

as shown in Figure 16.16. Meanwhile, if there is no applied load at vOUT, thecapacitor voltage vOUT remains constant.

Next, when S1 is opened, the inductor current cannot instantaneously goto 0. Instead, the current finds a path through the diode (thereby turning it on)and into the capacitor. In its ON state, the diode behaves like a short circuit,and so the driven LC circuit shown in Figure 16.18 results. The current iL in the

V

+

-

C

L

+

-

vOUTiL

S1

vC

vD+ -

iD

F IGURE 16.15 A switchedpower supply circuit with diodeand a switch.

918a

F IGURE 16.16 Switched powersupply operation.

t

CLOSED

T

One cycleS1 State

(ON)

OPEN(OFF)

t

Diode

t

iL

0

t

vC

0

vC [n]

vC [n + 1]

VT

L------

StateDiodeOFF

DiodeON

DiodeOFF

TP

LC circuit follows a sinusoidal pattern as illustrated in Figure 16.16. Because ofthe flow of current into the capacitor, its voltage vOUT starts to increase, and ittoo follows a sinusoidal pattern.

As iL follows its sinusoidal pattern, it soon reaches zero and the positivevoltage on the capacitor attempts to drive it negative. At this instant, the diodeturns off and disconnects the capacitor from the rest of the circuit, so in theabsence of a load, the capacitor maintains its voltage.

918b

V

+

-

L

iL

S1

F IGURE 16.17 The equivalentcircuit when S1 is closed and thediode is open.

V

+

-

C

L

+

-

iL

vC

iD

F IGURE 16.18 The equivalentLC circuit when S1 is open and thediode is ON.

This cycle repeats, dumping some amount of charge into the capacitoreach cycle. We can compute the increase in vOUT very quickly using an energyargument similar to that used in Example 12.4 as follows: At the end of theramp, the inductor current is given by Equation 16.34, and so the energy storedin the inductor is given by:

wM = V2T2

2L.

Since the capacitor is charged by the inductor until iL becomes zero, the energy(wM) stored in the inductor is transferred completely to the capacitor in eachcycle. After n cycles, the energy stored in the capacitor becomes n times theenergy transferred in a single cycle, plus any energy initially stored on thecapacitor (say wE[0]):

wE[n] = nV2T2

2L+ wE[0].

Unlike Example 12.4, the capacitor must start with vC = V, since it is connectedby a diode instead of a switch to a voltage source. Unlike the switch, which can

918c

be forced to stay off, the (ideal) diode turns on if V is greater than vC. Therefore,

wE[0] = 1

2CV2.

Since wE[n] = CvOUT[n]2/2, we can derive the voltage after n cycles as:

vOUT[n] = V

√nT2

LC+ 1.

Substituting, ωo = 1/√

LC, we have

vOUT[n] = V√

nT2ω2o + 1.

If nT2ω2o 1, we get

vOUT[n] = VTωo√

n.

Finally, when a load is added to the circuit as shown in Figure 16.19, thecapacitor begins to discharge through the load. Suppose we wish to maintainthe voltage vOUT at a specified average value, say vREF, then in each cycle, wemust arrange to have the capacitor charged up by the same amount of chargethat it supplies to the load. This can be accomplished by using a feedbacksystem as shown in Figure 16.20.

In the circuit in Figure 16.20, the controller compares vOUT to vREF, andif vOUT falls below vREF, it increases the duration T for which the switch S1is kept ON, thereby increasing vOUT. Conversely, the controller decreases theduration T if vOUT increases past the value of vREF. Thus, vOUT is kept closeto vREF throughout.

F IGURE 16.19 Adding a load. C

L

+

-vOUT

iL

S1

vC RL

V

+

-

+

-

918d

C

L

+

-

vOUT

iL

S1

vC

RLV+

-

+

-

vREF

Control

change T

t

T

TP

F IGURE 16.20 Feedbacksystem to maintain a voltage vREFat the load.

918e

16.5 ADD I T I ONAL EXAMPLES

For review purposes, more examples of both piecewise linear and incrementalanalysis are given in the following subsections. No new material is presented,so readers who do not need additional practice can omit this section withoutloss of continuity.

16.5.1 P I E C EW I S E L I N E A R E X AMP L E :C L I P P I N G C I R C U I T

The output voltage vo in the diode clipper circuit, shown in Figure 16.21a, willresemble the input voltage vi, except that the bottom of the waveform willbe clipped off. The circuit has only one diode, so that the Thévenin solutionmethod discussed in Chapter 3.6.1 can be used, but here we will use the methodof assumed diode states. Assume that the diode in Figure 16.21 is ideal, thendraw the two subcircuits, one with the diode OFF, and the other with the diodeON, as shown in Figures 16.21b and 16.21c. By inspection, the output voltagewith the diode OFF is constant, because there is a fixed current IO flowing upthrough R. Thus

vo1 = −IOR. (16.35)

The current source and the voltage source are in series, so the voltage sourcehas no effect on vo1. Furthermore, when the diode is OFF,

vi = vo1 + vD. (16.36)

Because the diode is in the OFF state, vD must be negative. It follows that inthe OFF state vi must always be more negative than −IOR.

Next, when the diode is ON, the output is directly connected to the input:

vo2 = vi. (16.37)

In the ON state, vi must be more positive than −IOR. Hence the valid portionsof the waveforms in the subcircuits are the darkened segments, and the completeoutput waveform is as shown in Figure 16.21d. As promised, the circuit hasclipped off the bottom of the input wave.

16.5.2 E X PON EN T I A T I O N C I R C U I T

The circuit shown in Figure 16.22 produces an output voltage vOUT that isproportional to the exponential of the input voltage vIN for sufficiently largevIN. To analyze this circuit, assume that the Op Amp is ideal, the saturationcurrent of the diode is Is = 10−12 A, and the temperature of the diode isapproximately 29C so that its thermal voltage is VTH = 26 mV. Because

918f

vo

vo1

+-

+

-

Rvi

IO

vo1

+

-

+

-

Rvi

IO

iD = 0

+ -vD

Valid for vi < -IOR

vo2

+-

+

-

Rvi

IO

vD = 0+ -

Valid for vi > -IOR

vi

t

-IOR

vo2

vi = vo2

t

-IOR

vo

vo

vi

(a)

(b)

(c)

(d)

t

-IOR

F IGURE 16.21 Diode clipper.

918g

F IGURE 16.22 A diode-basedexponentiation circuit. +

-

vOUT+

-

vIN

+-

R = 100 kΩ

iD

the Op Amp is ideal, and used in a stable negative-feedback configuration, thevoltage at the inverting terminal of the Op Amp is zero. As a result,

iD = Is(evIN/VTH − 1

)= 10−12 A

(evIN/(26 mV) − 1

).

For sufficiently large vIN, for example for vIN ≥ 120 mV, the exponential termdominates, and this relation simplifies to

iD ≈ 10−12 A evIN/(26 mV) .

Next, because the voltage at the inverting terminal of the Op Amp iszero, and because the current into that terminal is zero, the output voltageis given by

vOUT = −RiD ≈ −10−7 V evIN/(26 mV),

which exhibits an exponential dependence on vIN.For example, for vIN = 200 mV, 300 mV, and 400 mV, vOUT =

−0.219 mV, −10.3 mV, and −480 mV, respectively.

16.5.3 P I E C EW I S E L I N E A R E X AMP L E : L I M I T E R

The circuit in Figure 16.23 is useful for making square waves out of sine waves,and for limiting the amplitude of an output waveform when the input waveformamplitude varies over a wide range. To analyze the circuit, we note that theThévenin approach is not helpful, and a graphical solution might be messybecause of the two diodes (not so, in fact, but that is not obvious yet). So resortto analysis by assumed diode states. The subcircuits for the four states, assumingan ideal-diode model, are shown in Figures 16.23b, 16.23c, 16.23d, and 16.23e

918h

vo

vo1

+-

+

-

R

vi

vi

t

vi

(a) Limiter circuit

D2+-

V+

-V

D1

vo1

+-

+

-

R

vi

(b) Both diodes OFF

vD1

+-V +

-V

OFF OFF+-

vD2+-

vo2

+-

+

-

R

vi

(c) D1 ON

V+

-V

OFF+-

vo3

+-

+

-

R

vi

(d) D2 ON

V+-V

OFF

+-

vo4

+-

+

-

R

vi

(e) Both diodes ON

V

ON

+-

V+

-

ON

+V

-V

vo2

vo3

+V

-V

vo

0

0

(f) Complete waveform

t

t

t0

0

vo

F IGURE 16.23 Diode limiter.

918i

along with the appropriate subcircuit output voltages, obtainable by inspection.From Figure 16.23b,

vo1 = vi (16.38)

because there is no current through R. When either diode is ON, the outputvoltage is independent of the source voltage vi. For D1, ON, for example,vo2 = V. The fourth diode state, Figure 16.23e, cannot be reached with thistopology, (assuming V is a positive quantity) because there is no value of vi thatwill force both diodes ON at the same time. Now we must identify the validsegments of these waveforms. In Figure 16.23b, both diodes are assumed OFF,so vd1 and vd2 must both be less than zero. Hence, using KVL:

vi − V = vD1 < 0 (16.39)

vi < V (16.40)

−vi − V = vD2 < 0 (16.41)

vi > −V. (16.42)

Thus vi must be between −V and +V. Likewise vo1, from Equation 16.38.This range of validity is indicated by the darkened segments of the waveformin Figure 16.23b. It follows that the complete output wave must be as shownin Figure 16.23f. If the peak amplitude of vi is ten or twenty times V, then vo isa reasonable approximation of a square wave.

16.5.4 E X AMP L E : F U L L - W A V E D I O D E B R I D G E

Figure 16.24 shows one of the most common rectifier circuits found in elec-tronic equipment, the full-wave diode bridge. We assume therefore that vi is a60-Hertz sinusoid with 10-volt peak amplitude, and we wish to find the wave-form vo across the output resistor. A full-blown assault using assumed diodestates would yield 16 subcircuits, but it will turn out that only two of theseare possible, suggesting a more insightful approach. Suppose that vi is a smallpositive voltage. Then current must flow down through the bridge. The onlyavailable path is D1, RL, and D4, because of the orientation of D3 and D2.Similarly, for vi negative, current must flow up, and thus must follow the pathD3, RL, D2. The two corresponding subcircuits, assuming ideal diodes, areshown in Figures 16.24b and 16.24c. Now, by inspection, for vi positive,

vo = vi (16.43)

and for vi negative,

vo = −vi. (16.44)

918j

(e)

vi

+

- RL

D1 D2

D3 D4

vo+ -

voA

D3

D1 OFF

+ -vi

+

-OFF

voB

D4 OFF

D1 OFF+ -vi

+

-

voC

D3 OFF

+vi

+

-D4 OFF

-

t

(a)

(b) Subcircuit for vi positive

(c) Subcircuit for vi negative

(d) D1 and D2 ON

t

vovi

F IGURE 16.24 Full-wave diodebridge.

All other subcircuits are degenerate. Consider, for example, the subcircuit forboth D1 and D2 ON, as in Figure 16.24d. Clearly no current can flow in RL.Also, current can’t flow down through D3, or up through D4, so all diode cur-rents must be zero in this state. A similar argument holds for all adjacent diodepairs, whether ON or OFF. Hence the two states depicted in Figures 16.24band 16.24c are the only ones we need to consider.

Note that the current always flows in the same direction through RL,regardless of the polarity of vi. For sinusoidal input the waveforms appearas in Figure 16.24e. The circuit is called a full-wave rectifier because currentflows through RL on both halves of the input wave. Neglecting diode volt-age drops, the average value of the output voltage, that is the DC voltage, is0.637 times the peak of the input sinusoid. Further, by symmetry there is nofrequency component in the output waveform at the input frequency, 60 Hertzin our example, or odd multiples thereof. Hence the circuit has a much higherpercentage of DC relative to harmonics compared to the half-wave rectifierdiscussed in Section 4.3.

918k

F IGURE 16.25 Zener-dioderegulator.

vov

i+

-

v

+

-

+

-

R

50 mV AC

20 V DC

(a) (b)

i

16.5.5 I N C R EM EN T A L E X AMP L E : Z E N E R - D I O D ER E GU L A T O R

All semiconductor diodes will break down and conduct appreciable currentunder reverse bias conditions if the reverse voltage across the diode is largeenough. This breakdown is non-destructive if the current is not excessive; thediode returns to normal reverse-bias behavior if the voltage is reduced. A Zenerdiode is a semiconductor diode in which this breakdown under reverse bias iscarefully controlled by the manufacturing process so that the breakdown occursat a specified voltage, the so-called Zener voltage of the diode. A typical v icurve is shown in Figure 16.25a.

Because the breakdown voltage of a Zener diode can be carefully con-trolled by the manufacturing process, and the incremental resistance in thebreakdown region is quite small (around 10 to 50 ), Zener diodes arequite useful as voltage regulators. A simple example is shown in Figure 16.25b.Equation 4.74 is clearly inappropriate for finding the incremental resistance inbreakdown, because this part of the characteristic is not an exponential. Hencethe value must be obtained from the data sheet for the Zener diode in question.Integrated-circuit regulators, with transistors, Zener diodes, and resistors allon a single chip, will certainly outperform either of the crude regulator circuitsdiscussed here.

16.5.6 I N C R EM EN T A L E X AMP L E :D I O D E A T T E NU A T O R

It should be clear from Section 4.5, and particularly from Equations 4.63and 4.74, that for small increments of voltage or current, the semiconduc-tor diode looks like a linear resistor whose value depends on the DC currentflowing through it. Thus it should be fairly easy to build an attenuator withan attenuation constant that can be changed by means of an external voltageor current. Figure 16.26 shows a simple example. Here a diode is used in theshunt branch of a voltage divider on a small-signal source vi. The DC cur-rent through the diode is controlled by the DC voltage VC through the large

918l

RC

R1

rd

+

-

(a)

VC

+

- vi

+

-

RC

R1

(b)

VC

+

- ID0

Rt = R1||RC

Rd(c)

+- 0.6 V-VOC = VC

R1

R1 + RC-------------------

RC

R1

(d)

+

-

0

+-

vi

vo

F IGURE 16.26 Diodeattenuator.

resistor RC. If we assume that vi produces less than a 5 mV change in thediode voltage, then the incremental analysis approach discussed in Section 4.5can be applied.

First, draw the circuit for the calculation of the DC current ID0 is to form theThévenin equivalent of the linear part of the circuit, as shown in Figure 16.26b.An easy way to solve for ID0 is to form the Thévenin equivalent of the linearpart of the circuit, as shown in Figure 16.26c. At the same time we replace thediode by its piecewise linear model. Then

ID0 = (VOC − 0.6)

Rt + Rd. (16.45)

The incremental resistance rd of the diode will thus be a function of VC:

rd = kT

qID0(16.46)

= kT

q

(R1‖RC) + Rd

VCR1

R1+RC− 0.6

. (16.47)

Now draw the subcircuit that relates the incremental variables. Replace thediode in Figure 16.26a by the incremental resistance rd, and set all DC sources,in this case VC, to zero, as indicated in Figure 16.26d. By inspection,

vo = viRC‖rd

R1 + (RC‖rd). (16.48)

The attenuation is clearly dependent on the DC voltage VC, as desired.

918m