61 1 IEFb TRANSACTIONS ON POWFR ELFCTRONICS VOL 6 NO 4 OCTOBLR 1991

Practical Switch Based State-Space Modeling of DC-DC Converters with All Parasitics

Chun T. Rim, Gyu B. Joung, and Gyu H. Cho, Member, IEEE

Abstract-All parasitics such as switch conduction voltages, conduction resistances, switching times and ESR’s of capaci- tors are counted in the new state-space modeling based on non- ideal switching functions. An equivalent simplified model is de- rived from the complex circuit with parasitics. Hence the re- sults are very simple. The pole frequency, dc voltage gain and efficiency of the general converter, the buck-boost converter are analyzed and verified by experiments with good agreements with the theories. The procedure for determining the gain mar- gin of controller, the turn-ratio of isolation transformer, the optimum duty factor and the switching frequency is given for an example flyback converter.

I . INTRODUCTION N THE modeling of switching systems, parasitics such I as switch conduction voltages, conduction resistances,

switching times and ESR’s of capacitors are commonly ignored because of the difficulties in the modeling and complexities in the result. This situation of excluding par- asitics is very helpful for the understanding of the main features of a switching system. Most conventional mod- elings are thought to be adequate for this purpose [ 2 ] - [ 6 ] . So it is no doubt that these modelings are successful in the primary stage design of a switching system. However the parasitic effects should be counted in the secondary stage design, where high performances such as high gain, efficiency and robustness of system poles are required. If we note the fact that efficiencies of typical switching reg- ulators are about 70-85 % [7], the parasitics are frequently not negligible in practice. A few papers which deal with the effects in part are found, but a large part of them are based on computer simulations [SI-[ 101. These consid- erably reduce the effort in the modeling, however. they give solutions for only finite selected values with poor physical insight. Only a few papers are found which give analytical results useful for the secondary design [ 111- [ 151. Parasitic resistances and part of switching times are counted in [ l 11. Rough description of all parasitics is found in [ 121. And switching times are considered in [ 131- [14]. Parasitics except the switching times are briefly ex- plained in [ 151. Oscillations due to turn-off delay time variation is studied in [ 161.

In this paper all parasitic effects are integrated into one as a summary of the previous works using a new state

Manuscript received January 5. 1988: revised February 1989. This paper was presented at the 1988 Power Electronics Specialists Conference. Kyoto Japan. April 11-14.

The authors are wi th Korea Advanced Institute of Science and Technol- o&y. P.O. Box 150. Chongryang. Seoul. 131 Korea.

IEEE Log Number 9101945.

space modeling. The analytical results are quite simpler than the previous works but they are very exact. This fea- ture of the modeling makes us understand the parasitics easily. It is also verified that all parasitic resistances are integrated into an equivalent resistor.

This paper is an extension of the previous work where switching time effect is extensively studied [ I ] . The no- tations and parameters are just same. The modeling pro- cedure is shown for the buck-boost converter as the gen- eral converter among the buck, boost, and buck-boost converters. The modeling is based on the state-space de- scription and nonideal switching functions. An equivalent circuit that eliminates all parasitics except switching times is derived without any approximation. This simplified cir- cuit is found to be just the same circuit used in [l] . Then the modeling is verified by the experiments with good agreement with theories. The results are also summarized in a compact table.

11. MODELING PROCEDURE It is assumed that the circuit elements are linear time

invariant and that the switches have finite switching times, conduction voltages VQ and V, and conduction resistances R, and RD. The inductor and capacitor are assumed to have series resistances. Continuous conduction mode is assumed and the switching time modulation is permitted. The circuit to be modeled is shown in Fig. 1.

A . Equivalent State-Space Model Assuming that switching operation is not much affected

by parasitic voltages and resistances, the switching func- tions defined in [ l ] can be used here also. The switching functions are composed of ramp, exponential, and step functions so that they may reflect more practical switch- ing actions.

Then the derivatives of states of the buck-boost con- verter of Fig. l(a) are found to be

0885-899319111000-061 l$Ol.OO 4 1991 IEEE

612 IEEE TRANSACTIONS ON POWER ELECTRONICS. VOL. 6. NO. 4 . OCTOBER 1991

Q , D : switches with f ini te switching times

(C)

Fig. 1 . Original circuits with all parasitics. (a) Buck-boost converter. (b) Buck converter. (c) Boost converter.

( lb)

and the output equation is represented as

where the switching functions s l ( t ) and s2(r) are linear functions of duty cycle h and s3(t) and s4(t) are the com- plementary functions of s l ( t ) and s2(t) , respectively, that is,

Equation (1) is very exact, however, it is somewhat com- plex to deal with. Hence (1) is simplified by introducing the new variables as

XI

rc Lx, = - [R, , + R,(t) + s2(r)r,.Rc] - - sl ( t )x2

+ S 3 ( f ) U * - U T ( t ) ( 4 4

(4b)

(4c) Note that no approximation is used to obtain this simpli- fied model.

The model for the buck converter of Fig. l(b) is found as

x2 cx2 = s,(t)x, - - RL

y = s ~ ( ~ ) R C X ~ + ~ 2 .

x2 cx, = XI - - RL

y = R c ~ i + ~ 2 . (5c) and that for the boost converter of Fig. l(c) is found as

X I

rc Lxl = -[Rho + R,(t) + s2(t)r,Rc1 - - s l ( t )x2

+ U* - u,(t) ( 6 4

(6b)

(6c) It is observed that the models for the buck and boost con- verters given by ( 5 ) and (6) can be deduced from the model for the buck-boost converter given by (4) if only s l ( t ) , s,(t) and s&), s,(t) are set to unities, respectively. This means that it is not necessary to analyze the buck and the boost converters since they can be explained from the analysis result of the general buck-boost converter.

Then the state equation and the output equation of the buck-boost converter are obtained from (4) as

x2 Cx2 = s2(t )xl - - RL

y =z SZ(t)RcXl + ~ 2 .

- -~ C

(8) These compact equations which represents the complex switching operations are of time-varying form. Equation

u,%(t) = s3(t)u* - uF(t) .

Then (1) becomes

RIM er al.: PRACTICAL SWITCH BASED STATE-SPACE MODELING OF DC-DC CONVERTERS

__

613

(7) is of the form

.i = A ( t ) x + B*v,\(t) ( 9 4

y = C ( t ) x . (9b)

B. State-Space Averaging and Perturbation It is postulated that the frequency spectrums of switch-

ing functions are much higher than the converter filter cut- off frequency and that harmonic losses in resistances are negligible. Then the generalized state-space averaging can be taken for the time-varying matrices and the source [ 11.

where

and

B = E], B* = [:I. 11

U , = V,( t ) = S3U* - VT = s3u,

Time-varying switching functions and resistances are changed to the averaged values. It is found that (lob) is just the state-space averaged equation of the circuit of Fig. 2 which is the same circuit analyzed in 111. All parasitics except the switching times are apparently disappeared in the simplified circuit. All parasitic resistances are unified into an equivalent resistor R, and all parasitic voltage sources are integrated into an equivalent voltage source U . Thus the analyses results of 113 can be used here, con- sidering the slight modification of the matrix C and as- suming that the variations of R, and VT are negligible.

Hence the dc and ac parts of the perturbed equation are

X, = A,Xo + BoUo

Y, = c,x, (13)

and

P = (A , + A2XoW + B2UOW)i + (A,Xo + B,Uo) i

9 = c,a + ClX,h . (14)

U

Fig. 2 . Equivalent simplified buck-boost converter.

And the operating point Yo and the ac transfer function G(s) are

Y, = -C~A;’B,U, (1 5 4

where the matrices are

L c CR,J

C I is added due to the parasitic resistance Rc

C. Pole Frequency

equation: The poles are found by evaluating the characteristic

IsZ - A0 - A,&W - B,UoW( = 0. (17)

The normalized natural frequency w,* and normalized damping factor I* are the same as those of [ l ] since (17) has not C,:

The switching time modulation effect is counted in r,* and s;, and the duty cycle variation effect is represented in s I and s;. By these equations the robustness of system poles is identified.

In the design of controllers the frequency drift pre- dicted by (18) should be counted in the gain or phase mar- gins.

614

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IEEE TRANSACTIONS ON POWER ELECTRONICS. VOL. b. NO. 4. OCTOBER 1991

D. DC Gain The dc voltage gain Gs is obtained from (15a) as

U*

(19) G, is slightly modified by rc compared with the result in [ l ] . (19) is not the true dc voltage gain, however, since U, is not the true source voltage U,*. From (12) the ratio of U, to U t is determined as

Then the true voltage gain G,, is evaluated as

(21) It is notable that the G,, and G,. are concerned with the switching loss and conduction loss, respectively. It can be seen that voltage degeneration due to conduction volt- age loss increases as the duty cycle decreases (for the buck and buck-boost converters only) and that the boost con- verter is robust to the conduction voltage loss.

E. Eficiency

rent I , to the input current I , is obtained as The current gain G, which is the ratio of the output cur-

Then the efficiency q becomes

where qs and qr are the efficiency degenerations due to switching loss including parasitic resistances and conduc- tion loss, respectively. They are given as

The qc is much deteriorated when the source voltage is low and the duty cycle (for the buck and buck-boost con- verters only) is low. For example, the efficiency becomes not more than 70% when VT = VQ = VD = 0.6 V, the source voltage is 10 V and the duty cycle is 0.2 even though the switching frequency is low. Hence, it is desir- able to set the duty cycle near to unity for the buck con- verter to avoid excessive conduction loss.

In the low-voltage high-efficiency applications, qc may be a reference for determining qF or accordingly the switching frequency. If q F is much less than qc then the switching frequency becomes unacceptably too low,

RL 21 7

which results in a very large filter size. A good example is to let q , be the same as 7,.

111. EXPERIMENT Experiments are done even for extreme cases such as

very high frequencies and very low efficiencies to test the validity of the proposed model. The boost converter shown in Fig. 3 is selected as an example converter. The ratings of the switching devices are selected very high enough to overcome severe experiment conditions. Since several switching times are very sensitive to the base driver, temperature and current, the base driver is simpli- fied and the switching times are measured case by case at the ambient temperature of 25°C. Fig. 4 is the picture of a practical switching case. The upper is the base drive voltage, the middle is the collector-emitter voltage of the transistor and the lower is the diode current. The param- eters of the switching devices are

transistor: 600 V , 200 A , VQ = 0.5 V,

R , = 0.035 0

diode: 600 V, 200 A, VD = 0.5 V, RD = 0.25 !I.

(25 )

The natural frequency of the open loop system is de- termined by inserting a small step change in the duty cycle and measuring the rise time and the overshoot of the re- sponse. This is depicted in Fig. 5 . It is observed that the parasitic effects become dominant as the switching fre- quency increases. The switching times and the derivatives of them with respect to the inductor current for this ex- periment are tabulated in Table I . There are a lot varia- tions of them due to the variations of collector current and temperature. The values are about five times larger than those of conventional 100-W class converters. Unfortu- nately, the data are not based on the uniform temperature distribution due to the difficulty in keeping the tempera- ture of the switches be constant.

The voltage gain is measured by dividing the output voltage by the input voltage for the wide range of duty cycle. That is shown in Fig. 6 for several switching fre- quencies with a large deviation from the ideal switching case. It is observed that the switching loss is the major source of the degeneration of the voltage gain.

The efficiency is calculated by measuring the currents and the voltages of the input and output, and comparing

I

RIM er a l . :

3 ~ 1 0 ~ -

PRACTICAL SWITCH BASED STATE-SPACE MODELING OF DC-DC CONVERTERS

\.

615

TABLE I THE SWITCHING TIMES A N D THEIR DERIVATIVES WITH RESPECT TO THE CURRENT

HO 0.3 0.5 0.7

f W z 1 5 k 10k 2 0 k 5 k 10k 2 0 k 5 k 10k 2 0 k

[I [PSI 6.1 7 . 8 9 . 5 6.3 8.0 8.3 8.5 5.5 -1.0 ~ , [ / L s ] -16 .0 -16 .9 -12 .4 -13 .0 -11 .8 -9 .4 -9.1 -10.2 -11.2

- 0 . 2 -1.0 -1 .2 1.3 0 .6 -0 .5 -0 .3 - 0 . 6 -0.4 rlt, dX,

-16 .0 -9 .3 -7.7 - 3 . 9 -3 .1 - 2 . 0 -1 .3 -1 .5 0.5 dt, dxi -

Fig. 4. Switching waveforms. Upper: base drive input voltage; I O V/div.; 10 ps/div.; middle: collector-emitter voltage; 20 V/div.; lower: diode current: 5 A l d i v . , +: GND.

the input and output powers. It is shown in Fig. 7 for several duty cycles. A little discrepancy between the the- ory and the experiment is found to be due to the harmonic losses in resistors. It was postulated that these losses are negligible.

On the whole, the proposed model predicts the pole fre- quency, dc voltage gain, and efficiency of converters with parasitics exactly to the extend of extreme cases.

IV. DISCUSSION AND SUMMARY The proposed model can be used to determine the gain

margin of controller, the turn-ratio of isolation trans-

I

,/

0 r H 0 0.5 (b)

Fig. 6. Voltage gains of experimental boost converter. (a) -: theory. - _ : ideal case, 0: f = 1 kHz, ti: f = 20 kHz. (b) -: theory, --: ideal case, A:!= 5 kHz, o:f= 50 kHz.

former, and the switching frequency for given efficiency. An example procedure for a fly-back converter is given here.

Since the switching times are varied by collector cur- rent and temperature, it is necessary to measure (or find when data sheet is available) the minimum and maximum values of them first, and determine roughly the initial val- ues of the turn-ratio, duty cycle, and switching frequency. The initial turn-ratio can be set to the ratio of input supply voltage and output voltage. The initial duty cycle can be

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1.0 r IEEE TRANSACTlONS ON POWER ELECTRONICS, VOL. 6. NO. 4, OCTOBER 1991

TABLE I1 SUMMARIES OF PARASITIC EFFECTS

Type Buck Boost Buck-boost

1

.r*

set to 0.5 as discussed in [ l ] . The initial switching fre- quency can also be determined by letting the conduction and switching efficiencies are equal using (24). , These can be used to calculate the initial equivalent parameters as shown in Fig. l(a).

Then plot the curves such as Figs. 5-7. The corrected switching frequency is found from the efficiency curve for a given efficiency. The corrected tum-ratio is found from the voltage gain curve. The amount to be compensated is measured for a given switching frequency and initial duty cycle and this is multiplied to the initial turn-ratio. The corrected duty factor is calculated for a given switching frequency as shown in [ 13. The gain margin is found from the pole frequency curve for a given switching frequency and duty cycle.

If the corrected values have much deviations from the initial values then repeat the procedure again. In practical case the gain margin and the turn-ratio need to be in- creased about 10-20% from the ideal converter.

The analytical results are tabulated in Table I1 using the normalized resistance r,, r,, the conduction voltage VT and the average switching functions s,, s2, s3 and s4. The pole frequency, dc voltage gain, dc current gain, and efficiency of the buck and boost converters are those of the buck- boost converter whose sI, s2 and s3, s4 are set to l’s, re- spectively.

The dc voltage gain and efficiency are also found to be just the products of those of the conduction loss term and those of the switching loss term.

V. CONCLUSION All parasitics, such as switch conduction voltages, and

conduction resistances, switching times, and ESR’s of ca- pacitors are counted in the new state-space modeling which is based on nonideal switching functions. The re- sults are, however, quite simple and are verified by a boost converter example that they are very exact even for sev- eral extreme cases.

A very simple equivalent circuit is deduced from the complex original circuit that has all parasitics. The para-

r: + s,~: r: + I

1

Fig. 7 . Eficiencies of experimental boost converter. -: theory; A : Ho = 0.3, 0: H,] = 0.7.

V T

U * I - -

s2

r, = R , / R , . r: = RT/R, .

sitic effects become dominant as the switching frequency, parasitic resistances, duty cycle (for the boost converter case), and conduction voltage increase and the duty cycle (for the buck converter case) and source voltage decrease. Those of the buck-boost converter become dominant as the duty cycle approaches to either zero or unity.

The procedure for determining the gain margin of con- troller, the turn-ratio of isolation transformer, the opti- mum duty cycle and the switching frequency is suggested based on the proposed model.

REFERENCES

[ I ] C. T. Rim, G. B. Joung, and G. H . Cho, “A state space modeling of non-ideal dc-dc converters,” in IEEE Power Electronics Special- ists Con$ Rec., 1988, pp. 943-950.

[2] R . D. Middlebrook and S . Cuk, “A general unified approach to mod- eling switching converter stages,” in IEEE Power Electronics Spe- cialists Conf. Rec., 1976, pp. 18-34.

[3] P. Wood, “General theory of switching power converters,” in IEEE Power Electronics Specialists Con$ Rec., 1979, pp. 3-10.

[4] G. Verghese and U . Mukherji, “Extended averaging and control pro- cedures,’’ in IEEE Power Electronics Specialists Conf. Rec., 1981,

[5] G. C. Verghese, M. E. Elbuluk, and J . G. Kassakian, “A general approach to sampled-data modeling for power electronic circuits,” IEEE Trans. Power Electronics, vol. PE-I, no. 2, Apr. 1986, pp, 76-89.

161 K . D. T . Ngo, “Low frequency characterization of PWM con-

pp. 329-336.

I

et a l . : PRACTICAL SWITCH BASED STATE-SPACE MODELING OF DC-DC CONVERTERS 617

verter,” IEEE Trans. Power Electronics. vol. PE-1, no. 4, Oct. 1986.

Motorola Data Book, Linear and Interface Integrated Circuits, Mo- torola Inc., 1985. H. Haneda, Y . Kuroe, and T . Maruhashi, “Computer-aided analysis of power-electronic DC-motor drives: transient and steady-state anal- ysis,” in IEEE Power Electronics Specialists CoriJ Rec.. 1982, pp. 128- 139. S . S . Kelkar and F. C. Y . Lee, “A fast time domain digital simulation technique for power converters: application to a buck converter with feed forward compensation,” fEEE Trans. Power Electron., vol. PE- 1 . no.1. DD. 21-31. Jan. 1986

pp. 223-230. Chun T. Rim was born in Korea on December 7 , 1962. He received the B.S . degree from Kumoh lnstitute of Technology, Kumi, Korea, and the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Seoul, in 1985, 1987, and 1990, respectively, all in electrical engineering.

His research areas are the modeling of linear switching systems, the control of resonant con- verters. the design of SMPS and the design of lin- ear IC’s.

. I

1 F C Y . Lee, R. P Iwens, Y Y u , and J E. Triner, “Generalized Gyu B. Joung was born in Korea in 1961. He re- computer-aided discrete time-domain modeling and analysis of DC- ceived the B S degree from AJU University, SU- DC converters,” IEEE Trans Ind Electron Contr fnstruni , vol won, Korea, and the M S and Ph.D degrees from IECl-26, no 2, pp 58-69, May 1979 Korea Advanced lnstitute of Science and Tech-

I W M Polivka, P R K Chetty, and R D Middlebrook, “State- nology (KAIST), Seoul, all in electrical engineer- space average modeling of converters with parasitics and storage-time ing, in 1984, 1986, and 1990, respectively. modulation,” in IEEE Power Ekctronics Specialist, Conf Re< , pp His research interests include all aspects of 219-243. 1980 power electronics, particularly resonant convert-

[I21 R. C. Wong, G. E Rodriguez, H. A Owen, Jr . and T G Wilson, ers, and modeling of power converters “Application of small-signal modeling and measurement techniques to the stability analysis of an integrated switching-mode power sy\- tern,” in fEEE Power Electronics Specialists Conj” Rec , 1980. pp 104-118 Gyu H. Cho (S’76-S’78-M’80) was born in Ko-

1131 G Eggers. “Fast switches in linear networks,” IEEE Truns PUWYI rea on April 19, 1953 He received the M S. and Electron . vol PE-I, no 3, pp 129-140. July 1986 Ph D. degrees from Korea Advanced Institute of

[I41 J Sebastian and J Uceda, “The double converter. A fully regulated Science and Technology (KAIST), Seoul, in 1977 two- output dc-dc converter,” fEEE Trans Pobtvr Electron , vol and 198 I , respectively PE-2, no 3 , pp 239-246. July 1987 During 1982-1983, he joined the Electronic

[IS] R D. Middlebrook and S Cuk. “Modeling and analysis methods tor Technology Division of Westinghouae R&D Cen- dc-to-dc switching converters,” invited review paper, in fEEE fnrer- ter. Pittsburgh, PA, where he worked on unre- national Semiconductor Power Converter Conj Rec , 1977. pp 90- stricted frequency changer systems and inverters. 1 1 1 Since 1984, he has been an AssistadAssociate

[I61 V. J. Thottuvelil and T G Wilson, “Study of oscillations due to turn Professor in the Electrical Engineering Depart- off delay variations in DC-to-DC converters employing BJT ment of KAIST, where he is now d Professor. His research interests are in switches,” in IEEE Power Electroiucs Spec/u/rrtJ Conf Rec , 1988. the area of static power converters and drivers, resonant converters and pp 951-959 integrated linear electronic circuit design