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GEC 2000 Tutorial

10 Gigabit Ethernet Physical Layer

Presented by: Rich Taborek, Corp.2500-5 Augustine Dr., Santa Clara, CA 95054; 408-845-6102; [email protected]

Presentation Material derived from:

IEEE 802.3ae Task Force10 Gigabit Ethernet Alliance

nnnnnnnnSerialSerial

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10 GbE Physical GEC 2000 Tutorial

Tutorial Agenda

Introduction to the 10 GbE Physical Layer

Layered Model MAC/PHY Interfaces

Physical Coding Sublayer - Coding

Physical Medium Attachment - Signaling

Physical Medium Dependent - Opto-Electronics

UniPHY Overview Alternative Ethernet WAN Support Acknowledgements

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PHY Related Objectives 1 of 2

Preserve the 802.3/Ethernet frame format Preserve 802.3 minimum and maximum Frame Size Support full-duplex operation only Support star-wired local area networks using point-to-point

links and structured cabling topologies.

Specify an optional Media Independent Interface (MII). Support a speed of 10 Gbps at the MAC/PLS Define a LAN PHY, operating at a data rate of 10 Gbps

Define a WAN PHY, operating at a data rate compatiblewith the payload rate of OC-192c/SDH VC-4-64cu Define a mechanism to adapt the MAC/PLS data rate to the data

rate of the WAN PHY

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PHY Related Objectives 2 of 2

Provide Physical Layer specifications which support linkdistances of:

u At least 100 m over installed MMF

u At least 300 m over any MMF

u At least 2 km over SMF



Support fiber media selected from the second edition ofISO/IEC 11801

u 802.3 to work with SC25/WG3 to develop appropriate

specifications for any new fiber media

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802.3 Layer Model to 1 GbE

PHYSICAL

DATA LINK

NETWORK

TRANSPORT

SESSION

PRESENTATION

APPLICATION

OSI

REFERENCE

MODEL

LAYERS

PMA

PLS

PMA

PLS

Reconciliation

PMD

PMA

PCS

Reconciliation

PMD

PMA

PCS

Reconciliation

MAC

MAC CONTROL (Optional)

LLC

MEDIUM MEDIUMMEDIUM MEDIUM

AUI

MAU

PHY

MII GMII

MDI MDI MDI MDI

AUI

MII

LAN

CSMA/CD

LAYERS

HIGHER LAYERS

AUI = Attachment Unit Interface

MDI = Medium Dependent Interface

MII = Media Independent Interface

GMII = Gigabit Media Independent Interface

MAU = Medium Attachment Unit

1 Mb/s, 10 Mb/s 10 Mb/s 100 Mb/s 1000 Mb/s

PLS = Physical Layer Signaling

PCS = Physical Coding Sublayer

PMA = Physical Medium Attachment

PHY = Physical Layer Device

PMD = Physical Medium Dependent

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802.3 Proposed 10 GbE Layer Model

PHYSICAL

DATA LINK

NETWORK

TRANSPORT

SESSION

PRESENTATION

APPLICATION

OSI

REFERENCE

MODEL

LAYERS

Reconciliation

MAC

MAC Control (Optional)

LLC

XAUI

LAN

LAYERS

HIGHER LAYERS


XGMII = 10 Gigabit Media Independent Interface

XAUI = 10 Gigabit Attachment Unit Interface


XGXS = XGMII Extender Sublayer




PMD

MEDIUM

MDI

XGXS

XGMII

PMA

PCS

XGXS

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MAC/PHY Interfaces - XGMII/XAUI

PHYSICAL

DATA LINK

NETWORK

TRANSPORT

SESSION

PRESENTATION

APPLICATION

OSI

REFERENCE

MODEL

LAYERS

Reconciliation

MAC


LLC

XAUI

LAN

LAYERS

HIGHER LAYERS









PMD

MEDIUM

MDI

XGXS

XGMII

PMA

PCS

XGXS

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Implementation Example

TX C

TX D

R X C

R X DPHY

MAC RS 36

36

XAUIXGMII

XG

X

S

MDI

XG XSP

C

S

P

M

A

P

M

D

Big ChipLittle

Chip

TransceiverForm Factor varies

from daughter card

to small-fo rm-factor

Management

MDC

MD IOManagement

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XGMII 1/4

eXtended Gigabit Media Independent Interface

Tx: 32 data bits, 4 control bits (one per byte), one clock Rx: 32 data bits, 4 control bits (one per byte), one clock

Dual Data Rate (DDR) signaling, with data and controldriven and sampled on both rising and falling clock edges

Control bit per byte:u Allows use of embedded delimiters rather than discrete signals

u Allows interface to be scaled in speed and width

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XGMII 2/4

Control bit (C) is 1 for delimiter and special characters

Control bit (C) is 0 for normal data characters

Delimiter and special character set includes:u

IDLE: Signaled in the absence of data and IPGu SOP: One byte duration at start of packet

u EOP: One byte duration at end of packet

u ERROR: Signaled upon received error or when an error needs to

be forced into the transmit signal

Delimiters and special characters are distinguished by thevalue of the 8 bit data bundle when the correspondingcontrol bit is 1

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XGMII 3/4

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XGMII 4/4

XGMII can be scaled in speed and widthu 32 data bits, 4 control bits

u 16 data bits, 2 control bits

u 8 data bits, 1 control bit

Stub Series Terminated Logic for 2.5 Voltsu SSTL_ 2

u EIA/ JEDEC Standard EIA/ JESD8- 9

u Class I (8 ma) output buffers

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XAUI/XGXS

XAUI: 10 Gigabit eXtended Attachment Unit Interface

XGXS: XGMII eXtender Sublayer

Based on original Hari proposals

CDR-based, 4 lane serial, self-timed interface 3.125 Gbaud, 8B/10B encoded over 20 FR-4 PCB traces

PHY and Protocol independent scalable architecture

Convenient implementation partition

May be implemented in CMOS, BiCMOS, SiGe Direct mapping of Reconciliation Sublayer to/from PCS

Both XGMII and XAUI/XGXS are optionalu Neither, either or both may be implemented

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XAUI/XGXS Applications

Increased XGMII reach

Low pin count interface = implementation flexibility

Ease link design with multiple jitter domains

Lower power consumption re: XGMII Common transceiver module interface

u Enables small form factor transceivers

PCS/PMA agent for MultiChannel PHYsu Agent to WWDM, Parallel Optics

u Avoids excessive penalties for all other PHYs

Self-timed interface eliminates high-speed interface clocks

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XAUI/XGXS Highlights

Increased reachu XGMII is ~3 (~7 cm)

u XAUI is ~20 (~50 cm)

n

Equalization may further increase distance

Lower connection countu XGMII is 74 wires (2 sets of 32 data, 4 control & 1 clock)

u XAUI is 16 wires (2 sets of 4 differential pairs)

Better jitter controlu XGMII does not attenuate jitter

u XAUI self-timed interface enables excellent jitter control at PCS

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10G Link Architecture/Jitter Budget

XGXS

EnDec

SerDes

PCS

P M A

P M D

.35 .65 Independent .35 .65 (UI)

Jitter Budget 1 Jitter Budget 2 Jitter Budget 3

Medium Jitter Budget is independent of XAUI Requires XGXS functionality at both XAUI link ends

XAUI/XGXS simplifies 10 GbE link development

MediumXAUI XAUI

XGXS

EnDec

SerDes

Local

Device

Remote

Device

SerDes1

SerD

es1

EnD

ec2

EnD

ec2

EnD

ec2

SerD

es2

EnD

ec2

SerD

es2

T P2 T P 3T P 3TP 4 TP 1 TP 3T P 2 TP 4 TP 1

TP 2T P 1T P 4

1 Optional XGXS retiming functionality 2 Optional PCS/PMA

PCS

P M A

P M D

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XAUI/XGXS Benefits

MACRS

XGXS

XAUI

0.25 micronCMOS feasible

to 20

FR-4 PCB

Low power

SerDes

Low pin count

System Layout

Flexibility

Multi-Protocol

Commonality

10 GbE

10 GFC

InfiniBand

OIF

Scalability

Self-Timed

Independent

Jitter budget

PCS/PMA

Integration

Into MAC

PMD

Independence

Sali

Inside

X

GX

S

MDI

PC

S

PM

A

PM

D

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XGXS Functions

Use 8B/10B transmission code

Perform column striping across 4 independent serial lanesu Identified as lane 0, lane 1, lane 2, lane 3

Perform XAUI lane and interface (link) synchronization

Idle pattern adequate for link initialization

Perform lane-to-lane deskew

Perform clock tolerance compensation

Provide robust packet delimiters

Perform error control to prevent error propagation

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Data Mapping Example

Lane 0 K R S dp d d --- d d d df A K R K

Lane 1 K R dp dp d d --- d d df T A K R K

Lane 2 K R dp dp d d --- d d df K A K R K

Lane 3 K R dp ds d d --- d d df K A K R K

XGXS Encoded Data

XGMII

D I I S dp d d --- d d d df I I I I

D I I dp dp d d --- d d df T I I I I

D I I dp dp d d --- d d df I I I I I

D I I dp ds d d --- d d df I I I I I

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Basic Code Groups

Similar to GbEu No even/odd alignment, new Skip and Align

/A/ K28.3 (Align) - Lane deskew via code-group alignment

/K/ K28.5 (Sync) - Synchronization, EOP Padding

/R/ K28.0 (Skip) - Clock tolerance compensation

/S/ K27.7 (Start) - Start-of-Packet (SOP), Lane 0 ID

/T/ K29.7 (Terminate) - End-of-Packet (EOP)

/E/ K30.7 (Error) - Signaled upon detection of error

/d/ Dxx.y (data) - Packet data

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Extra Code Groups

The following are included in related proposals:

/Kb/ K28.1 (Busy Sync) - Synchronization/Rate control

/Rb/ K23.7 (Busy Skip) - Clock tolerance comp/Rate control

/O/ K28.2 (FCOS) - Fibre Channel Ordered Set

The following remaining 8B/10B special code-groups areare not used:

K28.4, K28.6, K28.7*

* (Be careful not to follow /K28.7/ with /K28.x/, /D3.x/, /D11.x/, /D12.x/,/D19.x/, /D20.x/, or /D28.x/, as a comma is generated across the boundaries of

the two adjacent code-groups and may result in false code-group alignment)

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XGXS Idle Encoding

Idle is conveyed by the repeating sequence:

AKRKRKRKRKRKRKRKAKRKR....

on each of 4 XAUI lanes

/A/ used to deskew and align XAUI lanes at receiver /K/ contains a comma. The alternating sequence KRKRcontains both running disparity versions of comma

(comma+, comma-).

/R/ is disparity neutral enabling insertion/removal withoutaffecting lane running disparity.

/A/, /K/ and /R/ hamming distance is 3

Latest Idle proposal effectively scrambles /A/K/R/ stream

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Synchronization

XAUI 4-lane link synchronization is a 5 step process1-4 acquire sync on all 4 lanes individually

5 align/deskew synchronized lanes

Loss of sync on any lane results in XAUI link loss-of-sync Lane sync acquisition similar to 1000BASE-X PCS

u Employ hysteresis to preclude false sync and loss-of-sync due to bit

errors

u Hot-sync not an appropriate implementation technique

u Periodic Align (/A/-column) check a good link health check

XAUI Link Sync is fast, straightforward and reliable

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XAUI/XGXS Deskew

Skew is imparted by active and passive link elements

Deskew process accounts for all skew present at the receiver

Lane deskew performed by alignment to deskew pattern present inIdle stream: Align code-groups in all lanes

/A/ columns are issued a minimum of 16 columns apart

40 UI deskew pattern needs to be 80 bits. Idle is 160 bits.

Skew Source # Skew Total Skew

SerDes Tx 1 1 UI 1 UI

PCB 2 1 UI 2 UI

Medium 1

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XGXS Deskew

Lane 3 K R K A K R K R K R K R




Skewed data at receiver input. Skew ~18 bits





Deskew lanes by lining up Align code-groups

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Clock Tolerance Compensation

The XGXS provides jitter and noise isolation by retiming orattenuating jitter by the use of a high quality repeater

Retiming is optional, but may help control jitter

Idle pattern Skip (/R/) columns may be inserted/removed toadjust for clock tolerance differences due to retimingu Skip columns may be inserted anywhere in Idle stream

u Proper disparity Skip required in each Lane

u Any Skip column may be removed

Clock tolerance for 1518 byte packet @ 100 ppm is 0.76UI/laneu A few bytes of elasticity buffering is sufficient to wait for many

frames in case a Skip column is not available for removal

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Skip Column Insert Example

Lane 0 K R S dp d d --- d d d df A K R K

Lane 1 K R dp dp d d --- d d df T A K R K

Lane 2 K R dp dp d d --- d d df K A K R K

Lane 3 K R dp ds d d --- d d df K A K R K

Lane 0 K R S dp d d --- d d d df A R K R

Lane 1 K R dp dp d d --- d d df T A R K R

Lane 2 K R dp dp d d --- d d df K A R K R

Lane 3 K R dp ds d d --- d d df K A R K R

Skip column inserted here

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XAUI/ XGXS Error Control

Packets with detected errors must be abortedu 8B/10B code violation detection may be propagated forward

u IPG special code-groups stop error propagation (e.g. /A/, /K/, /R/)

Rule: Signal Error code upon detected error or in columncontaining EOP if the error is detected during the IPG.Error signaling is a lane function since disparity is checked

per lane.

XGXS checks received packets for proper formationu

Rules TBD, should be PHY/Protocol independent 8B/10B code violation functionality may be used for link

integrity testing

u May be used in conjunction with loopback modes

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XAUI Electrical

Electrical interface is based on low swing ACcoupled differential interface

AC coupling is required at receiver inputs

Link compliance point is at the receiver Transmitter may use equalization as long as

receiver specifications are not exceeded

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XAUI Rx/Tx & Interconnect

Transmitter Parameter Value

Vo Dif(max) 800 mv

Vo Dif(min) 500 mv

Voh AC

Vol ACInput nominal 6.5 ma

Differential Skew(max) 15 ps

Receiver Parameter Value

Vin Dif(max) 1000 mv

Vin Dif(min) 175 mv

Loss 50 9.1 dB

Differential Skew(max) 75 ps

Interconnect Parameter Value

Tr/Tf Min, 20%-80% 60 ps1

Tr/Tf Max, 20%-80% 131 ps1

PCB Impedance 100 10

Connector Impedance 100 30

Source Impedance 100 20

Load Termination 100 20

Return Loss 10 dB2

1. Optional if t ransmitter meets the receiver

ji tter and eye mask with golden PCB

2. SerDes inputs must meet the return loss

from 100 MHz to 2.5 GHz (0.8 x 3.125

Gbaud)

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XAUI Loss Budget

Item Loss

Connector Loss 1 dB

Next + Fext Loss 0.75 dB

PCB Loss 7.35 dB

Loss Budget 9.1 dB

PCB Condition 1 Normal Worst

MSTL Loss Max (dB/in) 0.32 0.43

Max Distance (in) 23 17.1

PCB Condition 2 Normal Worst

STL Loss Max (dB/in) 0.41 0.55

Max Distance (in) 18 13.4

Normal PCB was assumed with loss tangent of 0.22,

worst case it was assumed high temperature and

humidity 85/ 85. Better grade of FR4 may reduce the

loss by as much as 50%.

HP test measurement for 20" line showed 5.2 dB loss or

0.26dB/ in based on the eye loss, the loss assumed here

is very conservative.

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XAUI Jitter

Jitter Compliance Point Tx1 Rx

Deterministic Jitter 0.17 UI 0.41 UI

Total Jitter 0.35 UI2 0.65 UI

1-sigma RJ @ max DJ for 10-12BER3 4.11 ps 5.49 ps

1-sigma RJ @ max DJ for 10-12BER3 3.92 ps 5.23 ps

1. Tx point is for reference. Rx point is for compliance.

2. The SerDes component should have better jitter performance than specified

here to allow for system noise.

3. 1-Sigma value listed here are at maximum DJ, if the DJ value is smaller then

the 1-Sigma RJ may increase to the total jitter value.

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XAUI/XGXS Summary

PHY and Protocol independent scalable architecture

XAUI/XGXS provide PHY, Protocol & Application independence

Common interface/rules for 10 GbE LAN PHY and UniPHY, 10Gigabit Fibre Channel & InfiniBand

Based on generic 10 Gbps chip-to-chip interconnect architecture

Architecture resembles simple and familiar 1000BASE-X PHY

Low complexity, low latency, quick synchronizing reliableinterface

Enabler for early 10 GbE PHYs

May be integrated into MAC/RS ASIC, eliminating XGMII

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PCS, PMA & PMD Sublayers

PHYSICAL

DATA LINK

NETWORK

TRANSPORT

SESSION

PRESENTATION

APPLICATION

OSI

REFERENCE

MODEL

LAYERS

Reconciliation

MAC


LLC

XAUI

LAN

LAYERS

HIGHER LAYERS









PMD

MEDIUM

MDI

XGXS

XGMII

PMA

PCS

XGXS

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PHY Guts

OK, weve got 10 Gbps of data lined up at the end

of these PCB traces. Now how do we get it into

that little piece of glass?

Enter the 3 Sublayers: Physical Coding Sublayer (PCS)

Physical Medium Attachment (PMA)

Physical Medium Dependent (PMD)

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Proposed LAN PMDs

Serial @ 10.3125 Gbaud @ 1300/1550 & 850 nmu 100 m using uncooled 1300 nm FP over standard MMF

u 300 m using 850 nm VCSELs with enhanced MMF

u 2 km using uncooled unisolated 1300 nm FP over SMF

u 10 km using uncooled 1300 nm DFB over SMF

u 40 km using cooled 1300/1550 nm DFB over SMF

Parallel proposalsu Parallel Optics (including fibers) @ 850nm

u 4 x 3.125 Gbps WDM @ 1300 nm (WWDM) over MMF or SMF

Multilevel Analog Signaling (MAS) using PAM5

Leading Proposals indicated in Red

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1300/1550 nm Serial PMD

Directly modulated uncooled DFB laser for typicalLAN distances

Single mode fiber, 1 m to 40 km

10.3125 Gbps line rate with 64B/66B PCS Optical Transceiver components from current

production may be adapted to 10 GbE LAN

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Wide WDM (WWDM)

4 x 3.125 Gbaud eases transmission and jitterspecifications

1300 nm DFB single interface supports:u

300 m of installed or new 62.5 MMF and 50 MMFu 10 km of SMF

WWDM's large channel spacing enables low costoptical demultiplexers

Larger number of lower speed devices than Serial Requires lasers having separated wavelengths;

adding complexity to the specification

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Serial LAN PHY Proposal

The following slides describe one leading proposalin front of the IEEE 802.3ae Task Force.

This proposal includes includes PCS, PMA and

PMD elements and supports all interfaces to theMAC and is the basis of the UniPHY proposal.

Tutorial time does not permit full descriptions ofall PHY proposals in front of the Task Force.

u See http://grouper.ieee.org/groups/802/3/ae/index.htmlfor all proposals presented to date.

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Serial LAN PHY Block Diagram

8B/10BCDR

(XGXS)

8B/10BCDR

(XGXS)

O/E

(PMD)

O/E

(PMD)SerDes

(PMA)

SerDes

(PMA)

XAUI 64B/66BCoding

(PCS)

64B/66BCoding

(PCS)(PCBTraces)

MDI

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Serial PCS

Physical Coding Sublayer (PCS)

Supports 10 Gbps data transport + high efficiency coding

Directly maps XAUI/XGXS data to/from PMA

Performs 64B/66B Encoding/Decodingu DC-balanced, high transition-density, quick-sync code

u Frame and IPG control delineation preserved

u Supports clock tolerance compensation functionality

66-bit word PMA Service Interface defined (PCS nn PMA)

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XAUI/XGXS-to-PCS Mapping

Lane 0 K R S dp d d --- d d d df A K R K R

Lane 1 K R dp dp d d --- d d df T A K R K R

Lane 2 K R dp dp d d --- d d df K A K R K R

Lane 3 K R dp ds d d --- d d df K A K R K R

XAUI/XGXS columns partitioned into 64B/66B sub-frames

d d d d d d d dd d d d d d d d10 1--- 0

78 dp dp dp dp dp dp ds1E K K K K R R R R01 01

64B/66B sub-frames in serial transmission order

1E A A A A K K K KD2 d df df df df K K01 01

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Why 64B/66B?

Provide full 10.000 Gb/s bandwidth for LAN applicationsu No flow-control necessary for LAN applications

u Extends LAN to 40 km+ applications

Interface directly to XAUI with control code transparencyu Allows interoperability with other common backplane coding schemes

(Fibre Channel, InfiniBand as well as XAUI)

Ensure robust DC-balance, transition density, and framesynchronization properties suitable for optical transmissionu Two-bit preamble allows frame synchronization AND sets maximum

degenerate run length at 66 bits (

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Building 64B/66B Frames

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64B/66B Code Overview

Data Codewords have 01 sync preamble

Mixed Data/Control frames are identified with a "10" syncpreamble. Both the coded 56-bit payload and TYPE field

are scrambled

00,11 preambles are considered code errors and cause thepacket to be invalidated by forcing error (E) symbols on

the output

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64B/66B Code Summary

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Serial PMA


Directly maps PCS data to/from PMD

Translates PCS 66B sub-frames to/from a PMD serial bitstream

1-bit PMD Service Interface defined (PMA nn PMD) Intra-PMA physical interfaces not specified (i.e. may be 16b,

4b, etc.)

Serializer, Deserializer and Clock/Data Recovery unit

specified PCS clocks Tx data to PMA, PMA clocks Rx data to PCSu PMA based reference clock provides PCS/PMA master clock

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Implementation Example

XGXS RxCDR

DESERIALIZE

ALIGN

SYNC

DESKEW

8B/10B DECODE

PCS

64B/66B

FRAME

ENCODE

ELASTIC

BUFFER

Hari Rx

RefCLK

Hari Rx

CLKout

Hari Rx

CLKin

66B Tx

CLKin

66B Tx

CLKin

PMA66B:16B

GEARBOX

16B Tx

CLKin

XGXS Tx

SERIALIZE

8B/10B ENCODE

PCS

SYNC

DECODE

ELASTIC

BUFFER

Hari Tx

CLKin

Hari Tx

CLKin

66B Rx

CLKin

66B Rx

CLKin

PMA66B:16B

GEARBOX

16B Rx

CLKin

16

Tx Data

TCLK

Tx CMU 66B Tx CLK16B Tx CLKHari Rx

CLKin

Tx Path

Rx Path

Hari Rx RefCLK

Rx CMU16B Rx CLK

Hari Tx CLK66B Rx CLK

OIFXAUI

MDIO

MDC

Hari

SysCLK

OIF

SysCLK

(Reqd)

Hari

CLKout

Signal

Detect

Tx

Disable

Loop

Back

DataIn

16

Rx Data

RCLK

MADR5

GPIO 4

DataOut

PMAMUX

VCO

PLL

PMA

DEMUX

CDR

PMDDRIVER

LASER

PMDPIN

PREAMP

AGC

OIF

SysCLK

MDI

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Another Implementation Example

LAN PHY OpticsSerDes

64/66

Encode/Decode

Serializer/

Deserializer

Optical

Transmitter/Receiver

XGMII /XAUI

(Sali/Hari)

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Serial PMD - Five Candidates

1. 300 m., 850 nm, VCSEL, new multimode

2. 2 km, 1310 nm, FP laser, singlemode

3. 10 km, 1310 nm, DFB or VCSEL, singlemode

4. 40 km, 1310 nm, DFB, cooled, singlemode5. 40 km, 1550 nm, DFB, singlemode*

Leading Proposals indicated in Red

* A suitable method of specifying the required cable plant quality is underconsideration.

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Transmit Characteristics

dB303030--SMSR

dBm+2+7+2+2-1.3Avg. launch power

(max)

nm0.050.200.402.75*0.20***RMS Spectral Width

(max)

ps2040404030Trise/Tfall (20%-

80%)

nm1530 to

1560

1300 to

1315

1290 to

1325

1290 to

1330

840 to 860Wavelength (range)

GBd10.3125

+/- 100

ppm

10.3125

+/- 100

ppm

10.3125

+/- 100

ppm

10.3125

+/- 100

ppm

10.3125

+/- 100

ppm

Signaling Speed

(range)

LW laserLW laserLW laserLW laserSW laserTx type

UnitType 5Type 4Type 3Type 2Type 1Description

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Tx Characteristics (contd)


dBm-2+4-4-4-5.5Avg. launch power

(min)

dB66667Extinction Ratio**

(min)

dB/Hz-140-130-130-130-125RIN (max)

dBm-30-30-30-30-30Avg. launch power of

OFF transmitter (max)

*Requires k factor 0.5 max.** Alternate, OMA-like representation is under review

***Under review. Some experimental evidence suggests that a much larger linewidth may

be specified.

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Receive Characteristics

dBTBDTBDTBDTBDTBDVertical eye closurepenalty

dBm-16.25-18.41-11.47-7.44-8.52Stressed receivesensitivity

GHz12.3612.3612.3612.3612.36Receive electrical 3dB upper cutofffrequency (max)

dB1212121212Return loss (min)

dBm-22.84-22.84-14.84-14.84-13.5Receive sensitivity

dBm+2TBD+2+2-1.3Avg. receive power(max)

nm1530 to1560

1295 to1315

1290 to1325

1290 to1330

840 to 860Wavelength (range)

GBd10.3125+/- 100

ppm

10.3125+/- 100

ppm

10.3125+/- 100

ppm

10.3125+/- 100

ppm

10.3125+/- 100

ppm

Signaling speed(range)


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Further Serial PMD Work

Define Jitter specifications

Improve MPN model Consolidate some link types

Validate link model with experiments Study dynamic range vs. sensitivity tradeoffs

Research better ways of specifying cable plantquality

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UniPHY Overview

A Proposal for a PHY architecture suitable forserial transmission on both LAN and WAN

u Operating in a LAN or WAN at a data rate of 10 Gbps

u Upgrade to existing enterprise networks with:

n Minimal cost

n Minimal complexity

n Maximum compatibility with 10/100/1000 Mbps

u Operating in a WAN at a data rate which is compatible

with the payload rate of OC-192c/SDH VC-4-64cn Carry native Ethernet packets over the SONET WAN

infrastructure, which has an installed base with a specific

architecture and specific signaling requirements

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MEDIUM

Physical Medium Dependent (PMD)

Physical Coding Sublayer (PCS)


Reconciliation

Media Access Control (MAC)


Upper Layers

10 Gigabit Ethernet

Reference Model

SerDes

XGMII/XAUI

UniPHY Proposal

64/66 CODEC

SONET Framing

& scramblerWIS}

8B/10B CODEC

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WAN Interface Sublayer (WIS)

Enabled when attached to a WAN

Disabled (bypassed) when attached to a LAN Performs:

u SONET Framingu SONET Overhead processing

u x7 + x6 +1 scrambler

In short, everything you need to adapt the 64/66

Serial LAN PHY to a WAN interface

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UniPHY Benefits

Robust frame delimiters

Robust scrambler Excess code space for special codes

Low complexity encode/decode Commonality between LAN & WAN PHY silicon

PHY doesnt need to know the length of the frame

PHY doesnt need to overwrite Preamble

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UniPHY Block Diagram

8B/10BCDR

(XGXS)

8B/10BCDR

(XGXS)

64B/66BCoding

(PCS)

64B/66BCoding

(PCS)

XAUI

WISWIS MDIO/E

(PMD)

O/E

(PMD)SerDes

(PMA)

SerDes

(PMA)

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UniPHY = LAN PHY + WIS

LAN PHY OpticsSerDesWIS

64/66

Encode/Decode

Serializer/

Deserializer

Optical


WAN

Interface

Sublayer

XGMII /XAUI

(Sali/Hari)

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Integrated UniPHY

LAN PHY Optics+ W I S

SerDes

64/66

Encode/Decode

Serializer/

Deserializer

Optical


WANInterface

Sublayer

XGMII /XAUI

(Sali/Hari)

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Really Integrated UniPHY

LAN PHY Optics+ W I S

+SerDes

64/66

Encode/Decode

Serializer/

Deserializer

Optical


WANInterface

Sublayer

XGMII /XAUI

(Sali/Hari)

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UniPHY Nirvana

OpticsL A N P H Y

+WIS

+SerDes

64/66

Encode/Decode

Serializer/

Deserializer

Optical


WAN

Interface

Sublayer

XGMII /XAUI

(Sali/Hari)

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DWDM Transponder

M

D

ITU DWDM

Optics

L A N P H Y

+WIS

+SerDes

XAUI

(Hari)

Cheap LAN

Optics

To

Router

or Switch

To Photonic

Network

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Switch or Router Using UniPHY

SFF

XCVR

SFF

XCVR

SFF

XCVR

SFF

XCVR

Quad

SerDes

4 x 1 G

XGXS

UniPHY

Nirvana

SFF

XCVR

SFF

XCVR

SFF

XCVR

SFF

XCVR

Quad

SerDes

4 x 1 G

XGXS

UniPHY

Nirvana

Switch Fabric

XAUI

XGMII

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Data and Signal Rate Comparison

LAN PHY 64B/66B UniPHY 64B/66B

MAC Data Rate 10 Gbps 9.29419 Gbps

XGMII Signal Rate 156.25 MHz DDR 156.25 MHz DDR

XGMII Data Rate 10 Gbps 9.29419 Gbps

XAUI Signal Rate 4 x 3.125 GBaud 4 x 3.125 GBaud

XAUI Data Rate 10 Gbps 9.29419 Gbps

Encoded Data Rate 10.3125 GBaud 9.58464 GBaud

Serial Line Rate 10.3125 GBaud 9.95328 GBaud

UniPHY works with all rate adaptation proposals:u Open loop

u Word Hold

u Busy Idle

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UniPHY Benefits

Common interface can be used for both LAN/WAN PHY

Common functions can shared between LAN/WAN PHY

Common optics can be shared between LAN/WAN PHY

LAN PHY advocates get what they want:u Minimal cost

u Minimal complexity

u Maximum compatibility

WAN PHY advocates get what they want:u Compatibility with photonic infrastructure

u Compatibility with OAM&P

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Ethernet Native WAN capability

remote monitor

To provide reliable & maintainable PHY connections overmultiple spans of fibers and media converters in WAN.

802.1D Relay

MACPHY

customer site provider sites

LAN WAN LAN

customer site

fault localization

AU AU AU AU AUAU AU AU AU AU

802.1D Relay

MACPHYAU AU

AU: Attachment Unit

MMF SMF 1.3 WDMSMF 1.5 SMF 1.5 SMF 1.3 MMF

Physical

Media:

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Optical Cross-Connect Application

Router

SW

Mediaconverter

Array

Inter-office fibers

Opticalmatrix

switch

MAC

Reconciliation

XGXS

XGMII

XAUI

XGXSPCS

PMAPMD

MDI

400 x 400

switch

slot-

inunit

slot-

inunit

slot-

inunit

backboard

Media

convertersLAN

Port

MMF, SMF, or WDMMMF

Intra-Office

100 - 300 m

Inter-Office

- 10 km (Local Access)- 120 km (without Amp.)- 500 km (with Optical Amp.)

Inter-office Attachment UnitIntra-office Attachment Unit

Attachment

Unit

Layer Model

Providers Router

Customers SW

Provider

Site

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XGENIE Functionality

802.1D Relay

MAC

PHY AU AU AU AU AUAU AU AU AU AU

802.1D Relay

MAC

PHYAU AU

End-End global

Identifier

Provider A Provider B Provider C

Check

Provider-localIdentifier Insert Check &

removal

Insert

Insert Check &

removal

Insert Check &

removal

Crossconnect-local Identifier

Insert Check &

removal

Insert Check &

removal

SONET

analogy

Path

Line

Section

XC XC

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Why Layer1 Signaling?

MAC

Reconciliation

XGXS

XGMII

XAUI

XGXS

PCSPMAPMD

Layer Model

MDI

400 x 400

switch

slot-

inunit

slot-

inunit

slot-

inunit

backboard

Media

converters

LAN Port

MMF, SMF, or WDMMMF

Notdesirable tou Customize devices other than AU, nor touch Layer 2 and higher.

u Implement buffers in AU beyond the need for clock tolerance.

u Hack client packets, nor overwrite preamble and length field.

Customize

MAC

Touch Layer-2

at Attachment UnitInsert/Hack

packets

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XGENIE Protocol 1/2

Optional Layer 1 signaling by using IPG

packet IPG

No influence on Layer-2 and higher.u XGXS/PCS to RS translates XGENIE data into Idle

Ether packet Ether packetIPG

Replace IDLE with signaling data

Check the signaling data

IPG:

InterPacket Gap

packet Ether packet Ether packet

packet Ether packet Ether packet

another signaling data

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XGENIE Protocol 2/2

On XAUI, Idles may be replaced with Ordered-Sets at mostevery other column.

KKK

K

RRR

R

Sdpdp

dp

dpdpdp

dp

ddd

d

...

...

...

... ddd

d

ddd

d

ddfdf

df

dfTK

K

AAA

A

KKK

K

RRR

R

KKK

K

...

...

...

...RRR

R

RRRR

KKKK

Sdpdpdp

dpdpdpdp

dddd

...

...

...

... dddd

dddd

ddfdfdf

dfTKK

AAAA

KKKK

RRRR

KKKK

...

...

...

...Od1d2d3

XGENIE data inserted into IPG

d1, d2, d3: valid data bytes for signaling

Lane 1Lane 2

Lane 3

Lane 0

Lane 1Lane 2Lane 3

Lane 0

XAUI

XAUI +

XGENIE

Signaling bandwidth Bs > 9.8 Mbps can be expected

Influence on buffer size for clock tolerance is negligible

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Conclusion

10 Gigabit Ethernet is Real

10 Gigabit Ethernet Physical Layer proposals for the LANand WAN are complete and well defined

The schedule is looking more realistic every day

Leveraging of as much technology as possibleu 8B/10B coding, Scrambling, OC-192 optics, Ethernet Management

Interface, InfiniBand, DDR clocking, SSTL-2, etc.

10 GbE will be 100% Ethernet LAN compatible

10 GbE will support SONET directly as well as function asa native MAN/WAN

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Acknowledgements

IEEE 802.3 members who have directly/indirectlycontributed to key 10 GbE PHY proposals

Jonathan Thatcher, World Wide Packets; Brad Booth, Intel; John Ewen, IBM;

Ben Brown, Nortel; Howard Frazier, Cisco; Rick Walker, Agilent;

Don Alderrou, nSerial; Vipul Bhatt, Finisar; Osamu Ishida, NTT;

Richard Dugan, Agilent; Walt Thirion, JatoTech Ventures; Bob Grow, Intel;

Henning Lysdal, Giga; Bill Woodruff, Giga; Schelto van Doorn, Infineon;

Mark Ritter, IBM; Joel Goergen, Lucent; David Cunningham, Agilent;

Paul Kolesar, Lucent; Del Hanson, Agilent; Piers Dawe, Agilent;

Dave Dolfi, Agilent; Brian Lemoff, Agilent; Fred Weniger, Vitesse;

Mike Dudek, Cielo; Jack Jewel, Picolight; Russ Patterson, Picolight;

Shawn Rogers, TI; Shimon Mueller, Sun; Nariman Yousefi, Broadcom;

Steve Haddock;

and the hundreds of others who are playing critical roles in developing the10 GbE Standard

Documents

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