· Table of Contents INTRODUCTION

THE DINI GROUP

LOGIC Emulation Source

User Manual DN7002K10MEG

L O G I C E M U L A T I O N S O U R C E

DN7002K10MEG User Manual Version 1.0

Date of Print February 28, 2011

The Dini Group 7469 Draper Avenue

La Jolla, CA92037 Phone 858.454.3419 • Fax 858.454.1728

[email protected] www.dinigroup.com

mailto:[email protected]

http://www.dinigroup.com/

Copyright Notice and Proprietary Information

Copyright © 2009 The Dini Group. All rights reserved. No part of this copyrighted work may be

reproduced, modified or distributed in any form or by any means, without the prior written permission of

The Dini Group.

Right to Copy Documentation

The Dini Group permits licensee to make copies of the documentation for its internal use only. Each copy

shall include all copyrights, trademarks, disclaimers and proprietary rights notices.

Disclaimer

The Dini Group has made reasonable efforts to ensure that the information in this document is accurate and

complete. However, The Dini Group assumes no liability for errors, or for any incidental, consequential,

indirect, or special damages, including, without limitation, loss of use, loss or alteration of data, delays, or

lost profits or savings, arising from the use of this document or the product which it accompanies.

Table of Contents

INTRODUCTION ..................................................................................................................................................................................................................... 1

1 DN7002K10MEG LOGIC EMULATION KIT .................................................................................................................................................. 1 2 DN7002K10MEG LOGIC EMULATION BOARD FEATURES ............................................................................................................................ 2 3 PACKAGE CONTENTS: ..................................................................................................................................................................................... 3 4 INSPECT THE BOARD ....................................................................................................................................................................................... 4 5 ADDITIONAL INFORMATION ............................................................................................................................................................................ 5

GETTING STARTED .............................................................................................................................................................................................................. 6

1 BEFORE YOU BEGIN ........................................................................................................................................................................................ 6 1.1 Configuring the Programmable Components ......................................................................................................................................................... 6 1.2 Warnings ................................................................................................................................................................................................................. 6

2 INSTALLING THE SOFTWARE ........................................................................................................................................................................... 7 2.1 Exploring the Customer CD .................................................................................................................................................................................... 7 2.2 Installing the USB GUI Driver (Windows XP) ....................................................................................................................................................... 8

3 BOARD SETUP ................................................................................................................................................................................................ 12 3.1 Before Powering Up the Board ............................................................................................................................................................................. 12 3.2 Powering Up the Board ........................................................................................................................................................................................ 12

4 RUNNING THE ONE SHOT TEST.................................................................................................................................................................... 13

INTRODUCTION TO THE SOFTWARE TOOLS ............................................................................................................................................................ 16

1 USB CONTROLLER (GUI) ............................................................................................................................................................................. 16 1.1 System Requirements ............................................................................................................................................................................................. 18 1.2 Getting Started with USBController ..................................................................................................................................................................... 18

1.2.1 Main Window ................................................................................................................................................................................................ 18 1.2.2 Basic Menu Operations ................................................................................................................................................................................. 19

2 AETEST USB APPLICATION (AEUSB_WDM.EXE) ........................................................................................................................................ 19 2.1 Compiling aeusb_wdm.exe .................................................................................................................................................................................... 19

3 AETEST USB APPLICATION ........................................................................................................................................................................ 20 3.1 Functionality ......................................................................................................................................................................................................... 20 3.2 Running AETEST................................................................................................................................................................................................... 21

PROGRAMMING/CONFIGURING THE HARDWARE ................................................................................................................................................. 23

1 INTRODUCTION .............................................................................................................................................................................................. 23 2 PREPARING THE CONFIGURATION FILES ....................................................................................................................................................... 24

2.1 Creating Configuration File “main.txt” ............................................................................................................................................................... 24 2.1.1 Format of “main.txt” ..................................................................................................................................................................................... 25

3 CONFIGURING A STRATIX-III/IV USING “MAIN.TXT” ................................................................................................................................... 27 3.1 Setup ...................................................................................................................................................................................................................... 27 3.2 Configuration MSEL Resistors ............................................................................................................................................................................. 27 3.3 HyperTerminal Setup ............................................................................................................................................................................................ 28 3.4 Configuring the FPGA .......................................................................................................................................................................................... 29

3.4.1 Description of Main Menu Options .............................................................................................................................................................. 30 4 CONFIGURING A STRATIX-III/IV FPGA USING USBCONTROLLER .............................................................................................................. 32

4.1 Setup ...................................................................................................................................................................................................................... 32 4.2 Configuring the FPGA .......................................................................................................................................................................................... 32

5 CONFIGURING A STRATIX-III/IV FPGA USING JTAG .................................................................................................................................. 34 5.1 Setup ...................................................................................................................................................................................................................... 34 5.2 Configuring the FPGA .......................................................................................................................................................................................... 34

6 SETTING UP THE CLOCK FREQUENCIES ........................................................................................................................................................ 36 6.1 Setup ...................................................................................................................................................................................................................... 36 6.2 Configuring the Clock Multipliers using USBController ..................................................................................................................................... 36

6.3 Selecting a Clock Source using USBController ................................................................................................................................................... 38 7 UPDATING THE FIRMWARE............................................................................................................................................................................ 39

7.1 Introduction ........................................................................................................................................................................................................... 39 7.2 Updating the USBController ................................................................................................................................................................................ 40 7.3 Updating the Configuration FPGA (Spartan-3) PROM ....................................................................................................................................... 40

7.3.1 Updating the Configuration FPGA (Spartan-3) PROM using USBController ............................................................................................ 40 7.3.2 Using JTAG cable (Xilinx) ........................................................................................................................................................................... 41 7.3.3 Using AEtest_USB........................................................................................................................................................................................ 43

7.4 MCU Startup Modes ............................................................................................................................................................................................. 45 7.5 Updating MCU Boot Code (EEPROM) ................................................................................................................................................................ 45

7.5.1 Updating MCU Boot Code (EEPROM) using USBController .................................................................................................................... 45 7.5.2 Updating MCU Boot Code (EEPROM) using AETest_USB ...................................................................................................................... 46

7.6 Updating the MCU Firmware (Flash) .................................................................................................................................................................. 47 7.6.1 Updating the MCU Firmware (Flash) using USBController ....................................................................................................................... 47 7.6.2 Updating the MCU Firmware (Flash) using AETest_USB .......................................................................................................................... 48

HARDWARE DESCRIPTION .............................................................................................................................................................................................. 50

1 OVERVIEW ..................................................................................................................................................................................................... 50 2 ALTERA STRATIX-III/IV FPGAS ................................................................................................................................................................... 52

2.1 Summary of Stratix-III device features: ................................................................................................................................................................ 53 3 STRATIX-III/IV FPGA CONFIGURATION ...................................................................................................................................................... 54

3.1 Micro Controller Unit (MCU) .............................................................................................................................................................................. 55 3.1.1 MCU EEPROM Interface ............................................................................................................................................................................. 55 3.1.2 MCU SRAM External ................................................................................................................................................................................... 56 3.1.3 MCU Flash .................................................................................................................................................................................................... 56 3.1.4 MCU USB 2.0 Interface ................................................................................................................................................................................ 57 3.1.5 RS232 Interface ............................................................................................................................................................................................. 57

3.2 Configuration FPGA ............................................................................................................................................................................................. 58 3.2.1 Configuration PROM/FPGA Programming ................................................................................................................................................. 60 3.2.2 Design Notes on the Configuration FPGA ................................................................................................................................................... 61

3.3 CompactFlash ....................................................................................................................................................................................................... 61 3.3.1 CompactFlash Connector .............................................................................................................................................................................. 61 3.3.2 CompactFlash connection to Spartan-3 (Configuration FPGA) .................................................................................................................. 62

3.4 Stratix-III/IV Boundary-Scan (JTAG) Interface ................................................................................................................................................... 63 3.4.1 Stratix-III/IV FPGA JTAG Connector ......................................................................................................................................................... 63 3.4.2 Stratix-III/IV FPGA JTAG connection to Configuration FPGA ................................................................................................................. 64

3.5 Configuration MSEL Resistors ............................................................................................................................................................................. 64 4 CLOCK GENERATION ..................................................................................................................................................................................... 65

4.1 Clock Methodology ............................................................................................................................................................................................... 65 4.2 Stratix-III/IV FPGA Clocking Resources ............................................................................................................................................................. 67 4.3 Clock Multipliers (x3) ........................................................................................................................................................................................... 69

4.3.1 General Clock Multiplier (U32) - CLK_G0 ................................................................................................................................................. 69 4.3.2 Connections between the FPGAs and Clock Multipliers ............................................................................................................................. 73

4.4 Daughter Card (DC) Header Clocks .................................................................................................................................................................... 74 4.4.1 SMA & DC A0 Zero Delay Clock Generator (U1) ...................................................................................................................................... 74 4.4.2 SMA & DC B0 Zero Delay Clock Generator (U4) ...................................................................................................................................... 75 4.4.3 DC A2 & B1 Zero Delay Clock Generator (U37) ........................................................................................................................................ 75 4.4.4 DC B2 & A1 Zero Delay Clock Generator (U38) ........................................................................................................................................ 76 4.4.5 Connection between Daughter Card (DC) Clocks and FPGAs .................................................................................................................... 76 4.4.6 Secondary Daughter Card (DC) Header Clocks ........................................................................................................................................... 78 4.4.7 Connection between FPGAs and the Secondary DC Header Clocks ........................................................................................................... 78

4.5 Main Bus Clock – CLK_MB .................................................................................................................................................................................. 79 4.5.1 Main Bus Clock Circuit ................................................................................................................................................................................ 79 4.5.2 Connection between Main Bus Clock Buffer and the FPGAs ..................................................................................................................... 80

4.6 External SMA Clock Inputs, one per FPGA ......................................................................................................................................................... 80 4.6.1 External SMA Clock Input Circuit (FPGA A) ............................................................................................................................................. 81 4.6.2 Connection between Stratix-III/IV FPGAs and External SMA Connectors ................................................................................................ 81

4.7 External Clock Input - Test Point ......................................................................................................................................................................... 81 4.7.1 External Clock Test Point Circuit ................................................................................................................................................................. 81

5 MEMORY........................................................................................................................................................................................................ 82 5.1 DDR2 SDRAM SODIMMs .................................................................................................................................................................................... 82

5.1.1 DDR2 Termination........................................................................................................................................................................................ 82 5.1.2 VDD Switching Power Supply (P_SODIMM_x) ........................................................................................................................................... 85 5.1.3 VTT Linear Power Supply (P0.9V_VTT_x) ................................................................................................................................................ 85 5.1.4 Serial Presence-Detect EEPROM Operation ................................................................................................................................................ 85 5.1.5 Clocking Connections between Stratix-III/IV FPGAs and DDR2 SDRAM SODIMMs ............................................................................ 86

5.1.6 SODIMM connections to the Stratix-III/IV FPGAs ..................................................................................................................................... 87 5.1.7 DDR2 PCB Trace Lengths ............................................................................................................................................................................ 95

6 LED INDICATORS .......................................................................................................................................................................................... 96 6.1 User LEDs ............................................................................................................................................................................................................. 96 6.2 Configuration DONE LEDs .................................................................................................................................................................................. 97 6.3 Power Supply Status LEDs ................................................................................................................................................................................... 97 6.4 Miscellaneous LEDs .............................................................................................................................................................................................. 98

7 RS232 PORT .................................................................................................................................................................................................. 98 7.1.1 RS232 Circuit Diagram ................................................................................................................................................................................. 99 7.1.2 Connections between FPGAs and RS232 Port ............................................................................................................................................. 99

8 TEMPERATURE SENSORS ............................................................................................................................................................................... 99 8.1.1 Temperature Sensor Circuit ........................................................................................................................................................................ 100 8.1.2 Connection between Stratix-III/IV FPGAs and Temperature Sensors ...................................................................................................... 101

9 MISCELLANEOUS FPGA IO HEADERS ........................................................................................................................................................ 102 9.1.1 FPGA IO Header Circuit ............................................................................................................................................................................. 102 9.1.2 Connections between Stratix-III/IV FPGAs and 10-pin IO Headers ......................................................................................................... 102

10 REMOTE SLAVE SELECTMAP CONFIGURATION ......................................................................................................................................... 103 10.1.1 Slave SelectMAP Mictor Header ................................................................................................................................................................ 103 10.1.2 Slave SelectMAP Mictor connections to the Configuration FPGA ........................................................................................................... 103

11 FPGA INTERCONNECT ................................................................................................................................................................................ 105 11.1 MainBus (MB) ................................................................................................................................................................................................. 105

11.1.1 MainBus (MB) Header ................................................................................................................................................................................ 105 11.2 FPGA-FPGA ................................................................................................................................................................................................... 107

12 POWER MONITORS AND RESET ................................................................................................................................................................... 107 12.1.1 Power Monitor Circuit ................................................................................................................................................................................ 107 12.1.2 Connection between Reset Buffers and FPGAs ......................................................................................................................................... 107

13 POWER DISTRIBUTION ................................................................................................................................................................................. 108 13.1 Stand Alone Operation .................................................................................................................................................................................... 108

13.1.1 External Power Connector .......................................................................................................................................................................... 109 14 DAUGHTER CARD HEADERS ....................................................................................................................................................................... 110

14.1 Daughter Card clocking .................................................................................................................................................................................. 111 14.2 Daughter Card Header Pin Assignments ....................................................................................................................................................... 111

14.2.1 Daughter Card Header Banks ..................................................................................................................................................................... 111 14.2.2 Daughter Card Header to FPGA Interconnect with Stratix-III FPGAs ...................................................................................................... 113 14.2.3 Daughter Card Header to FPGA Interconnect with Stratix-IV FPGAs ..................................................................................................... 114

14.3 Special Pins on the Daughter Card Header ................................................................................................................................................... 115 14.3.1 GCAp/n, and GCBp/n ................................................................................................................................................................................. 115 14.3.2 VCCIO Power Supply .................................................................................................................................................................................... 115 14.3.3 VCCPD Power Supply .................................................................................................................................................................................... 115

14.4 Power and Reset .............................................................................................................................................................................................. 116 14.5 FPGA to Daughter Card Header IO Connections ......................................................................................................................................... 117 14.6 Insertion/Removal of Daughter Card ............................................................................................................................................................. 156 14.7 MEG-Array Specifications .............................................................................................................................................................................. 158

15 MECHANICAL .............................................................................................................................................................................................. 159 15.1 Board Dimensions ........................................................................................................................................................................................... 159 15.2 PCB and Chassis Support ............................................................................................................................................................................... 160 15.3 Standard Daughter Card Size ......................................................................................................................................................................... 161 15.4 Daughter Card Spacing .................................................................................................................................................................................. 161

APPENDIX 163

16 APPENDIX A: QSF FILE .............................................................................................................................................................................. 163 17 USING DAUGHTER CARD CLOCKS (MAIN.TXT) ........................................................................................................................................... 163 18 ORDERING INFORMATION ........................................................................................................................................................................... 164 19 OPTIONAL EQUIPMENT ................................................................................................................................................................................ 164

19.1 Compatible Dini Group Products ................................................................................................................................................................... 164 19.1.1 Memories ..................................................................................................................................................................................................... 164 19.1.2 Daughter Cards ............................................................................................................................................................................................ 165

19.2 Compatible third-party products .................................................................................................................................................................... 166 20 COMPLIANCE DATA ..................................................................................................................................................................................... 167

20.1 Compliance ...................................................................................................................................................................................................... 167 20.1.1 EMI .............................................................................................................................................................................................................. 167

20.2 Environmental ................................................................................................................................................................................................. 167 20.2.1 Temperature ................................................................................................................................................................................................ 167

20.3 Export Control................................................................................................................................................................................................. 167 20.3.1 Lead-Free .................................................................................................................................................................................................... 167 20.3.2 The USA Schedule B number based on the HTS ....................................................................................................................................... 167

20.3.3 Export control classification number ECCN .............................................................................................................................................. 167

List of Figures

Figure 1 - DN7002K10MEG Logic Emulation Board ........................................................................................................................................................................................ 2 Figure 2 - DN7002K10MEG CD ROM Directory Structure ............................................................................................................................................................................ 7 Figure 3 - CompactFlash Directory Listing ......................................................................................................................................................................................................... 27 Figure 4 - MSEL Configuration Resistors (default FPP) ................................................................................................................................................................................... 28 Figure 5 - DN7002K10MEG Logic Emulation Board Block Diagram .......................................................................................................................................................... 51 Figure 6 - MCU EEPROM Interface .................................................................................................................................................................................................................... 56 Figure 7 - MCU SRAM ............................................................................................................................................................................................................................................ 56 Figure 8 - MCU Flash .............................................................................................................................................................................................................................................. 57 Figure 9 - USB Connector ...................................................................................................................................................................................................................................... 57 Figure 10 – MCU/Configuration FPGA Serial Port .......................................................................................................................................................................................... 58 Figure 11 – Configuration PROM/FPGA Programming Header ................................................................................................................................................................... 61 Figure 12 - CompactFlash Connector ................................................................................................................................................................................................................... 62 Figure 13 – Stratix III/IV FPGA JTAG Connector .......................................................................................................................................................................................... 64 Figure 14 - MSEL Configuration Resistors (default FPP) ................................................................................................................................................................................. 64 Figure 15 - Clocking Block Diagram ..................................................................................................................................................................................................................... 66 Figure 16 - Stratix-III/IV FPGA Dedicated Clock Inputs ............................................................................................................................................................................... 69 Figure 17 - Clock Multiplier Circuit ...................................................................................................................................................................................................................... 73 Figure 18 – SMA & DC A0 Zero Delay Clock Generator ................................................................................................................................................................................ 75 Figure 19 – SMA & DC B0 Zero Delay Clock Generator ................................................................................................................................................................................ 75 Figure 20 – DC A2 & B1 Zero Delay Clock Generator .................................................................................................................................................................................... 76 Figure 21 – DC B2 & A1 Zero Delay Clock Generator .................................................................................................................................................................................... 76 Figure 22 – Secondary Daughter Card (DC) Header Clock .............................................................................................................................................................................. 78 Figure 23 – Main Bus Clock Buffer ....................................................................................................................................................................................................................... 80 Figure 24 - Stratix-III/IV FPGA SMA Clock Input Circuit ............................................................................................................................................................................. 81 Figure 25 - External Clock Test Point Circuit ..................................................................................................................................................................................................... 82 Figure 26 - Write Operation Using Parallel ODT and 50Ω Series OCT of the Stratix-III/IV FPGA Device ........................................................................................ 83 Figure 27 - Read Operation from DDR2 SDRAM Memory Using the Parallel OCT Feature of the Stratix-III/IV ............................................................................. 84 Figure 28 - VDD Switching Power Supply (P_SODIMM_A) ......................................................................................................................................................................... 85 Figure 29 - VTT Linear Power Supply (P0.9V_VTT_A) .................................................................................................................................................................................. 85 Figure 30 - LED IndicatorS .................................................................................................................................................................................................................................... 96 Figure 31 – MCU/Configuration FPGA Serial Port .......................................................................................................................................................................................... 99 Figure 32 - Temperature Sensor (FPGA A)....................................................................................................................................................................................................... 100 Figure 33 - Stratix-III/IV FPGA IO Header (FPGA A) ................................................................................................................................................................................ 102 Figure 34 – Slave SelectMAP Mictor Header .................................................................................................................................................................................................... 103 Figure 35 - MainBus Interconnect ....................................................................................................................................................................................................................... 105 Figure 36 - MainBus Header (QSE) .................................................................................................................................................................................................................... 106 Figure 37 - Low Voltage Comparator Circuit .................................................................................................................................................................................................... 107 Figure 38 - ATX Power Supply ............................................................................................................................................................................................................................ 109 Figure 39 - External Power Connection ............................................................................................................................................................................................................. 109 Figure 40 - Daughter Card Header Bank/Pin Assignments ........................................................................................................................................................................... 112 Figure 41 - Daughter Card Header to Stratix-III FPGA Interconnect ......................................................................................................................................................... 113 Figure 42 - Daughter Card Header to Stratix-IV FPGA Interconnect ......................................................................................................................................................... 114 Figure 43 - VCCIO Adjustable Linear Power Supply (x4) .................................................................................................................................................................................. 115 Figure 44 - VCCPD Voltage Select Circuit ........................................................................................................................................................................................................ 116 Figure 45 - Daughter Card Header Power & RESET ...................................................................................................................................................................................... 116

List of Tables

Table 1 - CD ROM Directory Contents ................................................................................................................................................................................................................. 7 Table 2 – Main.txt Command List ......................................................................................................................................................................................................................... 25 Table 3 – Stratix-III/IV Configuration Schemes ................................................................................................................................................................................................ 28 Table 4: HyperTerminal Main Menu Options .................................................................................................................................................................................................... 31 Table 5 - FPGA configuration file size ................................................................................................................................................................................................................. 61 Table 6 - Connection between the CF connector and the Configuration FPGA ......................................................................................................................................... 62 Table 7 – Stratix-III/IV FPGA JTAG connection to Configuration FPGA................................................................................................................................................. 64 Table 8 – Stratix-III/IV Configuration Schemes ................................................................................................................................................................................................ 64 Table 9 - Clock Multiplier Frequency Parameters ............................................................................................................................................................................................... 69 Table 10 - Connections between FPGAs and Clock Multipliers ..................................................................................................................................................................... 73 Table 11 - Connections between Daughter Card Clocks and FPGAs ............................................................................................................................................................ 76 Table 12 - Connections between FPGAs and Secondary DC Header Clocks ............................................................................................................................................... 78 Table 13 - Connection between Main Bus Clock Buffer and FPAGs ............................................................................................................................................................. 80 Table 14 - Connection between Stratix-III/IV FPGAs and External SMA Connectors ............................................................................................................................ 81 Table 15 - DDR2 Termination ............................................................................................................................................................................................................................... 84 Table 16 - Serial Presence-Detect EEPROM Connections .............................................................................................................................................................................. 86 Table 17 – Clocking Connections between Stratix-III/IV FPGAs and the DDR2 SDRAM SODIMMs ............................................................................................... 87 Table 18 - Connections between the Stratix-III/IV /IV FPGAs and the SODIMMs ................................................................................................................................ 87 Table 19 – DDR2 PCB Trace Lengths ................................................................................................................................................................................................................. 95 Table 20 – User LEDs ............................................................................................................................................................................................................................................. 96 Table 21 – FPGA DONE LEDs ........................................................................................................................................................................................................................... 97 Table 22 – Power Supply Status LEDs ................................................................................................................................................................................................................. 97 Table 23 – Miscellaneous LEDs ............................................................................................................................................................................................................................ 98 Table 24 - Connections between FPGAs and the RS232 Port ......................................................................................................................................................................... 99 Table 25 - Connection between Stratix-III/IV FPGAs and Temperature Sensors .................................................................................................................................... 101 Table 26 - Connection between Stratix-III/IV FPGAs and 10-pin IO Headers ........................................................................................................................................ 102 Table 27 – Slave SelectMAP Mictor connections to the Configuration FPGA........................................................................................................................................... 103 Table 28 - Connection between Reset Buffers and FPGAs ............................................................................................................................................................................ 107 Table 29 - Daughter Card Interconnect ............................................................................................................................................................................................................. 110 Table 30 – Daughter Card Reset .......................................................................................................................................................................................................................... 116 Table 31 - FPGA to Daughter Card Header IO Connections ....................................................................................................................................................................... 117

I N T R O D U C T I O N

DN7002K10MEG User Manual www.dinigroup.com 1

Introduction

This User Manual accompanies the DN7002K10MEG Stratix-III/IV Logic Emulation Board. For specific information regarding the Stratix-III/IV parts, please reference the datasheet on the Altera website.

1 DN7002K10MEG LOGIC Emulation Kit

DN7002K10MEG is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype system-on-chip (SOC) logic and memory designs for a fraction of the cost of existing solutions. The DN7002K10MEG is stand-alone or hosted via a USB interface. A single DN7002K10MEG configured with two Altera Stratix-III (EP3SL340) can emulate up to 5 million gates of logic as measured by LSI. This product is pin-compatible with the Stratix-IV, to provide vertical migration. Utilizing the Stratix-IV (EP4SE680) FPGA, the DN7002K10MEG will be able to provide 10.5 million ASIC gates. This ASIC gate estimate does not include the embedded memories and multipliers resident in each FPGA. The DN7002K10MEG achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Altera's Stratix-III/IV FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be populated and each FPGA position can be populated with any available speed grade.

Chapter

1



2 DN7002K10MEG Logic Emulation Board

Features

Figure 1 - DN7002K10MEG Logic Emulation Board

DN7002K10MEG Stratix-III/IV Board features the following:

Altera Stratix-III FPGAs (FF1760), -2, -3, -4 Speed Grade

o EP3SL340 (x2)

or, Altera Stratix-IV FPGAs (FF1760), -2, -3, -4 Speed Grade

o EP4SE530 (x2)

o EP4SE680 (x2)

FPGA to FPGA interconnect, Single-ended and LVDS

o 600MHz Chip-to-Chip

o Source Synchronous Clocking for LVDS

Flexible Clock Resources (see Figure 15)

o FPGA Clock Multipliers - Si5326 (x3)

General Clock Network

LVDS Clock Network



DDR2 Clock Network

o External FPGA Clock (LVDS) Input via SMA‘s (x2)

o External Clock (LVDS) Input via Daughter Card Clock Buffers - SMA‘s (x2)

o Multiple clocks from the Daughter Card Headers (P1, P2, P3, P4, P5, and P6)

o Global Clocks (LVDS) from Stratix-III/IV FPGAs

o Global Clocks (LVDS) from Spartan (Main Bus Clock)

o Clock Test Points

FPGA Configuration (Stratix-III/IV)

o JTAG/Boundary-Scan configuration mode

o Fast Passive Parallel (FPP) using the Spartan Configuration FPGA with CompactFlash or USB

Memory

o DDR2, 512MB (64Meg x 64), 200pin SODIMM (PC2-5300), support up to 4GB (x4)

User LEDs

Onboard Distributed Power Supplies

Daughter Card Headers (x6) Single Ended/LVDS – MEG-Array (400 pin)

Full support for Embedded Logic Analyzers

o SignalTapTM Logic Analyzer

Shared RS232 Port, 10 pin Header

Stand Alone operation, requires an external +12V ATX Power Supply.

3 Package Contents:

Before using the kit or installing the software, be sure to check the contents of the kit and inspect the board to verify that you received all of the items. If any of these items



are missing, contact The Dini Group before you proceed. The DN7002K10MEG Logic Emulation Board kit includes the following:

1GB CompactFlash Card

USB FLASH Memory Card Reader

USB 2.0 Cable

RS232 DB9(F) to IDC Header Cable

RS232 Serial Cable (DB9), 6ft, F/F

Chassis Plate (see paragraph 15.2)

o Standoff M3x37mm (x8)

o Standoff M3x53mm (x12)

o Screw, Machine M3x6mm (x20)

CD ROM containing:

o USB Application Program (usbcontroller.exe)

o Stratix-III/IV Reference Designs (Verilog)

o User Manual (pdf format)

o Schematic (pdf format)

o Component Datasheets (pdf format)

Optional items that support development efforts (not provided):

Altera Quartus-II Software

Altera USB-Blaster Download Cable

DDR2 SODIMMs (Available upon request)

4 Inspect the Board

Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment. Verify that all components are on the board and appear intact.




5 Additional Information

For additional information, please visit http://www.dinigroup.com/. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource Description/URL

User Manual This is the main source of technical information. The manual should contain most of the answers to your questions

Demonstration Videos

MEG-Array Daughter Card header insertion and removal video

Dini Group Web Site

The web page will contain the latest user manual, application notes, FAQ, articles, and any device errata and manual addenda. Please visit and bookmark: http://www.dinigroup.com

Data Book Pages from Stratix-III/IV Databook, which contains device-specific information on Altera device characteristics

E-Mail You may direct questions and feedback to the Dini Group using this e-mail address: [email protected]

Phone Support Call us at 858.454.3419 during the hours of 8:00am to 5:00pm Pacific Time.

FAQ The download section of the web page may contain a document called DN7002K10MEG Frequently Asked Questions (FAQ). This document is periodically updated with information that may not be in the User‘s Manual.



http://www.altera.com/literature/lit-stx3.jsp

G E T T I N G S T A R T E D


Getting Started

Congratulations on your purchase of the DN7002K10MEG Stratix-III/IV Logic Emulation Board. The remainder of this chapter describes how to start using the DN7002K10MEG Logic Emulation Board.

1 Before You Begin

1.1 Configuring the Programmable Components

The DN7002K10MEG has been factory tested and pre-programmed to ensure correct operation. The user does not need to alter any jumpers or program anything to see the board work.

1.2 Warnings

Daughter Card Test Headers (Over Voltage) - The 400-pin daughter card test headers are NOT 5V tolerant. These signals connect directly with the FPGA IO. Take care when handling the board to avoid touching the components and daughter card connections due to ESD.

Mechanical Stress – Two board stiffeners are provided to reduce mechanical stress; however, inserting and removing Daughter Cards may add additional stress that could cause board failures.

ESD Warning - The board is sensitive to static electricity, so treat the PCB accordingly. The target markets for this product are engineers that are familiar with FPGAs and circuit boards. However, if needed, the following web page has an excellent tutorial on the ―Fundamentals of ESD‖ for those of you who are new to ESD sensitive products:

http://www.esda.org/basics/part1.cfm

Chapter

2

http://www.esda.org/basics/part1.cfm



Operating Temperature - Avoid touching the PTH012050WAZ power supply modules (PSU1 and PSU3) as they operate at high temperatures and may cause skin burns.

2 Installing the Software

For complete information regarding the USB Graphical User Interface (GUI) and installation instructions, see the ―USB Controller Manual‖ available from The Dini Group website.

2.1 Exploring the Customer CD

The DN7002K10MEG CD ROM contains the following items (the CD ROM does not auto-install on the customer machine), see Figure 2:

<installation directory>

Config_Section_Code

Datasheets

DNMEG_Intercon_Daughtercard

DNMEG_Observation_Daughtercard

Documentation

FPGA_Reference_Designs

Schematics

USB_Software_Applications

Figure 2 - DN7002K10MEG CD ROM Directory Structure

A description of the CD ROM directory contents is listed in Table 1. Please visit The Dini Group website for the most recent revision of these documents.

Table 1 - CD ROM Directory Contents

CD ROM Directory Contents

Directory Name Description of Contents

Config_Section_Code Configuration source code, not intended to

http://www.dinigroup.com/downloads.php


http://www.dinigroup.com/DN7006k10PCIe8T.php

http://www.dinigroup.com/DN7006k10PCIe8T.php



be used by the customer.

Datasheets Datasheets for all the components used on the board.

DNMEG_Intercon_Daughtercard The DNMEG_Intercon is a daughter card that bridges the expansion signals between two 400-pin MEG-Array connectors.

DNMEG_Observation_Daughtercard The DNMEG_Obs Observation Daughter card is a complete solution for observation of signals on the 400-pin MEG-Array connector.

Documentation Contains this document and other project related documentation.

FPGA_Reference_Designs Contains the source and compiled programming files for the DN7002K10MEG reference designs.

Schematics A PDF version of the board schematic, and a text netlist that contains all nets on the board that connect to user IO on any FPGA.

USB_Software_Applications Source and binary files for USB Controller applications.

2.2 Installing the USB GUI Driver (Windows XP)

When the DN7002K10MEG powers on, and you connect it to a USB port for the first time, the pop-up window will ask you to install a driver. The driver installation instructions for Windows XP system are shown below:

Select ―No, not this time‖ to search for software.



Select ―Install from a list or specific location (Advanced)‖ and click ―Next‖ to continue.

Select ―Don‘t search. I will choose the driver to install‖ and click ―Next‖ to continue.



Select ―Have Disk…‖ and direct the browse window to location ―..\USB_Software_Applications\driver\windows_wdm‖ on the CD ROM.

A new window will display the list of compatible hardware, click ―Next‖ to continue.



The Windows software will then install the driver assigned to the hardware.

After successful installation of the driver the following window will be displayed.



3 Board Setup

The instructions in this section explain how to install the DN7002K10MEG Logic Emulation Board. For the purpose of this demonstration, the DN7002K10MEG will be configured in Stand-Alone mode.

3.1 Before Powering Up the Board

Before powering up the board, prepare the board as follows:

1. Attach an ATX Power Supply to the ―ATX PWR‖ header (J6) on the DN7002K10MEG Logic Emulation board.

2. Connect the USB Cable from the host computer to the USB Connector (J18). Ensure the USB Controller driver has been installed.

3. If the kit contains Memory SODIMMs, populate the SODIMM sockets (J1 and J2) with the required modules. Do not insert the SODIMM module with the board powered.

3.2 Powering Up the Board

Power up the board by turning ON the ATX power supply and verify the ―ATX PWR OK‖ LED (DS1) is ON indicating the presence of +12V (located at the top left of the PCB).



4 Running the One SHOT Test

The Dini Group provides a USB Controller application on the CD ROM (..\USB_Software_Applications\USBController\USBController.exe).

1. Open ―USBController.exe‖ and verify that the board was correctly identified as a ―DN7002K10MEG‖ in the log window.

2. Click on ―Production Tests‖ button and select the ―One Shot Test‖ option. Configure the ―One Shot Test‖ as follows (ensure that the path to the bitfiles are correct):



3. The FPGAs will now be configured and the ―One Shot Test‖ will test the following functions of the board, see transaction Log for more details:

Clock Readback

RS232 Test

DDR Tests

Single Ended Interconnect

FAST Single Ended Interconnect

LVDS Interconnect



Review the ―Scroll Log‖ on the ―USBController‖ and verify that the ―One Shot Test‖ passed.

4. Successful testing of the DN7002K10MEG results in the following message being displayed:

I N T R O D U C T I O N T O T H E S O F T W A R E T O O L S


Introduction to the

Software Tools

This chapter introduces the software tools that are shipped with the DN7002K10MEG Logic Emulation Board.

1 USB Controller (GUI)

The ―USBController‖ is a powerful software application for interfacing between USB-Enabled Dini Group products and a host system. It allows the user to program the board‘s FPGAs, access global memory registers, read and program clocks, run tests, and more. ―USBController‖ can be used to run various production tests on the boards to ensure that they are working properly. It can also be used for setting up board features, i.e. when running a custom design. All ―USBController‖ source code is included on the CD-ROM shipped with the DN7002K10MEG Logic Emulation Kit.

The ―USBController‖ application contains the following functionality:

FPGA Configuration

o Configure via USB (individually)

o Configure via USB using file

o Configure via Media Card

o Clear all FPGAs

o Reconfigure all FPGAs via USB

o Configure Daughter Card over SM Mictor

o Reset

Chapter

3



FPGA Reference Design

o Single Ended Interconnect Test

o Read FPGA Clock Frequencies

Mainbus

o Write and Read DWORDs

o Test Address Space

o Read Address Space to File

o Write File to Address Space

o Send Command File

Settings/Info

o FPGA Stuffing Information

o BOARD/SPARTAN/MCU Information

o Read FPGA Temperatures

o Read FAN TACH Frequencies

o Change Text Color

o Force Memory Menu Display

o Toggle Sanity Check

o Turn ON Massive Storage Device

o Hide Board Image

o Set Clock Frequencies

o DN7002K10MEG EXT Clock MUX Setting

Production Tests

o Test DDR

o One Shot Test



Service

o Program/Update Spartan

o Verify Flash is Blank

1.1 System Requirements

―USB Controller‖ can be installed on a Windows 2000/XP system with USB 2.0 capability.

1.2 Getting Started with USBController

The ―USBController.exe‖ program does not require an installer. Simply copy the executable to a suitable location on the host machine and run it (It is not recommended to run the software directly off the CD ROM). The device driver must be installed, as described in chapter 2, and the DN7002K10MEG should be powered ON and the USB cable plugged in. The ―USBController‖ application should immediately detect the DN7002K10MEG. If ―USBController‖ does not detect the DN7002K10MEG, the user will get the following alert:

1.2.1 Main Window

If the USB cable was connected between the DN7002K10MEG and the HOST PC, power turned ON, the ―USBController‖ software will correctly identify DN7002K10MEG and the following screen will be displayed:



1.2.2 Basic Menu Operations

Please refer to the ―USB Controller Manual‖ on the CD ROM for a complete description of all the ―USBController‖ functions.

2 AETEST USB Application (aeusb_wdm.exe)

The command line USB controller program (aeusb_wdm.exe) provides a subset of the features available on ―USBController‖ and is cross platform compatible. This program is a convenient place to start if the user is going to develop a custom IO controller for the DN7002K10MEG Logic Emulation Board.

2.1 Compiling aeusb_wdm.exe

―aeusb_wdm.exe‖ can be compiled using Microsoft Visual Studio 6 or later, or on any version of Linux that supports the usbdevfs library. A make file is provided, un-comment one of the following lines to define which operating system. In Windows, run nmake.

# set target operating system, define ONE of the following

DESTOS = WIN_WDM

#DESTOS = LINUX

#DESTOS = SOLARIS



3 AETEST USB Application

AETEST utility program can test and verify the functionality of the DN7002K10MEG Logic Emulation board, and provide data transfer to and from the user design. All AETEST source code is included on the CD-ROM shipped with your DN7002K10MEG Logic Emulation kit. AETEST USB can be installed on a variety of operating systems, including:

Windows 2000/XP/Vista (Windows WDM)

Linux

3.1 Functionality

All communication to the board using this program is over USB. In this way, the basic functionality of USB is tested. The AETEST utility program contains the following tests:

USB Menu

o Display Device Descriptor

o Display Interface/Endpoint Descriptors

o Display Pipes Info

o Enable USB to FPGA Communication

o Enable USB Mass Storage Mode

o Disable USB Mass Storage Mode

MainBus Menu

o MainBus Write DWORD

o MainBus Read DWORD

o MainBus Write/Read DWORD

o MainBus Fill

o MainBus Display

o MainBus Test

FPGA Configuration Menu



o Display Flash Version

o Check FPGA configuration status

o Configure FPGA via smartmedia

o Configure FPGA individually via USB

o Configure FPGA from configuration file

o Set PowerPC RS232 Multiplexing

o Clear all FPGAs

o Read PowerPC RS232 Multiplexing

o Soft Reset (User Reset)

o Toggle Sanity Check

Change Current Device

3.2 Running AETEST

Open the AETEST application, file location (CD ROM:\ USB_Software_Applications\aetest_usb\aeusb_wdm.exe). The following images show a terminal session in Windows XP.

The initial display of AETEST shows the results of the USB enumeration.



The AETEST USB main menu is displayed below. Use this software for debugging or communicating with the board.

P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E


Programming/Configuring

the Hardware

This chapter details the programming and configuration instructions for the DN7002K10MEG Logic Emulation Board.

1 Introduction

The Dini Group developed the CompactFlash Configuration Environment to address the need for a space-efficient, pre-engineered, high-density configuration solution for systems with single or multiple FPGAs. The technology is a groundbreaking in-system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high-capacity FPGA systems.

This section of the User Manual presents different methods to configure the Stratix-III/IV FPGAs starting with the most popular:

Preparing the Configuration Files – format of the ―main.txt‖ file.

Configuring a Stratix-III/IV FPGA using “main.txt” – using ―main.txt‖ file and CompactFlash Media Card.

Configuring a Stratix-III/IV FPGA using USBController – using the USB Graphical User Interface (GUI).

Configuring a Stratix-III/IV FPGA using JTAG – using the Altera ―USB-Blaster Cable‖ and JTAG.

Setting Up the Clock Frequencies – selecting the clock sources and setting the operating frequencies.

Chapter

4



Updating the Firmware – details the steps required to update the firmware.

The Stratix-III/IV devices are configured by loading application-specific configuration data—the bitstream—into internal memory. On the DN7002K10MEG this can be accomplished via the CompactFlash, or USB interface using Fast Passive parallel (FPP) configuration option. Because Altera FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes (the following are supported on this board):

Fast Passive Parallel (FPP)

Fast Passive Parallel (FPP) with design security feature and/or decompression enabled

JTAG/Boundary-Scan configuration mode

Remote Slave SelectMAP (parallel) configuration mode (x8), using the Mictor interface – used to configure daughter cards using selectMAP

The JTAG/Boundary-Scan configuration interface is always available, regardless of the Mode pin settings. The JTAG/Boundary-Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces. Certain configuration pins are dedicated to configuration, while others are dual-purpose, see datasheet. Dual-purpose pins serve both as configuration pins and as user I/O after configuration. Dedicated configuration pins retain their function after configuration. The remainder of this chapter describes the functional blocks that entail the FPGA configuration environment.

2 Preparing the Configuration Files

Using the CompactFlash card is the preferred method to configure the FPGAs. To control which bit file on the CompactFlash card is used to configure which FPGA, a file named ―main.txt‖ must be created and copied to the root directory of the CompactFlash card. The configuration process from the CompactFlash card cannot be performed without this file.

2.1 Creating Configuration File “main.txt”

The ―main.txt‖ interface is used to control/program the following features on the DN7002K10MEG Logic Emulation Board:

Basic Features

o Configure FPGAs



o Setup Clock Frequencies and MUX Settings

o RS232 Monitor (Verbose Level)

Advanced Features

o MainBus Read/Write Transactions

o Configuration Register Read/Write Transactions

Below is an example of a ―main.txt‖ file, a description of the options that can be set, and the format this file needs to follow.

2.1.1 Format of “main.txt”

The ―main.txt‖ file contains a list of commands, separated by newline characters. A list of valid ―main.txt‖ commands is given below:

Note: Configuring the on-board registers for selecting external Daughter Card Clocks using the above mentioned procedure have not been implemented, see Appendix 17.

Table 2 describes the function of each of the available ―main.txt‖ commands:

Table 2 – Main.txt Command List

Instruction Function

// <comment> Comments are allowed with the following rules:

All comments must start at the beginning of the line

All comments must begin with //

If a comment spans multiple lines, then each line should start with //

Commented lines will be ignored during configuration, and are only for the user’s purpose.

SANITY CHECK: <y/n> If <y/n> is set to y, then the MCU will examine the headers in the .bit files on the CompactFlash card before using them to configure each FPGA. If

//<comment> SANITY CHECK: <y/n> VERBOSE LEVEL: <level> FPGA A:<filename> FPGA B:<filename> CLOCK FREQUENCY: <clock> <number> [MHz] CLOCK FREQUENCY: <clock> <number> [MHz] CLOCK FREQUENCY: <clock> <number> [MHz] DCLK: DC2 100MHZ MAIN BUS: 0x<DWORDADDR> 0x<DWORDDATA> MEMORY MAPPED: 0x<WORDADDR> 0x<BYTE>




the target FPGA annotated in the .bit file header is not the same type as the FPGA the MCU detects on the board, it will reject the file and flash the error LED.

Before this command is executed, <y/n> is set to the default value y.

If you want to encrypt or compress your bitfiles, you will need to set <y/n> to n.

VERBOSE LEVEL: <level> During the configuration process, there are three different verbose levels that can be selected for the serial port messages:

Level 0:

o Fatal error messages

o Bit file errors (e.g., bit file was created for the wrong part, bit file was created with wrong version of Xilinx tools, or bitgen options are set incorrectly)

o Initializing message will appear before configuration

o A single message will appear once the FPGA is configured

Level 1:

o All messages that Level 0 displays

o Displays configuration type (should be SelectMAP)

o Displays current FPGA being configured if the configuration type is set to SelectMAP

o Displays a message at the completion of configuration for each FPGA configured.

Level 2:

o All messages that Level 1 displays

o Options that are found in “main.txt”

o Bit file names for each FPGA as entered in main.txt

o Maker ID, device ID, and size of Smart Media card

o All files found on Smart Media card

o If sanity check is chosen, the bit file attributes will be displayed (part, package, date, and time of the bit file)

During configuration, a “.” will be printed out after each block (16 KB) has successfully been transferred from the Smart Media to the current FPGA

FPGA A:<filename.rbf> For each FPGA the user would like to configure, there must be one line e.g. FPGA “A” will be configured with the file named by <filename.rbf>

CLOCK FREQUENCY: <clock> <number>MHz

The MCU will adjust the clock multiplier producing clock < clock > to the frequency <number>. Valid clock names are G0, G1, and G2

DCLK: DC<dc source> [<n>Mhz] For valid combinations, please see the diagram in par 4.4 Daughter Card (DC) Header Clocks of this document.

MEMORY MAPPED: 0x<WORDADDR> 0x<BYTE>

Writes to a configuration Register. This command can be used to access features that do not have a main.txt command. Example applications include setting clock sources, setting the EXT0 or EXT1 clock buffers to zero-delay mode, or setting the clocks to frequencies lower than 31Mhz.




MAIN BUS 0x<DWORDADDR> 0x<DWORDDATA>

Writes data in <DWORDDATA> to the address on the main bus interface at <DWORDADDR>. This command only makes sense in the context of the Dini Group reference design, unless your design implements a compatible controller on the main bus pins. The Specification for this interface is in the MainBus section.

3 Configuring a Stratix-III/IV using “main.txt”

This section lists detailed instructions for programming the Altera Stratix-III/IV FPGAs using ―main.txt‖. Before configuring the FPGAs, ensure that the FPGA bitfiles and ―main.txt‖ have been copied to the root directory of the CompactFlash card, see Figure 3 .

Figure 3 - CompactFlash Directory Listing

3.1 Setup

Before configuring the FPGA, ensure the following steps have been completed:


2. Connect the ―RS232 Cable‖ to the ―RS232 MCU‖ header (J7) on the DN7002K10MEG (this is not required but allows the user to observe the configuration process).

3.2 Configuration MSEL Resistors

Fast Passive Parallel (FPP) is the default configuration mode for DN7002K10MEG. The configuration mode is selected by setting the appropriate level on the dedicated Mode input pins MSEL[2:0] on the FPGAs.



Figure 4 - MSEL Configuration Resistors (default FPP)

Select the configuration scheme by driving the Stratix-III/IV device MSEL pins either HIGH or LOW as shown in Table 8.

Table 3 – Stratix-III/IV Configuration Schemes

Configuration Mode MSEL[2:0] Configuration Resistors

Fast Passive Parallel (FPP) – Factory Default

000 R575, R564, R565 Installed

FPP with design Security feature and/or decompression enabled


JTAG Do not leave MSEL pins floating.

R575, R564, R565 Installed

3.3 HyperTerminal Setup

Connect the RS232 Serial cable to a COM port on the Host Computer and configure HyperTerminal to the following settings:

1. Connect the ―RS232 Serial Cable‖ to the ―RS232 MCU‖ header (J7) on the DN7002K10MEG Logic Emulation board

R590 (DNI-100R)

FPGA_MSEL1

Silkscreen: "CFG MODE"

R564 0RR575 1K

FPGA_MSEL0

FPGA_MSEL2R565 0R

P2.5VD



3.4 Configuring the FPGA

To configure the Stratix-III/IV FPGAs, perform the following steps:

1. Insert the CompactFlash card into the CompactFlash socket (J14).

2. Open a HyperTerminal Window on the Host Computer.

3. Power up the board by turning ON the ATX power supply and verify the ―ATX PWR OK‖ LED (DS1) is ON indicating the presence of +12V (located at the top left of the PCB).

4. Monitor the configuration process in the HyperTerminal window.



5. After successful configuration process the ―Main Menu‖ will be displayed.

The HyperTerminal interface gives the user an easy method for handling and monitoring the DN7002K10MEG configuration.

3.4.1 Description of Main Menu Options

Table 4 describes the Main Menu options found on the MCU HyperTerminal interface.



Table 4: HyperTerminal Main Menu Options

Option Function Description

1 Configure FPGAs Using ―main.txt‖

The FPGAs will be configured using Fast Passive Parallel (FPP).

2 Interactive configuration menu

This option takes you to a menu titled ―Interactive Configuration Menu‖ and allows the FPGAs to be configured through a set of menu options instead of using the main.txt file.

3 Check Configuration Status

This option checks the status of the DONE pin and prints out whether or not the FPGAs have been configured along with the file name that was used for configuration.

4 Change MAIN configuration file

By default, the processor uses the file main.txt to get the name of the bit file to be used for configuration as well as options for the configuration process. However, a user can put several files that follow the format for main.txt on the CompactFlash card that contain different options for the configuration process. By selecting the main menu option 4, the user can select a file from a list of files that can be used in place of main.txt. If the power is turned off or the reset button (S2) is pressed, the configuration file is changed back to the default, main.txt.

5 List files on Memory Card

This option prints out a list of all the files found on the CompactFlash card.

6 Display Memory Card TXT File

This option allows the user to list the contents of any text file on the CompactFlash card.

7 Change RS232 PPC Ports

This option is not implemented.

The next 5 options are only available if the FPGAs are configured with The Dini Group reference design.

g Display FPGA Temperatures

Displays the current Stratix-III/IV FPGA temperatures.

h Set FPGA Temperature Alarm Threshold

Allows the user to change the temperature threshold. If the FPGA temperature exceeds the threshold, the FPGA will be cleared.

i Read Temperature Sensor Reg

Allows the use to read the temperature sensor registers directly.

j Write Temperature Sensor Reg

Allows the use to write the temperature sensor registers directly.

k Disconnect/Reconnect USB

Disconnect and then reconnects USB to the MCU.



4 Configuring a Stratix-III/IV FPGA using

USBController

This section lists detailed instructions for programming the Altera Stratix-III/IV FPGAs using the USBController software (available on the CD-ROM). Before configuring the FPGAs, ensure that the USBController and the USB driver software are installed on the host computer.

4.1 Setup



2. Connect the ―USB Cable‖ to the ―USB‖ header (J18) on the DN7002K10MEG Logic Emulation board.




1. Open ―USBController‖ and verify that the board was correctly identified as a ―DN7002K10MEG‖ in the log window.

Note: This User Manual will not be updated for every revision of the USBController software, so please be aware of minor differences.



2. Click ―FPGA Configuration‖ followed by ―Configure via USB (individually)‖ and select the FPGA that needs to be configured (this feature can also be invoked by ―right-clicking‖ on an FPGA in the board image).

3. Specify the file location for the FPGA programming file ―xxxx.rbf‖



5 Configuring a Stratix-III/IV FPGA using JTAG

This section lists detailed instructions for programming the Altera Stratix-III/IV FPGAs using Altera QUARTUS-II, Version 9.0 tools. Before configuring the FPGAs, ensure that the QUARTUS-II software and the USB-Blaster driver software are installed on the host computer. Note: The Configuration FPGA (Spartan) must be configured in order to drive the FPGA "nCE signals.

5.1 Setup



2. Connect the ―USB-Blaster Cable‖ to the ―JTAG Stratix-III/IV‖ header (J19) on the DN7002K10MEG Logic Emulation board.




Note: This User Manual will not be updated for every revision of the Altera QUARTUS-II tools, so please be aware of minor differences.



1. Open QUARTUS-II software and click the ―Programmer‖ button. The QUARTUS-II Programmer window appears. Ensure the ―USB-Blaster‖ is shown in the ―Hardware Setup‖ menu and the ―Mode‖ is set to ―JTAG‖.

2. Click ―Auto Detect‖, QUARTUS-II will identify the devices in the JTAG chain. The first device is FPGA A, then FPGA B.

3. Select the FPGA to be configured and click ―Change File‖. Specify the file location for the FPGA programming ―xxxx.sof‖.

4. Enable the ―Program/Configure‖ option and click ―Start‖ to configure the FPGA. A Process Dialog box will indicate programming progress.



5. Verify that the ―CFG DONE‖ blue LED (DS34 for FPGA A) is enabled, indicating successful configuration of the FPGA.

6 Setting Up the Clock Frequencies

This section lists detailed instructions for programming and configuring the clock sources on the DN7002K10MEG Logic Emulation Board. Before configuring the clocks, ensure that the USBController and the USB driver software are installed on the host computer.

6.1 Setup

Before configuring the clock sources, ensure the following steps have been completed:




6.2 Configuring the Clock Multipliers using USBController

To configure the clock multipliers, perform the following steps:

Note: This User Manual will not be updated for every revision of the USBController software, so please be aware of minor differences.




2. Click ―Settings/Info‖ followed by ―Setup Clock Frequencies‖, and select the clock source that needs to be configured. See par 4.2 Stratix-III/IV FPGA Clocking Resources for more information on clock sources.

3. Enter the desired clock output frequency (in MHZ)



4. Ensure the clock was set to 100 MHz in the GUI log window.

6.3 Selecting a Clock Source using USBController

To select an external source to drive a global clock multiplier, perform the following steps:


2. Click ―Settings/Info‖ followed by ―DN7002K10MEG EXT Global Clock Muxes Setting‖, and select the clock source. See par 4.2 Stratix-III/IV FPGA Clocking Resources for more information on clock sources.



3. Ensure the clock source was set in the GUI log window

7 Updating the Firmware

7.1 Introduction

The Dini Group may release periodic software updates as a result of bug fixes or added features.

The following parts of the design may be updated (recommended update sequence):

Configuration FPGA (Spartan-3) PROM – used to configure the Spartan-3 FPGA.

MCU EEPROM - used to load boot code into the MCU.

MCU Flash – used to store MCU firmware code.

Please contact The Dini Group at [email protected] for software updates. It is recommended to update all the devices for a given release of firmware since the software is not tested for backwards compatibility.




7.2 Updating the USBController

The USBController software is available from The Dini Group website under ―downloads‖.

7.3 Updating the Configuration FPGA (Spartan-3) PROM

The Configuration FPGA (Spartan-3) PROM code can be updated by using one of the following three methods, listed in order of preference:

USBController

JTAG Cable (Xilinx)

AETEST_USB

7.3.1 Updating the Configuration FPGA (Spartan-3) PROM using USBController

This section lists detailed instructions for programming the Xilinx Spartan-3 Configuration FPGA using the USBController software.



3. Open ―USBController.ini‖ and add the line ―service_mode=1‖. Save and close the file. This file is located in the same folder as USBController.exe- and for this reason USBController.exe cannot be run directly off of the CDROM for this operation. If USBController.ini does not exist, create it as a blank text file and add the required text.

4. Launch USBController, select ―Service‖ menu and ―Program/Update Spartan‖. A warning message will appear to ensure that you want to update Spartan. Select ―Yes‖ button.

Note: This update is dependent on USBController and FLASH firmware version. Please verify with [email protected] to make sure that your version of MCU code and USBController supports this option and request a *.xsvf file.





5. Specify the PROM file location (CUST_CD:\Config_Section_Code\ ConfigFPGA\DN7002K10MEG\). Open the PROM file ―prom_flp.xsvf‖ and select ―Debug Level 0‖ and wait for the PROM to be programmed.

6. The process takes about 10-15 minutes, do not interrupt the process to avoid corrupt files. The progress bar is on the bottom of USBController window.

7. The ―USBController‖ window will indicate the completion status, power cycle the board after successful execution.

7.3.2 Using JTAG cable (Xilinx)

This section lists detailed instructions for programming the Xilinx Spartan-3 Configuration FPGA using the Xilinx ISE Version 10.1.03 tools.

1. Connect the ―Xilinx Platform Cable USB‖ to the ―JTAG PROM/SPARTAN‖ header (J20) on the DN7002K10MEG Logic Emulation Board.


3. Open iMPACT and create a new default project. Select ―Configure devices using Boundary-Scan (JTAG)‖ from the iMPACT welcome menu.

Note: This User Manual will not be updated for every revision of the Xilinx tools, so please be aware of minor differences.



4. iMPACT will identify the devices in the JTAG chain.

Specify the file location for the PROM programming file, (CUST_CD :\Config_Section_Code\ConfigFPGA\DN7002k10MEG\) and open the PROM file ―prom_flp.mcs‖.

5. Click ―OK‖ on the ―Device Programming Properties‖ window to proceed.

6. Right-click on the XC18V04 device and select ―Program‖. Click ―OK‖ to program the PROM. A Process Dialog box will indicate programming progress.

Note: The FPGA (XC3S1000) will be high-lighted in the JTAG chain, select Bypass since we intend to configure the FPGA with the PROM.



7. Power-cycle the DN7002K10MEG and verify that the ―CFG DONE‖ blue LED (DS33) is enabled, indicating successful configuration of the FPGA.

7.3.3 Using AEtest_USB

If Xilinx tools are not available, use the following instructions to update the Spartan-3 PROM firmware. This update is dependent on AEtest_USB and Flash firmware version. Please confirm with [email protected] to make sure that your current version (MCU version, AEtest_USB) supports this option and request *.xsvf file from Dini Group.

1. Run ―aeusb_wdm.exe‖ (or ―aeusb_linux‖), from file location (CUST_CD:\USB_Software_Applications\aetest_usb) and press any key to continue.




2. Select option 3 ―FPGA Configuration Menu‖.

3. In the ―ASIC Emulator Flash Boot Menu‖, please select option ‗9‘ (Note: the menu option is not displayed for security purposes).

4. Select ―y‖ and enter the full path filename for the *.xsvf file.

5. Verbose level is ‗0‘. The higher verbose level, the slower the program runs.

6. The progress will go from 0 to 100%. This will take some time to complete (10 minutes). Please do not interrupt the process.

7. When the execution is finished, power cycle the board.

Note: Using the command line: ―aeusb_wdm_cmd.exe XSVF <filename.xsvf>‖ (or ―aeusb_linux_cmd.exe -XSVF <filename.xsvf>‖).



7.4 MCU Startup Modes

The DN7002K10MEG Logic Emulation Board can load its code from two different locations:

MCU EEPROM (Update Mode) – Boot Code

MCU Flash (default mode) - Firmware

7.5 Updating MCU Boot Code (EEPROM)

To protect against accidental erasure, the EEPROM firmware cannot be updated unless the board is put in ―Update Mode‖ during POWER-ON. Either USBController or AEtest_USB can be used to update the EEPROM code.

7.5.1 Updating MCU Boot Code (EEPROM) using USBController


2. Open ―USBController.ini‖ and add the line ―service_mode=1‖. Save and close the file. This file is located in the same folder as USBController.exe, and for this reason USBController.exe cannot be run directly off of the CDROM for this operation. If USBController.ini does not exist, create it as a blank text file and add the required text.

3. Hold down the ―LOG RST‖ switch (S1) during POWER ON; Verify that the MCU LEDs (DS37, DS38, DS39, and DS40) turned ON, indicating the board is in ―Update Mode‖.

4. Launch USBController software; A warning message will appear to ensure that you want to update Flash, select ―No‖.

5. Select ―Service‖ menu and ―Program EEPROM‖. Click ―Ok‖ and specify the EEPROM file location (CUST_CD:\Config_Section_Code\MCU \EEPROM). Open the EEPROM file ―EEPROM_FLP.iic‖ and wait for the EEPROM to be programmed.

6. The ―USBController‖ window will indicate completion status, click ―Ok‖ and power cycle the board.



7.5.2 Updating MCU Boot Code (EEPROM) using AETest_USB


2. Run ―aeusb_wdm.exe‖ (or ―aeusb_linux‖), from file location (CUST_CD:\ USB_Software_Applications\aetest_usb) and press any key to continue.

3. Select option 3 ―Firmware Menu (booted from EEPROM)‖.

4. Select option 1 ―Update EEPROM from <filename>.iic file‖ and enter the name of the file, (CD ROM:\Config_Section_Code\MCU\EEPROM\ EEPROM_FLP.iic). This process should take approximately 2 minutes to execute.




Note: Using the command line: aeusb_wdm_cmd.exe -EEPROM <filename.iic>

7.6 Updating the MCU Firmware (Flash)

To protect against accidental erasure, the MCU (Flash) firmware cannot be updated unless the board is put in ―Update Mode‖ during POWER-ON. Either USBController or AEtest_USB can be used to update the MCU Flash firmware.

7.6.1 Updating the MCU Firmware (Flash) using USBController


2. Open ―USBController.ini‖ and add the line ―service_mode=1‖. Save and close the file. This file is located in the same folder as USBController.exe, and for this reason USBController.exe cannot be run directly off of the CDROM for this operation. If USBController.ini does not exist, create it as a blank text file and add the required text.


4. Open USBController.ini and add this line ―service_mode=1‖, save and close the file.

5. Launch USBController software; A warning message will appear to ensure that you want to update Flash, select ―Yes‖.



6. Specify the Flash file location (CD ROM:\ Config_Section_Code\MCU\ FLASH\firmware.hex). Open the MCU Flash file ―firmware.hex‖ and wait for the MCU Flash to be programmed.

7. The ―USBController‖ window will indicate completion status, power cycle the board.

7.6.2 Updating the MCU Firmware (Flash) using AETest_USB

Hold down the ―LOG RST‖ switch (S1) during POWER ON; Verify that the MCU LEDs (DS37, DS38, DS39, and DS40) turned ON, indicating the board is in ―Update Mode‖.

Run ―aeusb_wdm.exe‖ (or ―aeusb_linux‖), from file location (CUST_CD:\ USB_Software_Applications\aetest_usb) and press any key to continue.

Select option 3 ―Firmware Menu (booted from EEPROM)‖.



4. Select option 2 ―Update Flash from <firmware>.hex file‖ and enter the name of the file, (CD ROM\Config_Section_Code\MCU\FLASH\firmware.hex). This process should take approximately 2 minutes to execute.


Note: Using the command line: ―aeusb_wdm_cmd.exe -Flash <filename.hex>‖ (aeusb_linux_cmd.exe -Flash <filename.hex>‖).

H A R D W A R E D E S C R I P T I O N


Hardware Description

This chapter describes the hardware features of the DN7002K10MEG Stratix-III/IV Logic Emulation Board.

1 Overview

The DN7002K10MEG Logic Emulation Board provides for a comprehensive collection of peripherals to use in creating a system around the Altera Stratix-III/IV FPGAs. A high level block diagram of the DN7002K10MEG Logic Emulation Board is shown in Figure 5, followed by a brief description of each section.

Chapter

5



Figure 5 - DN7002K10MEG Logic Emulation Board Block Diagram

The DN7002K10MEG provides two Altera Stratix-III/IV FPGAs (EP3SL340). The architecture of the board maximizes interconnect by providing a number of dedicated busses between the FPGAs, see block diagram. The FPGAs can be configured via JTAG using the ―Altera USB-Blaster Download Cable‖ or by the Configuration



FPGA (Spartan-3) using the Fast Passive Parallel (FPP) interface via the GUI (USB). The board can also configure a Daughter Card via the Mictor Interface. Numerous clocking options exist to allow the user a flexible clocking scheme. Three highly configurable clock multipliers (Si5326) provide global clock networks. External memory to the FPGAs are realized using a 64 bit, 200 pin SODIMM (PC-5300). Six 400 pin MEG-Array connectors on the bottom of the printed circuit board assembly (PCBA) are used to interface to Dini Group products, e.g. DNMEG_Obs Daughter Card, or to custom daugtercards. The DN7002K10MEG receives power from an external +12V ATX power supply. An RS232 interface exists to allow communication with the application. LEDs are used to indicate configuration status, power supply presence and numerous LEDs are provided for the user.

2 Altera Stratix-III/IV FPGAs

The Stratix- III family provides the most architecturally advanced, high performance, low power FPGAs in the market place. Stratix III FPGAs lower power consumption through Altera‘s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption everywhere else. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry‘s lowest power, high performance FPGAs.

Specifically designed for ease of use and rapid system integration, the Stratix-III FPGA family offers two family variants optimized to meet different application needs:

The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications.

The Stratix III E family is memory and multiplier rich for data-centric applications.

Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high speed I/O. Package and die enhancements with dynamic on-chip termination, output delay and current strength control provide best-in-class signal integrity. Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix-III family is a programmable alternative to custom ASICs and programmable processors for high performance logic, digital signal processing (DSP), and embedded designs and architectures.

Stratix-III/IV devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III/IV devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells.



2.1 Summary of Stratix-III device features:

48,000 to 337,500 equivalent logic elements (LEs)

20,491 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers

High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, 36×36 multipliers (at up to 550 MHz), multiply accumulate functions, and finite impulse response (FIR) filters

I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity

Programmable Power Technology, which minimizes power while maximizing device performance

Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation

Up to 16 global clocks, 88 regional clocks and 116 peripheral clocks per device

Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis and dynamic phase shifting

Memory interface support with dedicated DQS logic on all I/O banks

Support for high-speed external memory interfaces including DDR,DDR2,DDR3 SDRAM, RLDRAM II, QDR II and QDR II+ SRAM on up to 24 modular I/O banks

Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards

Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks

High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.25 Gbps performance

Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSLI, Rapid I/O and NPSI



The only high-density, high-performance FPGA with support for 256-bit (AES) volatile and non-volatile security key to protect designs

Robust on-chip hot socketing and power sequencing support Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support

Built-in error correction coding (ECC) circuitry to detect and correct configuration or user memory error due to SEU events

Nios II embedded processor support

Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPP)

3 Stratix-III/IV FPGA Configuration

The Dini Group developed the CompactFlash Configuration Environment to address the need for a space-efficient, pre-engineered, high-density configuration solution for systems with single or multiple FPGAs. The technology is a groundbreaking in-system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high-capacity FPGA systems.

Stratix-III/IV devices are configured by loading application-specific configuration data—the bitstream—into internal memory. On the DN7002K10MEG this can be accomplished via the CompactFlash or USB interface using Fast Passive parallel (FPP) configuration option. Because Altera FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes (the following are supported on this board):

Fast Passive Parallel (FPP)

Fast Passive Parallel (FPP) with design security feature and/or decompression enabled

JTAG/Boundary-Scan configuration mode

Remote Slave SelectMAP (parallel) configuration mode (x8), using the Mictor interface – used to configure daughter cards using SelectMAP

The JTAG/Boundary-Scan configuration interface is always available, regardless of the Mode pin settings. The JTAG/Boundary-Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces. Certain



configuration pins are dedicated to configuration, while others are dual-purpose, see datasheet. Dual-purpose pins serve both as configuration pins and as user I/O after configuration. Dedicated configuration pins retain their function after configuration. The remainder of this section describes the functional blocks that entail the FPGA configuration environment.

3.1 Micro Controller Unit (MCU)

The Cypress CY7C68013 (U63) micro controller is used to control the configuration process. The MCU contains an enhanced 8051 core, USB 2.0 transceiver and a Serial Interface Engine (SIE). The CY7C68013 provides the following features: 256 bytes of register RAM, three flexible Timers, 2 UARTs, and an integrated I2C compatible controller.

The MCU interfaces to the Configuration FPGA (U25) via a dedicated 8-bit bus [MCU_D8..MCU_D0] and the CompactFlash interfaces to the Configuration FPGA via an additional 8-bit bus [CF_D7..CF_D0]. The two Stratix- III/IV FPGAs on the board interfaces to the Configuration FPGA via an 8-bit bus [SELECTMAP_D7..SELECTMAP_D0] used for Fast Passive Parallel (FPP) configuration scheme. The amount of internal SRAM is not large enough to hold the FAT needed for CompactFlash, so an external 128Kb x 8 SRAM (U61) was added. In addition a 1Mb x 8 Flash (U60) was added to store the downloaded program code. An external EEPROM (X4) configures the MCU during power-up.

The micro controller has the following responsibilities:

Reading the CompactFlash card via the Configuration FPGA

Communicate to the system via the USB Interface

Configuring the Stratix-III/IV FPGAs (x2)

Executing DN7002K10MEG self tests

Drive MCU status LEDs

3.1.1 MCU EEPROM Interface

During the power-up sequence, internal logic checks the I2C-compatible port for the connection of an EEPROM (X4) whose first byte is either 0xC0 or 0xC2. If found, the MCU uses the VID/PID/DID values in the EEPROM in place of the internally stored values of and it boot-loads the EEPROM contents into internal RAM (0xC2). The EEPROM interface is shown in Figure 6.



Figure 6 - MCU EEPROM Interface

3.1.2 MCU SRAM External

Memory expansion for the MCU is provided as 128k x 8 SRAM (U61). Writing to the device is accomplished by taking Chip Enable (SRAM_CS#) and Write Enable (MEM_WR#) inputs low. Reading from the device is accomplished by taking the Chip Enable (SRAM_CS#) and the Output Enable (MEM_OE#) low while forcing Write Enable high. The contents of the memory location specified by the address pins will appear on the IO pins. Address space above 0x1000h is banked through the Configuration FPGA. The SRAM interface is shown in Figure 7.

Figure 7 - MCU SRAM

3.1.3 MCU Flash

Program memory is provided by the 1Mb x 8 Flash (U60). To eliminate bus contention the device has separate Chip Enable (FLASH_CS#), Write Enable (MEM_WR#) and Output Enable (MEM_OE#) controls. Device programming occurs by executing the program command sequence. Address space above 0x1000h is banked through the Configuration FPGA. The Flash interface is shown in Figure 8.

MCU_PROMA1

IIC_SCL_MCUpg7IIC_SDA_MCUpg7

C7092.2uF6.3V20%CER

IIC_SCL_MCU

R4924.7K

MCU_PROMA0

X4

24LC64 SOCKETDIP8

123 5

6

7

8

4

A0A1A2 SDA

SCL

WP

VCC

GND

R5214.7K

5678

4321

RN261K

R5344.7K

MCU_PROM_WPIIC_SDA_MCU

MCU_PROMA2

P3.3VD

MCU_D0

MCU_D5

CFPGA_A15

P3.3VD

Static RAM 128Kb X 8

U61

SOIC127P1176X120-32NCY7C1019CV33-12ZXC

25

11

20

1817

29

16151413

6

528

19

27

4321

21

12

26

243132

30

710

2223

8

9

GND

D3

A11

A9A8

A13

A7A6A5A4

D0

CE1OE

A10

D7

A3A2A1A0

A12

WE

D6

VCCA15A16

A14

D1D2

D4D5

VCC

GND

MCU_D2MCU_D1

MCU_A10

MCU_D4

MCU_D6

CFPGA_A14

MCU_A2

MCU_A8

MEM_WR#

MCU_A7

MCU_A9

MEM_OE#

MCU_A12

MCU_A5

MCU_A0

MCU_A11

MCU_A3

MCU_A1

MCU_D3

CFPGA_A16

MCU_D7MCU_A6

MCU_A4

CFPGA_A13

SRAM_CS#



Figure 8 - MCU Flash

3.1.4 MCU USB 2.0 Interface

Communication with the system is via the USB connector (J18), which interfaces directly with the MCU. The USB interface connector is a type B receptacle as shown in Figure 9.

Figure 9 - USB Connector

3.1.5 RS232 Interface

An RS232 serial port (J5/J7) is provided for low speed communication with the MCU and FPGA logic. The RS-232 standard specifies output voltage levels between –5V to –15V for logical 1 and +5V to +15V for logical 0. Input must be compatible with voltages in the range of -3V to -15V for logical 1 and +3V to +15V for logical 0. This

MEM_OE#

MCU_A6

FLASH_WP#

MCU_A5

MCU_A11

CFPGA_A19

Boot Block FLASH 1Mb X 8

U60

AM29LV800BSOPT50X2000-48N

2524232221201918

87654321

481716

1310

29313335384042443032343639414345

262811

2746

37

12

9

14

15

47

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18

NC/VPPNC

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14

DQ15(A-1)

CEOEWE

GNDGND

VCC

RST

NC

NC/WP

RY/BY/NC

BYTE

MCU_D1

MCU_D4

MCU_D7

MCU_A10

MCU_D2

CFPGA_A13

MCU_A1

CFPGA_A14

MCU_D3

MCU_A8MCU_D6

CFPGA_A15

CFPGA_A18

MCU_A0

FLASH_CS#

MEM_WR#

MCU_A9

MCU_A4

MCU_A2

SYS_RSTn_MCU

MCU_A3

MCU_A12

FLASH_RY/BY#

MCU_D0

MCU_A7

CFPGA_A16CFPGA_A17

P3.3VD

MCU_D5

USB_VBUS

USB_D-

FB33

P3.3VD

+USB_GND

U72

(DNI)SOT23-3N

13

2

CH1VN

VP

USB_D+

R77812.7K+USB_SHLD

R7540R

C10960.1uF

CER

16V20%

C10684.7uF

P3.3VD

J18

67068-1000USB_TYPE_B

1324

56

VBUSD+D-

GND

GND-SHIELDGND-SHIELD

R7778.25K

C10674.7uF

U73

(DNI)SOT23-3N

13

2

CH1VN

VP

USB_VBUS_MCU



ensures data bits are read correctly even at maximum cable lengths between DTE and DCE, specified as 50 feet.

The RS-232 standard has two primary modes of operation, Data Terminal Equipment (DTE) and Data Communication Equipment (DCE). These can be thought of as host or PC for DTE and as peripheral for DCE. The DN7002K10MEG operates in the DCE mode only.

Figure 10 shows the implementation of the serial port on the DN7002K10MEG.

Figure 10 – MCU/Configuration FPGA Serial Port

There are two signals attached to the MCU:

Transmit Data - RS232_MCU_TX

Receive Data - RS232_MCU_RX

TX and RX provide bi-directional transmission of transmit and receive data. No hardware handshaking is supported.

3.2 Configuration FPGA

The Xilinx Spartan-3 XC3S1000 (U25) is needed to handle the counters and state machines associated with the high-speed USB, CompactFlash interface, MainBus communication and FGPA Configuration. The FPGA contains 1M system gates, 432K of BlockRAM and 391 user I/O‘s. Some of the Verilog source code for the Configuration FPGA (ConfigFPGA.v) is proprietary.

The Configuration FPGA interfaces with the following signals (see UCF):

Interface to the Micro Controller

MCU Data Bus: MCU_D[7..0]

MCU Address Signals: MCU_A[15..0]

RS232_FPGA_RX

P2.5VD

RS232_MCU_RX

RS232_CPUMP1+

J7

TSM-105-01-T-DV

1 23 45 67 89 10

P5.0V

+5V_LCD

R304 4.7K

GND

RS232_CPUMP2+

C3980.1uF

C4070.1uF

P2.5VD

FPGA

GND

+12V_LCD

RS232_MCU_TX

R320 5.11R

P2.5VD

RS232_FPGA_RXr R268(DNI)

MCU

RS232_CPUMP2-

R267(DNI)

RS232_MCU_RX

C380 0.1uF

RS232_FPGA_TX

RS232_FPGA_RXD

R311 4.7K

RS232SHDN#

R2914.7K

U56

MAX3388ESOP65P638X110-24N

1

2

45

6

3

789

212019

1312

10

1817

16

11 15

22

24

23

14

C1+

V+

C2+C2-

V-

C1-

T1INT2INT3IN

T1OUTT2OUTT3OUT

R1OUTR2OUT

LOUT

R1INR2IN

LIN

SWOUT SWIN

GND

SHDN

VCC

VL

RS232_FPGA_TX

J5

TSM-105-01-T-DV

1 23 45 67 89 10

RS232_VPUMP-

C404 0.1uF

P12V

RS232_MCU_RXD

RS232_CPUMP1-

RS232_MCU_TXDRS232_FPGA_TXD

C3900.1uF

RS232_VPUMP+



Control Signals: MCU_RDn, MCU_WRn, MCU_CSn, MCU_OEn, MCU_PSENn, MCU_RESETn

GPIF Signals: GPIF_D[7..0], GPIF_RDY[1..0], GPIF_CTL[1..0]

I2C: IIC_SCL_MCU, IIC_SDA_MCU

Interface to the CompactFlash

Data Bus: CF_D[7..0]

Control Signals: CFA[2..0], CF_CD[2..1]#, CF_INTRQ, CF_IORDY, CF_IOCS16#, CF_CS[1..0]#, CF_ATA_SEL#, CF_CSEL#, CF_RESET#, CF_IOWR#, CF_IORD#, CF_WE#, CF_PDIAG#, CF_DASP#, CF_DMACK#, CF_DMARQ#, CF_POWER_ON#

Banked Address to the SRAM/Flash

Upper Address Signals: CFPGA_A[13..19]

FPGA Configuration, SelectMAP Signals

Configuration Clock: FPGA[B..A]_CCLK

Data Bus: SELECTMAP_D[7..0]

Control Signals: FPGA[B..A]_DONE, FPGA[F..A]_NSTATUS, FPGA[B..A]_INIT, FPGA[B..A]_CRC_ERR, FPGA[B..A]_CSn, FPGA[B..A]_PROGn, FPGA_RDWRn, FPGA_RSTn_[B..A], FPGA_MSEL[2..0]

FPGA Configuration, JTAG

JTAG Signals: JTAG_FPGA_TCK, JTAG_FPGA_TDI, JTAG_FPGA_TMS, JTAG_FPGA_TDO_F

SRAM Signals

SRAM_CS#, MEM_OE#

Flash Signals

FLASH_CS#, FLASH_WP#, FLASH_RY/BY#

Clock Multiplier Signals

Control Signals: SYNTH_SCL_ALL, SYNTH_SDA_ALL, SYNTH_RSTn_G[2..0]

Clock MUX Signals

MUX Chip Select: CLKGEN_[B..A][2,0]_CLKSEL

Input Select: CLKGEN_[B..A]_S[0,1,23]

PLL Select: CLKGEN_[B..A][0,2]_PLLSEL

MUX Reset: CLKGEN_[B..A][0,2]_MR

MainBus Signals

Clock Signals: CLK_MB48_FB_P/N



Data Signals: MB_AD[31..0]

Control Signals: MB_AD[32..35] is actually MB_ALE, MB_WR, MB_RD, MB_DONE

LED Indicators

Signals: LED_S_GRN[3..0]#, LEDS_USBACT#, LEDS_CFACT#, LEDS_UND[1..0]#, LED_S_ERR_TEMP#, LED_S_ERR_CONFIG#

FAN Control Signals

FAN_TACH_[B..A]

Mictor Signals

CLK_48_MIC , FPGA_RD/WR#, FPGA_M_DONE, FPGA_M_CCLK, FPGA_M_PROG#, FPGA[15..14]_CS#, MICTOR_CLK_E

TEMP Sensor Signals

TEMP_ALERT#

Reset Signals

Daughter Card Reset: RST_DC_OUTn

Push Button Reset: RST_LOGn

RST_REMOTEn

3.2.1 Configuration PROM/FPGA Programming

The Configuration FPGA (U25) is programmed using Master Serial Mode with a Platform Flash PROM (U29). In Master Serial mode, the Spartan-3 FPGA configures itself. The JTAG chain from the PROM is in a serial daisy chain with the Configuration FPGA, allowing simultaneous JTAG programming option of both devices. The Configuration FPGA is set to Master Serial Mode using discrete resistors (R114, R115, and R691). At power-up, the Configuration FPGA provides a configuration clock (CFPGA_CCLK) that drives the PROM. A short access time after CEn (CFPGA_DONE) and OE (CFPGA_INIT#) are enabled, data is available on the PROM data (CFPGA_D0) pin that is connected to the Configuration FPGA. The programming header (J20) as shown in Figure 11, is used to download the files to the Configuration PROM/FPGA via a ―Xilinx Platform Cable USB‖.



Figure 11 – Configuration PROM/FPGA Programming Header

3.2.2 Design Notes on the Configuration FPGA

Oscillator (X6) is a 24 MHz oscillator used to clock the Configuration FPGA and MCU. This part is soldered down to the PCB and is not intended to be user-configurable. The clock signal is labeled ―CLKM_S‖ on the schematic. The 24 MHz is used directly for the state machines in the Configuration FPGA for controlling the interface to the CompactFlash card. The maximum DCLK clock frequency for Fast Passive Parallel (FPP) configuration is 100 MHz, resulting in a maximum data rate of 200Mbps.

3.3 CompactFlash

The configuration bit file for the FPGAs is copied to a CompactFlash card using the ―3.5 Inch Multi Flash Card Reader‖ supplied as part of the kit. The approximate file size for each possible FPGA option is shown below in Table 5. Note that several BIT files can be put on a 1GB CF card. The DN7002K10MEG is shipped with one 256MB, +3.3V CompactFlash card. The DN7002K10MEG supports card densities up to 1GB.

Table 5 - FPGA configuration file size

Stratix-III/IV /IV Device

Bitstream Length (Mbytes)

EP3SL340 15

EP4SE530 23.5

EP4SE680 29.25

3.3.1 CompactFlash Connector

Figure 12 shows J14, the CompactFlash connector used to download the configuration files to the FPGA.

C17447uF

CER

6.3V20%

C1722.2uF6.3V

PROM_TDO

PROM_TMS

P2.5VD

R7671K

P2.5VD

R7681K

R7691K

PROM_TCK

CFPGA_TDI

R7701KJ20

87832-1420

13579

1113

2468101214

GNDGNDGNDGNDGNDGNDGND

VREFTMSTCKTDOTDINCNC



Figure 12 - CompactFlash Connector

3.3.2 CompactFlash connection to Spartan-3 (Configuration FPGA)

Table 6 shows the connection between the CompactFlash connector and the Configuration FPGA.

Table 6 - Connection between the CF connector and the Configuration FPGA

Signal Name Configuration FPGA Connector

CF_ATA_SEL# U25-P18 J14-9

CF_CD1# U25-N21 J14-26

CF_CD2# U25-R18 J14-25

CF_CS0# U25-N18 J14-7

CF_CS1# U25-P17 J14-32

CF_CSEL# U25-P19 J14-39

CF_D0 U25-Y21 J14-21

CF_D1 U25-Y20 J14-22

CF_D2 U25-Y19 J14-23

CF_D3 U25-W22 J14-2

CF_VS2

CF_D1

CF_D6

R644.7K

CF_D5

R505 (DNI-4.7K)

CF_WE#

CFA2

CF_DMARQ#

(TRUE IDE Pin Name)

-CS0

-CS1

TIE TO VCC

-RESET

-ATA_SEL

-DASP-PDIAG

-DMACKDMARQ

GND

GND

GND

GND

GND

GND

GNDGND

INTRQ

IORDY

-IOCS16

OPT

OPT

OPT

OPT

OPT

OPT

OPT

OPT

J14MI21-50PD-SF-EJRMI21-50PD-SF-EJR_MOD

1

23456

7

8

9

101112

13

14151617181920 21

2223

24

2526

2728293031

32

33

3435

3637

38

39

40

41

42

43444546

474849

50GND

D03D04D05D06D07

CE1

A10

OE

A09A08A07

VCC

A06A05A04A03A02A01A00 D00

D01D02

WP

CD2CD1

D11D12D13D14D15

CE2

VS1

IORDIOWR

WEREADY

VCC

CSEL

VS2

RESET

WAIT

INPACKREGBVD2BVD1

D08D09D10

GND

P3.3VD

C924.7uF

CF_VS1

CF_D4

CF_CS1#

R431 (DNI-4.7K)

CF_CS0#

CF_RESET#

CF_DASP#

CF_IOWR#

CFA0

CF_CD2#

CF_ATA_SEL#

CF_POWER_ON#

CF_DMACK#

CF_INTRQ

CF_D7

P3.3VD

Q11PMV65XP

3

1

2D

G

S

P3.3V_CF

CF_IORD#

CF_D3

CF_D0

CF_D2

CF_CSEL#

CF_CD1#

CF_IOCS16#

R934.7K

CF_IORDY

CFA1

CF_PDIAG#

Note: Do not press down on the top of the CompactFlash connector if a CF card is not installed. The metal case can short +3.3V to GND.




CF_D4 U25-Y22 J14-3

CF_D5 U25-V19 J14-4

CF_D6 U25-W19 J14-5

CF_D7 U25-W21 J14-6

CF_DASP# U25-T19 J14-45

CF_DMACK# U25-T20 J14-44

CF_DMARQ# U25-M21 J14-43

CF_INTRQ U25-T18 J14-37

CF_IOCS16# U25-T21 J14-24

CF_IORD# U25-R19 J14-34

CF_IORDY U25-T22 J14-42

CF_IOWR# U25-P22 J14-35

CF_PDIAG# U25-R22 J14-46

CF_POWER_ON# U25-N17 Q11-1

CF_RESET# U25-P21 J14-41

CF_WE# U25-R21 J14-36

CFA0 U25-N20 J14-20

CFA1 U25-N19 J14-19

CFA2 U25-N22 J14-18

3.4 Stratix-III/IV Boundary-Scan (JTAG) Interface

In boundary-scan mode, dedicated pins are used for configuring the Stratix-III/IV devices. The configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP). The FPGA JTAG interfaces to IO on the Configuration FPGA. This allows manipulation of the data as required by the application and allows the JTAG chain to become an address on the existing bus. The processor can then read from, or write to the address representing the JTAG chain. FPGAs that are not populated require a feed through resistor to maintain the daisy chain connection between FPGAs.

3.4.1 Stratix-III/IV FPGA JTAG Connector

Figure 13 shows J10, the JTAG connector used to download the configuration files to the FPGAs.



Figure 13 – Stratix III/IV FPGA JTAG Connector

3.4.2 Stratix-III/IV FPGA JTAG connection to Configuration FPGA

Table 7 shows the connection between the Stratix-III/IV FPGA JTAG connector and the Configuration FPGA.

Table 7 – Stratix-III/IV FPGA JTAG connection to Configuration FPGA


JTAG_FPGA_TCKr U25.J5 J19.1

JTAG_FPGA_TDIr U25.K6 J19.9

JTAG_FPGA_TDO_B U25.K5 J19.3

JTAG_FPGA_TMS U25.J6 J19.5

3.5 Configuration MSEL Resistors

The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins MSEL[2:0].

Figure 14 - MSEL Configuration Resistors (default FPP)

Select the configuration scheme by driving the Stratix-III/IV device MSEL pins either HIGH or LOW as shown in Table 8.

Table 8 – Stratix-III/IV Configuration Schemes


R80410K

VIO

P2.5VDP2.5VD

JTAG_FPGA_TDO_B

JTAG_FPGA_TDIr

P2.5VD

J19

TSM-105-01-T-DV

12345678910

TCKGNDTDOVCCTMSVIONCNCTDIGND

R80510K

P2.5VD

R779(DNI-0R)

JTAG_FPGA_TMS

JTAG_FPGA_TCK

R8031K

R575 1K

R565 0R

FPGA_MSEL1

FPGA_MSEL0

Silkscreen: "CFG MODE"

R590 (DNI-100R)

R564 0R

P2.5VD

FPGA_MSEL2




Fast Passive Parallel (FPP) 000 R575, R564, R565 Installed

FPP with design Security feature and/or decompression enabled


JTAG Do not leave MSEL pins floating.

R575, R564, R565 Installed

4 Clock Generation

4.1 Clock Methodology

The DN7002K10MEG has a flexible and configurable clocking scheme. Figure 15 is a block diagram showing the clocking resources and connections. All of the ―Global Clock Networks‖ on the DN7002K10MEG are routed point-to-point using dedicated LVDS routes. Since LVDS is a low voltage-swing differential signal, using a single ended input buffer in the FPGA will not work. An example Verilog implementation of a differential clock input is given below:

alt_inbuf_diff #(.io_standard("LVDS")) clkG0_inst (.i(CLK_G0P), .ibar(CLK_G0N), .o(CLK_G0_in));

The pin assignment in the QSF file:

set_location_assignment PIN_AA1 -to CLK_G0_RN

set_location_assignment PIN_AA2 -to CLK_G0_RP

All global clock networks have a differential test point terminated by a 100R resistor used to measure clock frequency. The positive side of the differential signal is connected to pin 1 (square) and the negative side is connected to pin 2 (circular) of the test point.



CL

OC

K

MU

LT

IPL

IER

Si5

326

(QF

N3

6)

11

4.2

85M

Hz

CK

1C

K2

LV

DS

CL

K

BU

FF

ER

ICS

85

408

(TS

SO

P24

)

CL

OC

K

MU

LT

IPL

IER

Si5

326

(QF

N3

6)

11

4.2

85M

Hz

CK

1C

K2

LV

DS

CL

K

BU

FF

ER

ICS

85

408

(TS

SO

P2

4)

CL

OC

K

MU

LT

IPL

IER

Si5

326

(QF

N3

6)

OS

C2

4M

Hz

(50

32

)

11

4.2

85M

Hz

CK

1C

K2

LV

DS

CL

K

BU

FF

ER

SY

89

82

6

(TQ

FP

64)

DD

R2

CL

K x

2

GE

N C

LK

x 2

MB

CL

K x

3L

VD

S C

LK

BU

FF

ER

SY

898

26LH

Y

(TQ

FP

64)

LV

DS

CL

K

GE

NIC

S8

74

5B

(TS

SO

P2

4)

Use

r D

iffe

ren

tia

l

Clo

ck In

pu

t

(SM

A)

6:1

MU

XIC

S8

3056

(TS

SO

P1

6)

DC

CL

K A

0 &

SM

A (

x3

)

FP

GA

(L

VC

MO

S)

x 2

EP

SL

34

0

F1

76

0

R4

R1

R3

R2

L1

L3

L2

L4

T1

T2

B1

B2

8C

8B

8A

7A

7B

7C

3C

3B

3A

4A

4B

4C

6A

6B

6C

5C

5B

5A

1A

1B

1C

2C

2B

2A

CLK13

CLK15

CLK7

CLK5

CLK4

CLK6CLK12

CLK14

CL

K1

CL

K3

CL

K0

CL

K2

CL

K8

CL

K1

0

CL

K9

CL

K1

1

EP

SL

34

0

F1

76

0

R4

R1

R3

R2

L1

L3

L2

L4

T1

T2

B1

B2

8C

8B

8A

7A

7B

7C

3C

3B

3A

4A

4B

4C

6A

6B

6C

5C

5B

5A

1A

1B

1C

2C

2B

2A

CLK13

CLK15

CLK7

CLK5

CLK4

CLK6 CLK12

CLK14C

LK

1

CL

K3

CL

K0

CL

K2

CL

K8

CL

K1

0

CL

K9

CL

K1

1

LV

DS

x 2

Sp

art

an

XC

3

XC

3S

10

00

-

4F

GG

45

6C

CL

K_S

0

TP

TP

TP

OS

C2

4M

Hz

(50

32

)

OS

C2

4M

Hz

(50

32

)

DA

UG

HT

ER

CA

RD

(B

OT

)M

EG

AR

RA

Y –

Re

ce

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

DA

UG

HT

ER

CA

RD

(B

OT

)M

EG

AR

RA

Y –

Re

ce

pta

cle

(4

00

Pin

)

74

39

0-1

01L

F

DA

UG

HT

ER

CA

RD

(B

OT

)M

EG

AR

RA

Y –

Re

ce

pta

cle

(4

00

Pin

)

74

39

0-1

01L

F

LV

DS

CL

K

GE

NIC

S87

45

B

(TS

SO

P24

)

LV

DS

CL

K

GE

NIC

S8

74

5B

(TS

SO

P2

4)

DC

CL

K A

2 &

B1

(x2

)D

C C

LK

B2

& A

1 (

x2

)

DA

UG

HT

ER

CA

RD

(B

OT

)M

EG

AR

RA

Y –

Re

ce

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

DA

UG

HT

ER

CA

RD

(B

OT

)M

EG

AR

RA

Y –

Re

ce

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

DD

R-I

I S

OD

IMM

2G

B (

20

0P

IN)

DD

R-I

I S

OD

IMM

2G

B (

20

0P

IN)

FP

GA

B

LV

DS

CL

K

GE

NIC

S8745

B

(TS

SO

P24)

DC

CL

K B

0 &

SM

A (

x3

)

DA

UG

HT

ER

CA

RD

(B

OT

)M

EG

AR

RA

Y –

Re

ce

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

Use

r D

iffe

ren

tia

l

Clo

ck In

pu

t

(SM

A)

Use

r D

iffe

ren

tia

l

Clo

ck In

pu

t

(SM

A)

Use

r D

iffe

ren

tia

l

Clo

ck In

pu

t

(SM

A)

A0

A1

A2

B2

B1

B0

Main Bus ConnenctorReceptacle (120 Pin)

QSE-060-01-L-D-A

CL

K_

DC

_A

0_

QS

Ep

CL

K_D

C_

B0

_Q

SE

p

CL

K_

MB

48

_Q

SE

n

CL

K_

G2

_Q

SE

n

SO

DIM

M A

SO

DIM

M B

FP

GA

AF

PG

A B

Figure 15 - Clocking Block Diagram



The clocking structures for the DN7002K10MEG include the following features:

Clock Multipliers (x3)

o General Clock Multiplier (U32) - CLK_G0

o DDR2 Clock Multiplier (U7) – CLK_G1

o LVDS Interconnect Clock Multiplier (U17) - CLK_G2

Daughter Card Header Clocks

o EXT SMA & DC A0 Clocks (U1)

o EXT SMA & DC B0 Clocks (U4)

o DC A2 & B1 Clocks (U37)

o DC B2 & A1 Clocks (U38)

Main Bus Clock – CLK_MB48

External SMA Clock Inputs, one per FPGA – CLK_FPGA_x_EXTp/nThe individual clock resources will be further explained in the following paragraphs.

4.2 Stratix-III/IV FPGA Clocking Resources

The dedicated clock inputs on the Stratix-FPGAs are shown in the block diagram in Figure 16.



Si5326CLK_G0_[A..B]p/n

Si5326

Si5326

CLK_M48_[A..B]p/n

CLK_DC_A0_[A..B]p/n

General CLK

Multiplier

DDR2 CLK

Multiplier

LVDS Interconnect

CLK Multiplier

CLK_MB48_P

CLK_MB48_N

CLK_DC_Ap/n

CLK_USER_p/nExternal Differential

Clock Input

DAUGHTER CARD (A0)MEG ARRAY – Receptacle (400 Pin)

74390-101LF

Configuration

FPGA

Spartan-3

CLK_DC_B0_[A..B]p/nCLK_DC_Bp/n

CLK_USER_p/nExternal Differential

Clock Input

DAUGHTER CARD (B0)MEG ARRAY – Receptacle (400 Pin)

74390-101LF

CLK_DC_A2_[A..B]p/nCLK_DC_A2p/n

CLK_USER_B1p/n


74390-101LF

CLK_DC_B2_[A..B]p/nCLK_DC_B2p/n

CLK_USER_A1p/n


74390-101LF


74390-101LF


74390-101LF

CLK_G1_[A..B]p/n

CLK_G2_[A..B]p/n



Figure 16 - Stratix-III/IV FPGA Dedicated Clock Inputs

4.3 Clock Multipliers (x3)

The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface (configured for I2C). The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Please refer to the ―Any-rate Precision Clocks Si5316, Si5322, Si5323, Si5325, Si5326, Si5365, Si5366, Si5367, Si5368 Family Reference Manual‖ from Silicon Laboratories for the Si5326 for programming information.

4.3.1 General Clock Multiplier (U32) - CLK_G0

One of the outputs of the Clock Multiplier (U32) is buffered (U30) and distributed as a general reference clock for the FPGAs while the other output is connected to the ―CKIN2‖ input on the DDR CLK Multiplier (U7). The clock multiplier (U32) can use either oscillator (X6) or the Stratix-III/IV FPGA clock output signals (multiplexed) as a reference input. The clock multiplier (U32) must be programmed via the I2C interface. Signal ―SYNTH_RSTn_G0‖ is provided to reset the clock multiplier.

Provided on the CompactFlash card, is a table giving the command to set a clock to any of a large number of intermediate frequencies, see Table 9. The main.txt syntax is:

Source: G1 1 <a> <b> <c> <d><e>

Where <a>, <b>, <c>, <d> and <e> are arbitrary parameters given in the table. The correct value of the five parameters for selected frequencies is given below.

Table 9 - Clock Multiplier Frequency Parameters

Frequency “a” “b” “c” “d” “e”

# 0.003000 Mhz 7 29393 1599 7 146969

# 0.005000 Mhz 1 969 23 6 96999

# 0.010000 Mhz 1 969 23 6 48499

Note: Three clock multipliers (U32, U17, and U7) are on the I2C chain, driven from the Configuration FPGA (U25).

http://www.silabs.com/



# 0.015734 Mhz 6 44035 2178 3 44035

# 0.024000 Mhz 5 22453 999 5 22453

# 0.032000 Mhz 3 10825 374 3 21651

# 0.032768 Mhz 7 63915 3478 7 13455

# 0.038400 Mhz 4 15787 624 4 15787

# 0.044100 Mhz 7 139971 7618 7 9997

# 0.048000 Mhz 7 9185 499 7 9185

# 0.050000 Mhz 1 969 23 6 9699

# 0.060000 Mhz 3 5773 199 3 11547

# 0.075000 Mhz 2 10777 319 2 10777

# 0.076810 Mhz 5 168383 7498 5 7015

# 0.096000 Mhz 5 5613 249 5 5613

# 0.100000 Mhz 1 969 23 6 4849

# 0.150000 Mhz 0 4041 79 4 4041

# 0.176400 Mhz 3 72667 2516 3 3927

# 0.192000 Mhz 4 3157 124 4 3157

# 0.220000 Mhz 7 1377 74 4 2755

# 0.325000 Mhz 3 13857 479 3 2131

# 0.440000 Mhz 7 1377 74 4 1377

# 0.455000 Mhz 3 13857 479 6 1065

# 0.880000 Mhz 7 1377 74 0 1377

# 1.843199 Mhz 4 15791 624 3 375

# 2.457600 Mhz 4 15791 624 3 281

# 3.276800 Mhz 4 47487 1874 3 211

# 3.579545 Mhz 5 7909 351 2 225

# 3.686399 Mhz 4 15791 624 3 187

# 4.096000 Mhz 7 2303 124 7 107

# 4.194304 Mhz 6 36307 1790 6 115

# 4.433617 Mhz 6 49867 2462 0 273

# 4.915200 Mhz 7 2303 124 7 89



# 6.144000 Mhz 4 631 24 1 157

# 7.372799 Mhz 4 15791 624 3 93

# 8.192000 Mhz 7 2303 124 7 53

# 8.867238 Mhz 1 2153 52 7 49

# 9.216000 Mhz 7 2303 124 7 47

# 9.830400 Mhz 4 15871 624 4 61

# 10.160000 Mhz 2 507 14 6 47

# 10.245000 Mhz 3 23221 799 3 67

# 11.059200 Mhz 7 2303 124 7 39

# 11.228000 Mhz 5 5613 249 5 47

# 11.289600 Mhz 3 3611 124 1 85

# 12.288000 Mhz 7 2303 124 7 35

# 14.318181 Mhz 3 2549 87 6 33

# 14.745599 Mhz 7 2303 124 7 29

# 16.384000 Mhz 4 383 14 6 29

# 16.934400 Mhz 5 14111 624 5 31

# 17.734475 Mhz 0 190485 3735 2 45

# 17.900000 Mhz 0 6085 119 4 33

# 18.432000 Mhz 7 2303 124 7 23

# 19.200000 Mhz 4 383 14 4 31

# 19.440000 Mhz 5 269 11 1 49

# 19.531250 Mhz 1 31249 767 1 49

# 19.660800 Mhz 4 15871 624 0 61

# 22.118400 Mhz 7 2303 124 7 19

# 24.576000 Mhz 7 2303 124 7 17

# 26.562500 Mhz 1 3909 95 0 45

# 32.768000 Mhz 4 383 14 1 29

# 33.330000 Mhz 7 605 31 1 29

# 38.880000 Mhz 5 1133 49 5 13

# 66.660000 Mhz 7 403 19 6 7



# 74.175824 Mhz 7 6749 363 7 5

# 76.800000 Mhz 4 383 14 4 7

# 77.760000 Mhz 5 575 24 4 7

# 98.304000 Mhz 4 383 14 1 9

# 122.880000 Mhz 4 383 14 6 3

# 124.416000 Mhz 5 575 24 6 3

# 133.330000 Mhz 0 26665 479 6 3

# 155.520000 Mhz 5 575 24 4 3

# 156.256000 Mhz 4 9765 374 4 3

# 159.375000 Mhz 1 509 11 4 3

# 160.380000 Mhz 7 485 24 4 3

# 161.130000 Mhz 0 10741 199 4 3

# 161.132800 Mhz 4 50353 1874 4 3

# 164.360000 Mhz 3 1173 39 1 5

# 166.630000 Mhz 0 33325 639 1 5

# 166.667000 Mhz 0 333333 6399 1 5

# 167.331600 Mhz 5 92961 3999 1 5

# 172.640000 Mhz 0 2157 39 1 5

# 173.370000 Mhz 3 11557 399 3 3

# 176.100000 Mhz 3 1173 39 3 3

# 176.840000 Mhz 3 8841 299 3 3

# 184.320000 Mhz 4 671 24 3 3

# 195.312500 Mhz 3 6249 191 3 3

# 311.010000 Mhz 3 2961 99 4 1

Figure 17 shows one of the clock multiplier circuits. LED (DS30) is used to indicate ―PLL Loss of Lock‖.



Figure 17 - Clock Multiplier Circuit

4.3.2 Connections between the FPGAs and Clock Multipliers

All of the ―Global Clock Networks‖ on the DN7002K10MEG are routed point-to-point using dedicated LVDS routes. The arrival times of the clock edges at each FPGA are phase-aligned (length-matched on the PCB) within about 100ps. These clocks are all suitable for synchronous communication among FPGAs. The connections between the FPGAs and the Clock Multipliers are shown in Table 10.

Table 10 - Connections between FPGAs and Clock Multipliers

Signal Name Clock Multiplier Pin FPGA Pin

General Clock Multiplier (CLK_G0)

CLK_G0_AN U30-11 U9-AA1

CLK_G0_AP U30-12 U9-AA2

CLK_G0_BN U30-9 U10-AB1

CLK_G0_BP U30-10 U10-AB2

CLK_G0_TN U30-13 TP57-2

CLK_G0_TP U30-14 TP57-1

DDR2 Clock Multiplier (CLK_G1)

CLK_G1_AN U6-11 U9-A21

CLK_G1_AP U6-12 U9-B21

CLK_G1_BN U6-9 U10-BB22

CLK_G1_BP U6-10 U10-BA22

SYNTH_A1_G0

CLKG0r

C1

68

0.1

uF

C158 0.1uF CLK_FPGA_INTr

C153 0.1uF

C171 (DNI)

SYNTH_LOL_G0r

R608 4.7K

R605 4.7K

SYNTH_DEC_G0

DS30RED

___LVCMOS

Rate0-Rate1 X[A:B] ref

L M 38.88Mhz

M M 114.285Mhz

H H DataSheet

CMODE0 -> I2C mode

1 -> SPI mode

I2C address1101A[2]A[1]A[0]

U32Si5326QFN50P600X600X90-37N

1

2

3

4

5

6 7

89

10

11

1213

14

15

1617

18

1920

21

2223

242526

27

2829

30

31

32

33

3435

36

37

RSTn

NC

INT_C1B

C2B

VDD

XA

XB

GN

D

NC

VDD

RATE0

CKIN2+CKIN2-

NC

RATE1

CKIN1+CKIN1-

LOL

DECINC

CS_CA

SCLSDA_SDO

A0A1A2_SSn

SDI

CKOUT1+CKOUT1-

NC

GN

D

VDD

NC

CKOUT2-CKOUT2+

CMODE

GN

D P

AD

SYNTH_SCL_ALLpg5

SYNTH_A2_G0

CLK_G0p1

C140 0.1uF

SYNTH_SDA_ALLpg5

CLK_G0n1

R607 4.7KP2.5_G0

SYNTH_LOL_G0

SYNTH_XA_G0

R640 4.7K

C147 0.1uF

C1

56

4.7

uF

CLK_FPGA_INTrn

FB10

R100 4.7K

R700 4.7K

C1

61

0.1

uF

P2.5VD

CLKG0

SYNTH_SDI_G0

SYNTH_CS_G0

R721 (DNI)

R606 4.7K

SYNTH_RATE0_G0

SYNTH_A0_G0

P2.5VD

SYNTH_INC_G0

R720 (DNI) SILK: G0 LOL

CLK_G0p2

SYNTH_XB_G0

SYNTH_CMODE_G0

SYNTH_RSTn_G0pg5

SYNTH_RATE1_G0

R1014.7K

R597453R

C1

57

0.1

uF

R111 (DNI)

IIC ADDR: 1101 000

C170 (DNI)

CLKG0rn

X7

114.285000MhzOSC_TXC_7MA1400014

12 34

XTAL_AGND XTAL_BGND

CLK_G0n2

R701 (DNI)

R675 100R



Signal Name Clock Multiplier Pin FPGA Pin

CLK_G1_TN U6-13 TP36-2

CLK_G1_TP U6-14 TP36-1

LVDS Clock Multiplier (CLK_G2)

CLK_G2_AN U15-11 U9-AB42

CLK_G2_AP U15-12 U9-AB41

CLK_G2_BN U15-9 U10-AA42

CLK_G2_BP U15-10 U10-AA41

CLK_G2_QSEN U15-7 J24-112

CLK_G2_QSEP U15-8 J24-114

CLK_G2_TN U15-13 TP45-2

CLK_G2_TP U15-14 TP45-1

4.4 Daughter Card (DC) Header Clocks

There are six daughter card headers on the DN7002K10MEG Logic Emulation Board. The 400 pin MEG-Array connectors on the bottom of the PCBA are used to interface to Dini Group products, e.g. DNMEG_AD-DA. Each of the daughter card headers provides an LVDS clock that is buffered and distributed to the Stratix-III/IV FPGAs. In addition two secondary clocks are provided on the daughter card header and connect to clock inputs on the FPGA bank. The DNMEG_INTERCON Daughter Card bridges the expansion signals between two adjacent 400-pin MEG-Array connectors, adding 182 signals for FPGA to FPGA interconnect.

4.4.1 SMA & DC A0 Zero Delay Clock Generator (U1)

Two SMA‘s (J3/J4) are provided to allow for an external differential clock (CLK_USER_A0p/n) input to the FPGAs via a Zero Delay Clock Buffer (U1). The second input port on the Zero Delay Clock Buffer (U1) is used to buffer the global clock signal from Daughter Card A0 (CLK_DC_A0p/n).

Capacitors (C48, C49) allows for AC coupling, refer to Figure 18. J3/J4 are Amphenol SMA jacks, P/N 901-144-8RFX with an impedance rating of 50Ω. Refer to the Altera Stratix III/IV Device Handbook for IO levels.

http://www.dinigroup.com/DNMEG_Intercon.php




Figure 18 – SMA & DC A0 Zero Delay Clock Generator

4.4.2 SMA & DC B0 Zero Delay Clock Generator (U4)

Two SMA‘s (J8/J9) are provided to allow for an external differential clock (CLK_USER_B0p/n) input to the FPGAs via a Zero Delay Clock Buffer (U4). The second input port on the Zero Delay Clock Buffer (U4) is used to buffer the global clock signal from Daughter Card B0 (CLK_DC_B0p/n).

Capacitors (C65, C66) allows for AC coupling, refer to Figure 19. J8/J9 are Amphenol SMA jacks, P/N 901-144-8RFX with an impedance rating of 50Ω. Refer to the Altera Stratix III/IV Device Handbook for IO levels.

Figure 19 – SMA & DC B0 Zero Delay Clock Generator

4.4.3 DC A2 & B1 Zero Delay Clock Generator (U37)

A clock from Daughter Card A2 (CLK_DC_A2p/n) and a clock from Daughter Card B1 (CLK_DC_B1p/n) drives a Zero Delay Clock Buffer (U37) which in turn drives the FPGAs. The Configuration FPGA (U25) determines which clock input is selected.

CLK_USER_A0n

R281100R

J3901-144-8RFX

2

3 4

51 CLK_DC_A0_QSEn pg24

P3.3V_CLK_A0

CLKGEN_A0_MR

R265.11R

CLK_DC_A0npg8

CLKGEN_A0_S23

C474.7uF

CLKGEN_A0_S1

CLK_DC_A0_FBn

R289100R

C414.7uF

CLKGEN_A0_PLLSEL

C494.7uF CLK_DC_A0_TPp

CLK_DC_A0_Bp pg2

R32100R

LVDSCLK_DC_A0ppg8

CLK_USER_A0p_c

U1

ICS8745BYLFICS8745B/LQFP32

12

34

56

8

9

12

13

1415

1632

31

30

29

28

2726

25

2423

22

2120

19

1817

1110

7

SEL0SEL1

CLK0nCLK0

CLK1nCLK1

MR

VDD1

SEL2

GND1

nQ0Q0

VDDO3VDD2

PLL_SEL

VDDA

SEL3

VDDO1

Q4nQ4

GND3

Q3nQ3

VDDO2

Q2nQ2

GND2

Q1nQ1

FB_INnFB_IN

CLKSELCLKGEN_A0_CLKSELCLKGEN_A0_S0

TP14 (DNI)

R38100R

CLK_DC_A0_An

J4901-144-8RFX

2

3 4

51

R302 100R

CLK_DC_A0_Ap

C484.7uF

CLK_USER_A0n_c

CLK_DC_A0_QSEn CLK_DC_A0_QSEp pg24

P3.3VD

CLK_DC_A0_Bn pg2

CLK_DC_A0_An pg2

R282100R

CLK_DC_A0_Ap pg2

C524.7uF

CLK_DC_A0_TPn

CLK_DC_A0_FBp

CLK_DC_A0_QSEp

R290 100R

CLK_DC_A0_BpCLK_DC_A0_Bn

P3.3VD

CLK_USER_A0p

C554.7uF

R327100R

CLK_DC_B0_Bp

J8901-144-8RFX

2

3 4

51

CLK_DC_B0_An

R378 100R

CLK_DC_B0_FBn

CLK_DC_B0_QSEp

J9901-144-8RFX

2

3 4

51

R48100R

R47100R

CLKGEN_B0_S0

CLKGEN_B0_S23

R351 100R

CLK_DC_B0_TPn

C664.7uF

CLK_DC_B0_Ap pg2

P3.3VD

CLK_DC_B0_Bp pg2CLK_USER_B0p

C654.7uF

CLK_USER_B0n

CLK_DC_B0npg14

CLK_USER_B0n_c

R415.11R

CLK_DC_B0_Bn pg2TP31 (DNI)

LVDS

CLK_DC_B0_QSEp pg24CLK_DC_B0_QSEnCLK_DC_B0_QSEn pg24

CLK_DC_B0_FBp

CLK_DC_B0_Ap

CLKGEN_B0_S1

CLK_USER_B0p_c

CLK_DC_B0_TPp

R51100R

CLK_DC_B0_Bn

P3.3VD

U4


12

34

56

8

9

12

13

1415

1632

31

30

29

28

2726

25

2423

22

2120

19

1817

1110

7

SEL0SEL1

CLK0nCLK0

CLK1nCLK1

MR

VDD1

SEL2

GND1

nQ0Q0

VDDO3VDD2

PLL_SEL

VDDA

SEL3

VDDO1

Q4nQ4

GND3

Q3nQ3

VDDO2

Q2nQ2

GND2

Q1nQ1

FB_INnFB_IN

CLKSEL

CLK_DC_B0ppg14

CLKGEN_B0_MR

CLKGEN_B0_CLKSEL

CLK_DC_B0_An pg2

P3.3V_CLK_B0

C684.7uF

R350100R

CLKGEN_B0_PLLSEL

C584.7uF



Figure 20 – DC A2 & B1 Zero Delay Clock Generator

4.4.4 DC B2 & A1 Zero Delay Clock Generator (U38)

A clock from Daughter Card B2 (CLK_DC_B2p/n) and a clock from Daughter Card A1 (CLK_DC_A1p) drives a Zero Delay Clock Buffer (U38) which in turn drives the FPGAs. The Configuration FPGA (U25) determines which clock input is selected.

Figure 21 – DC B2 & A1 Zero Delay Clock Generator

4.4.5 Connection between Daughter Card (DC) Clocks and FPGAs

The connection between Daughter Card Clocks and FPGAs are shown in Table 11.

Table 11 - Connections between Daughter Card Clocks and FPGAs

Signal Name Clock Buffer Pin FPGA Pin

SMA & DC A0 Zero Delay Clock Generator (CLK_DC_A0_xx)

R813 100R

CLKGEN_A2_S0

CLK_DC_B1npg16

CLK_DC_B1p

CLKGEN_A2_CLKSEL

CLK_DC_B1n

U37


12

34

56

8

9

12

13

1415

1632

31

30

29

28

2726

25

2423

22

2120

19

1817

1110

7

SEL0SEL1

CLK0nCLK0

CLK1nCLK1

MR

VDD1

SEL2

GND1

nQ0Q0

VDDO3VDD2

PLL_SEL

VDDA

SEL3

VDDO1

Q4nQ4

GND3

Q3nQ3

VDDO2

Q2nQ2

GND2

Q1nQ1

FB_INnFB_IN

CLKSEL

R809100R

CLKGEN_A2_MR

CLK_DC_A2p

CLK_DC_B1ppg16

C1854.7uF

CLKGEN_A2_S1

R1495.11R

CLK_DC_A2n

CLKGEN_A2_PLLSEL

CLK_DC_A2_TPp

CLK_DC_A2ppg12

CLKGEN_A2_S23

CLK_DC_A2_An pg2CLK_DC_A2_Bp

CLK_DC_A2_Bn pg2

CLK_DC_A2npg12

CLK_DC_A2_Bp pg2

C2034.7uF

LVDSCLK_DC_A2_Ap

R152 100R

TP83 (DNI)

CLK_DC_A2_FBn

CLK_DC_A2_TPn

P3.3V_CLK_A2

CLK_DC_A2_FBp

CLK_DC_A2_An

CLK_DC_A2_Bn

R810 100R

C1894.7uF

P3.3VD

CLK_DC_A2_Ap pg2

CLK_DC_B2n

CLK_DC_A1ppg10

C2074.7uF

CLK_DC_B2_Ap pg2

R814 100R

CLK_DC_B2_TPnCLKGEN_B2_S0

CLK_DC_A1p

CLKGEN_B2_MR

CLK_DC_B2_Ap

CLK_DC_B2_Bp pg2

CLKGEN_B2_S1

CLK_DC_B2_Bn

R811 100R

CLK_DC_B2_Bn pg2CLK_DC_A1npg10

CLKGEN_B2_CLKSEL

CLK_DC_B2_Bp

R1505.11R

C1914.7uF

C1904.7uF

CLKGEN_B2_PLLSEL

CLK_DC_B2_TPp

CLK_DC_B2ppg18

CLKGEN_B2_S23 R151100R

TP84 (DNI)

CLK_DC_B2_FBp

R812 100R

CLK_DC_B2npg18

CLK_DC_B2_FBn

CLK_DC_B2_An

P3.3VD

U38


12

34

56

8

9

12

13

1415

1632

31

30

29

28

2726

25

2423

22

2120

19

1817

1110

7

SEL0SEL1

CLK0nCLK0

CLK1nCLK1

MR

VDD1

SEL2

GND1

nQ0Q0

VDDO3VDD2

PLL_SEL

VDDA

SEL3

VDDO1

Q4nQ4

GND3

Q3nQ3

VDDO2

Q2nQ2

GND2

Q1nQ1

FB_INnFB_IN

CLKSEL

LVDSP3.3V_CLK_B2

CLK_DC_B2p

CLK_DC_B2_An pg2

CLK_DC_A1n




CLK_DC_A0_AN U1-14 U9-AB1

CLK_DC_A0_AP U1-15 U9-AB2

CLK_DC_A0_BN U1-17 U10-AA1

CLK_DC_A0_BP U1-18 U10-AA2

CLK_DC_A0_QSEN U1-20 J24-117

CLK_DC_A0_QSEP U1-21 J24-119

CLK_DC_A0_TPN U1-23 TP14-2

CLK_DC_A0_TPP U1-24 TP14-1

SMA & DC B0 Zero Delay Clock Generator (CLK_DC_B0_xx)

CLK_DC_B0_AN U4-14 U9-A22

CLK_DC_B0_AP U4-15 U9-B22

CLK_DC_B0_BN U4-17 U10-BB21

CLK_DC_B0_BP U4-18 U10-BA21

CLK_DC_B0_QSEN U4-20 J24-111

CLK_DC_B0_QSEP U4-21 J24-113

CLK_DC_B0_TPN U4-23 TP31-2

CLK_DC_B0_TPP U4-24 TP31-1


DC B1 & DC A2 Zero Delay Clock Generator (CLK_DC_A2_xx)

CLK_DC_A2_AN U37-14 U9-AA42

CLK_DC_A2_AP U37-15 U9-AA41

CLK_DC_A2_BN U37-17 U10-AB42

CLK_DC_A2_BP U37-18 U10-AB41

CLK_DC_A2_TPN U37-23 TP83-2


DC A1 & DC B2 Zero Delay Clock Generator (CLK_DC_B2_xx)

CLK_DC_B2_AN U38-14 U9-BB21

CLK_DC_B2_AP U38-15 U9-BA21

CLK_DC_B2_BN U38-17 U10-A22




CLK_DC_B2_BP U38-18 U10-B22

CLK_DC_B2_TPN U38-23 TP84-2

CLK_DC_B2_TPP U38-24 TP84-1

4.4.6 Secondary Daughter Card (DC) Header Clocks

One secondary, bidirectional LVDS clock is provided on the daughter card header bank 0 (pin E1, F1). The clock pins connect to the clock inputs on the Stratix-III/IV FPGAs IO bank that is connected to the daughter card header, see Figure 22. These clocks need to comply with the IO requirements of the Stratix-III/IV FPGA IO bank they are connected to.

Figure 22 – Secondary Daughter Card (DC) Header Clock

4.4.7 Connection between FPGAs and the Secondary DC Header Clocks

The connection between the Stratix-III/IV FPGAs and the secondary DC header clocks are shown in Table 12.

Table 12 - Connections between FPGAs and Secondary DC Header Clocks

Signal Name FPGA Pin DC Header Pin

Daughter Card A0

DC_A0B0_RX11N_GCA U9-AA3 P6-F1

DCD0NRX3

DCD0NTX5 DCD0NRX5

PVIO_DCD0

DCD0PRX5

C1452.2uF6.3V20%CER

DCD0PTX6

DCD0NTX2

DCD0NTX6

DCD0NTX1

DCD0NTX0

DCD0NRX6

DCD0PRX0

DCD0NRX2

DCD0PRX6

DCD0PRX10

DCD0PRX2

DCD0PTX1

DCD0PTX7

DCD0PTX9

DCD0NRX0

DCD0PTX3

DCD0PRX1

DCD0NTX7

DCD0NTX9

DCD0NRX11_GCA

DCD0PTX0

DCD0NRX1

DCD0PRX7

DCD0PRX9

DCD0PRX3

DCD0PTX2

DCD0NRX7

DCD0NRX9

DCD0NRX10

DCD0NTX4

DCD0PRX11_GCA

DCD0PTX8

DCD0NTX10

DCD0PTX4

LVDS Outputs from Main Board / Single-Ended bidir

LVDS Inputs to Main Board/ Single-Ended bidir

Stratix III MEG-400 Bank 0

Section 2 of 6

P4-2

MEG-Array 400 Stratix-3

A3B4

C3D4

A5B6

C5D6

A7B8

C7D8C9

D10C11D12C13D14C15D16C17D18C19D20C21D22

A9B10A11B12A13B14A15B16A17B18A19B20

E1F1

E9F9E13F13

E7F7

E11F11

A6

B0_RX_L0PB0_RX_L0N

B0_TX_L0PB0_TX_L0N

B0_RX_L1PB0_RX_L1N

B0_TX_L1PB0_TX_L1N

B0_RX_L2PB0_RX_L2N

B0_TX_L2PB0_TX_L2NB0_TX_L3PB0_TX_L3NB0_TX_L4PB0_TX_L4NB0_TX_L5PB0_TX_L5NB0_TX_L6PB0_TX_L6NB0_TX_L7PB0_TX_L7NB0_TX_L8PB0_TX_L8NB0_TX_L9PB0_TX_L9N

B0_RX_L3PB0_RX_L3NB0_RX_L4PB0_RX_L4NB0_RX_L5PB0_RX_L5NB0_RX_L6PB0_RX_L6NB0_RX_L7PB0_RX_L7NB0_RX_L8PB0_RX_L8N

B0_RX_L11P_GCAB0_RX_L11N_GCA

B0_RX_L9PB0_RX_L9N

B0_RX_L10PB0_RX_L10N

B0_TX_L10PB0_TX_L10NB0_TX_L11PB0_TX_L11N

B0_VCCO

DCD0NTX8

DCD0PTX10

DCD0PRX4

DCD0PRX8

DCD0NTX11

DCD0NRX4

DCD0NTX3

DCD0NRX8

DCD0PTX11

DCD0PTX5



Signal Name FPGA Pin DC Header Pin

DC_A0B0_RX11P_GCA U9-AA4 P6-E1

Daughter Card A1

DC_A1B0_RX11n_GCA U9-AB3 P5-F1

DC_A1B0_RX11p_GCA U9-AB4 P5-E1

Daughter Card A2

DC_A2B0_RX11N_GCA U9-AY22 P4-F1

DC_A2B0_RX11P_GCA U9-AW22 P4-E1

Daughter Card B0

DC_B0B0_RX11N_GCA U10-AB3 P3-F1

DC_B0B0_RX11P_GCA U10-AB4 P3-E1

Daughter Card B1

DC_B1B0_RX11N_GCA U10-AA3 P2-F1

DC_B1B0_RX11P_GCA U10-AA4 P2-E1

Daughter Card B2

DC_B2B0_RX11N_GCA U10-C21 P1-F1

DC_B2B0_RX11P_GCA U10-D21 P1-E1

4.5 Main Bus Clock – CLK_MB

The Main Bus clock (CLK_MB48p/n) is a 48MHz clock provided by the Configuration FPGA (U25) and distributed to the rest of the board with an LVDS clock buffer (U20).

4.5.1 Main Bus Clock Circuit

The Main Bus clock buffer (U20) is provided to distribute the clock network to the Stratix-III/IV FPGAs, see Figure 23.



Figure 23 – Main Bus Clock Buffer

4.5.2 Connection between Main Bus Clock Buffer and the FPGAs

The connection between the Main Bus Clock Buffer (U20) and the FPGAs are shown in Table 13.

Table 13 - Connection between Main Bus Clock Buffer and FPAGs


CLK_MB48_AN U20-60 U9-BB22

CLK_MB48_AP U20-61 U9-BA22

CLK_MB48_BN U20-58 U10-A21

CLK_MB48_BP U20-59 U10-B21

CLK_MB48_QSEN U20-56 J24-118

CLK_MB48_QSEP U20-57 J24-120

4.6 External SMA Clock Inputs, one per FPGA

Two SMA‘s are provided to allow for an external differential clock (CLK_FPGA_x_EXTp/n) input to each of the Stratix-III/IV FPGAs.

CLK_MB48ppg24

CLK_MB_NC21p

CLK_MB_NC13n

CLK_MB_NC19n

CLK_MB_NC15p

CLK_MB_NC11p

CLK_MB48_QSEp pg24

CLKMB_BUF_OE

TP55(DNI)

CLK_MB48_Ap pg2

CLK_MB_NC6n

R5661K

CLK_MB48_Ap

R537 100R

R88 100R

R87 100R

CLK_MB48_Sp

CLK_MB_NC12n

CLK_MB_NC7n

CLK_MB_NC5n

R524 100R

CLK_MB_NC17nCLK_MB_NC18p

R509 100R

CLK_MB48_QSEn

CLK_MB_NC9n

R78 100R

CLK_MB_NC18n

CLK_MB_NC14p

CLK_MB_NC7p

CLK_MB_NC5p

R508 100R

C1342.2uF6.3V20%CER

CLK_MB_NC15n

R79 100R

CLK_MB_NC16nCLK_MB_NC17p

CLKMB_BUF_SEL

CLK_MB48p

CLK_MB_NC21n

CLK_MB48_QSEn pg24CLK_MB_NC4p

R525 100R

CLK_MB_NC20p

CLK_MB48n

C1352.2uF6.3V20%CER

CLK_MB48_QSEp

CLK_MB_NC10n

CLK_MB_NC6p

CLK_MB48_Bn

U20

SY89826L/TQFP64SY89826LHY

56

2

2728293031

3233

3435

26252423222120191815

1

3

4

7

89

10

11

12

13 1617

53525150

4948

474645444342414039383736

63626160595857565554

64

14

65

LVDS_CLKLVDS_CLK

GNDO

Q16Q15Q15Q14Q14

VCCOGNDO

Q13Q13

Q16Q17Q17Q18Q18Q19Q19Q20Q20Q21

VCCO

NC

VCCI

CLK_SEL

LVPECL_CLKLVPECL_CLK

GNDI

OE

NC

GNDO VCCOVCCO

Q5Q5Q6Q6

VCCOGNDO

Q7Q7Q8Q8Q9Q9

Q10Q10Q11Q11Q12Q12

Q0Q0Q1Q1Q2Q2Q3Q3Q4Q4

VCCO

Q21

EPAD

CLK_MB_NC20n

CLK_MB_NC16p

R94 100R

C1362.2uF6.3V20%CER

R481 100R

CLK_MB48_An

CLK_MB_NC14n

CLK_MB48_Bn pg2

R557 100R

C1102.2uF6.3V20%CER

CLK_MB48npg24

CLK_MB_NC13p

CLK_MB48_Sn

CLK_MB_NC12p

R499 100R

R500 100R

CLK_MB_NC9p

R567 100R

CLK_MB_NC4n

CLK_MB48_Bp CLK_MB48_An pg2

CLK_MB_NC19p

CLK_MB48_Bp pg2

R548 100R

CLK_MB_NC10p

C1112.2uF6.3V20%CER

C1302.2uF6.3V20%CER

CLK_MB_NC11n

CLK_MB_NC8n

R602

1K

R547 100R

P3.3VD

CLK_MB_NC8p

R655 100R



4.6.1 External SMA Clock Input Circuit (FPGA A)

Resistors (R844, R845) can be preplaced with capacitors if AC coupling is required, refer to Figure 24. J22/J23 is Amphenol SMA jacks, P/N 901-144-8RFX with an impedance rating of 50Ω. Refer to the Altera Stratix III/IV Device Handbook for IO levels. J10/J11 is provided for FPGA B, please see schematic.

Figure 24 - Stratix-III/IV FPGA SMA Clock Input Circuit

4.6.2 Connection between Stratix-III/IV FPGAs and External SMA Connectors

The connection between the Stratix-III/IV FPGAs and the external SMAs are shown in Table 14.

Table 14 - Connection between Stratix-III/IV FPGAs and External SMA Connectors

Signal Name FPGA Pin SMA

CLK_FPGA_A_EXTN U9.AY42 J22-1

CLK_FPGA_A_EXTP U9.AY41 J23-1

CLK_FPGA_B_EXTN U10.C42 J11-1

CLK_FPGA_B_EXTP U10.C41 J10-1

4.7 External Clock Input - Test Point

A three terminal header is provided to allow for an external differential clock (CLK_FPGA_TPp/n) input to the Clock MUX (U31). The output of the Clock MUX (U31) drives the General Clock Multiplier (U32) which in turn drives the Stratix III/IV FPGAs. The Clock MUX (U31) input is selected by the Configuration FPGA with MUX_FPGA_CLK[2..0].

4.7.1 External Clock Test Point Circuit

The external clock test point circuit is shown below, see Figure 25.

CLK_FPGA_A_EXTpR845 0RrCLK_FPGA_A_EXTn

J23901-144-8RFX

2

34

51

CLK_FPGA_A_EXTnrCLK_FPGA_A_EXTp

J22901-144-8RFX

2

34

51

R844 0R



Figure 25 - External Clock Test Point Circuit

5 Memory

This section describes the on-board memory interfaces and provides signal name, type and signal connectivity relative to the Stratix-III/IV devices. The Dini Group also provides a number of SODIMM Daughter Cards that can be used in the SODIMM locations.

5.1 DDR2 SDRAM SODIMMs

The DN7002K10MEG supports two 64-bit, 200 pin SODIMM modules connected to the Stratix-III/IV FPGAs (A and B) and allow addressing for up to 4GB DDR2 SDRAM (PC2-4200/PC2-5300) modules. The interface is connected to IO Banks on the Stratix-III/IV FPGAs and uses a +1.8V switching power supply for VDD and VCCIO. VTT and VREF are powered from a separate linear power supply set at 0.9V. DDR2 SDRAM modules are available from Micron, example part number for a 512MB (64Meg x 64) 200-pin SODIMM SDRAM module is: MT4GTF6464HY-53E. Altera published a DDR2 application note; please refer to AN 435: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Stratix III Devices.

5.1.1 DDR2 Termination

Stratix-III/IV devices support both series and parallel on-chip termination (OCT) resistors to improve signal integrity. Another benefit of the Stratix-III/IV OCT resistors is eliminating the need for external termination resistors on the FPGA side. This feature simplifies board design and reduces overall board cost. It is possible to dynamically switch between the series and parallel OCT resistor depending on whether the Stratix-III/IV devices are performing a write or a read operation. The OCT

CLK_FPGA_A_OUTp

MUX_FPGA_CLK1

CLK_FPGA_A_OUTn

CLK_FPGA_TPp

Clock TP

C1492.2uF6.3V20%CER

CLK_FPGA_INTn

P3.3VD

R610 100R

CLK_FPGA_B_OUTp

CLK_FPGA_TPn

MUX_FPGA_CLK0

CLK_FPGA_INTp

R676 100R

J17

90120-0123

123

U31

ICS854058/TSSOP24ICS854058AG

1

3

678

17 20

19

5

2

4

910

1112

1413

1615

2221

2423

18PCLK0p

PCLK1p

SEL0SEL1SEL2

GND VDD

Q0p

VDD

PCLK0n

PCLK1n

PCLK2pPCLK2n

PCLK3pPCLK3n

PCLK4pPCLK4n

PCLK5pPCLK5n

PCLK6pPCLK6n

PCLK7pPCLK7n

Q0nR641 100R

C1482.2uF6.3V20%CER

MUX_FPGA_CLK2

CLK_FPGA_B_OUTn

P3.3VD

http://www.micron.com/

http://www.micron.com/products/partdetail?part=MT4GTF6464HY-53E

http://www.altera.com/literature/an/an435.pdf

http://www.altera.com/literature/an/an435.pdf



features offer user-mode calibration to compensate for any variation in voltage and temperature during normal operation to ensure that the OCT values remain constant. The parallel and series OCT features on the Stratix III/IV devices are available in

either a 25Ω or 50Ω setting. Refer to the I/O Features chapter of the Stratix III /IV

Device Handbook for information about the OCT features.

On the DDR2 SDRAM, there is a dynamic parallel on-die termination (ODT) feature that can be turned on when the FPGA is writing to the DDR2 SDRAM memory and turn off when the FPGA is reading from the DDR2 SDRAM memory. The ODT

features are available in settings of 150Ω, 75Ω, and 50Ω. The 50Ω setting is only available in DDR2 SDRAM with operating frequencies greater than 267MHz. Refer to the respective memory data sheet for additional information about the available settings of the ODT and the output driver impedance features, and the timing requirements for driving the ODT pin in DDR2 SDRAM.

Figure 26 illustrates the write operation to the DDR2 SDRAM memory with the ODT feature turned on and using the 50Ω series OCT feature of the Stratix-III/IV FPGA device. In this setup, the transmitter (FPGA) is properly terminated with matching impedance to the transmission line, thus eliminating any ringing or reflection. The receiver (DDR2 SDRAM memory) is also properly terminated when the dynamic

ODT setting is at 75Ω

Figure 26 - Write Operation Using Parallel ODT and 50Ω Series OCT of the Stratix-III/IV FPGA Device

Figure 27 illustrates the read operation from the DDR2 SDRAM memory using the parallel OCT feature of the Stratix-III/IV device. In this setup, the driver's (DDR2 SDRAM memory) output impedance is not larger than 21Ω. This is in keeping with SSTL-18 JEDEC specification JESD79-2, which combined with an on DIMM series resistor, matches that of the transmission line resulting in optimal signal transmission to the receiver (FPGA). On the receiver (FPGA) side, it is properly terminated with 50Ω which matches the impedance of the transmission line, thus eliminating any ringing or reflection.



Figure 27 - Read Operation from DDR2 SDRAM Memory Using the Parallel OCT Feature of the Stratix-III/IV

Finally, the loading seen by the FPGA during writes to the memory is different between a system using dual-inline memory modules (DIMMs) versus a system using components. The additional loading from the DIMM connector can reduce the edge rates of the signals arriving at the memory thus affecting available timing margin.

The DDR2 SDRAM SODIMM interface has bi-directional and uni-directional signals, and the termination scheme is different for both types of signals, see Table 15. Reference the JESD8-15a JEDEC standard, Stub Series Terminated Logic for 1.8V (SSTL_18) for more information regarding output specifications.

Table 15 - DDR2 Termination

Signal Drivers at FPGA Termination at FPGA

Termination at SODIMM

Data (DQ) SERIES 50 OHM WITHOUT CALIBRATION

No Termination ODT

Data Strobe (DQS) SERIES 50 OHM WITHOUT CALIBRATION

No Termination ODT

Data Mask (DM) SERIES 50 OHM WITHOUT CALIBRATION

No Termination ODT

Clock (CK, CKn) SSTL_18_DIFF No Termination No Termination

Address (A, BA) SSTL-18 CLASS I No Termination 56Ω Pull-up to 0.9V

Control (RASn, CASn, WEn, CSn, CKE)

SSTL-18 CLASS I No Termination 56Ω Pull-up to 0.9V



5.1.2 VDD Switching Power Supply (P_SODIMM_x)

The Texas Instruments PTH12050 POLA DC-DC Converter is used to create the VDD supply for the DDR2 SDRAM SODIMM, set to 1.8V @ 6A, see Figure 28. A jumper (JP2) allows the user to change the voltage to the SODIMM and the FPGA VCCIO, see table (default jumper 3-5, +1.8V).

Figure 28 - VDD Switching Power Supply (P_SODIMM_A)

5.1.3 VTT Linear Power Supply (P0.9V_VTT_x)

The National Semiconductor LP2996 linear regulator was designed to meet the JEDEC SSTL_18 specifications for termination of DDR2 SDRAM SODIMMs. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A, see Figure 29.

Figure 29 - VTT Linear Power Supply (P0.9V_VTT_A)

5.1.4 Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM‘s SCL (clock) and SDA (data) signals, together with SA[1:0], which provide four unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. VDDSPD is connected to P_SODIMM_x to meet IO standards of the Stratix-III/IV FPGA IO Bank.

Note: The GND pins of the VOUT ADJ trim

resistors must be connected directly to

the converter GND pin with a trace. The

jumper option may degrade performance.

Adjust VOUT ADJ Trim Resistors:

OPEN - DDR3 (+1.5V)

3-5 - DDR2 (+1.8V)

3-4 - DDR1 (+2.5V)

1-3 - SDR (+3.0V)

P1.8V_A

PSU3

PTH12050W/DIP6PTH12050WAZ

5

1

3 6

4

2

VOUT ADJ

GND

VIN VOUT

INHIBIT

TRACKC7847uF

CER

16V20%

Silkscreen: "Volt JMPR"

+C458330uF6.3V20%TANT

P_SODIMM_A

R62(DNI-0R)

+C425150uF16V20%TANT

VO_ADJ_A

C642.2uF6.3V20%CER

P_SODIMM_A

JP2

TSM-103-01-T-DV

1 23 45 6

C6047uF

CER

6.3V20%

+C457330uF6.3V20%TANT

F9

7A

P2.5V_A

P12V

INH_DIMMAn

P3.0V_A

R4521.5K

P12VFUSED_P_SODIMM_A

C7747uF

CER

16V20%

GND

TP251

R432.94K

R425.23K

R4424.9K

C670.1uF

CER

16V20%


P_VREF_SODIMM_A

U49

LP2996/PSOP-8LP2996MR

8

9

7

42

65 3

1

VTT

PKG GND

PVIN

VREFSD

AVINVDDQ VSENSE

GND

R2731K

P_SODIMM_A

VTT_SNS_A+

C364330uF6.3V20%TANT

P_SODIMM_A

C3832.2uF6.3V20%CER

R240 0R

P3.3VD

VTT_SDn_A

GND

TP21

C3702.2uF6.3V20%CER

C39147uF6.3V20%CER

C3992.2uF6.3V20%CER

P0.9V_VTT_A

P0.9V_VTT_A

C36747uF

CER

6.3V20%

P3.3VD

P3.3VD

C3842.2uF6.3V20%CER



Table 16 - Serial Presence-Detect EEPROM Connections

Signal Name FPGA SODIMM

SODIMM A (J1) – FPGA A (U9)

DIMMA_SA0 Not Connected J1.198 pull-down with 4.7K (R246)

DIMMA_SA1 Not Connected J1.200 pull-down with 4.7K (R245)

DIMMA_SCL U9-E22 J1.197 pull-up 4.7K (R231)

DIMMA_SDA U9-F22 J1.195 pull-up 4.7K (R232)

SODIMM B (J2) – FPGA B (U10)

DIMMB_SA0 Not Connected J2.198 pull-down with 4.7K (R248)

DIMMB_SA1 Not Connected J2.200 pull-down with 4.7K (R247)

DIMMB_SCL U10-AV22 J2.197 pull-up 4.7K (R234)

DIMMB_SDA U10-AU22 J2.195 pull-up 4.7K (R235)

5.1.5 Clocking Connections between Stratix-III/IV FPGAs and DDR2 SDRAM

SODIMMs

The clocking connections between the Stratix-III/IV FPGAs and the DDR2 SDRAM SODIMMs are shown in Table 17.



Table 17 – Clocking Connections between Stratix-III/IV FPGAs and the DDR2 SDRAM SODIMMs

Signal Name FPGA Pin SODIMM

FPGA A (U9) - SODIMM A (J1)

DIMMA_CK0N U9-D25 J1-32

DIMMA_CK0P U9-E25 J1-30


DIMMA_CK1P U9-F25 J1-164

FPGA B (U10) - SODIMM B (J2)

DIMMB_CK0N U10-AW25 J2-32

DIMMB_CK0P U10-AV25 J2-30


DIMMB_CK1P U10-AY26 J2-164

5.1.6 SODIMM connections to the Stratix-III/IV FPGAs

Table 18 shows the SODIMM connector pinouts and the connection to the Stratix-III/IV FPGAs.

Table 18 - Connections between the Stratix-III/IV /IV FPGAs and the SODIMMs

Signal Name FPGA Pin SODIMM Pin

FPGA A (U9) - SODIMM A (J1)

DIMMA_A0 U9-F27 J1-102

DIMMA_A1 U9-F26 J1-101

DIMMA_A10 U9-J24 J1-105

DIMMA_A11 U9-M24 J1-90

DIMMA_A12 U9-J25 J1-89

DIMMA_A13 U9-K25 J1-116

DIMMA_A14 U9-L24 J1-86

DIMMA_A15 U9-K24 J1-84

DIMMA_A2 U9-G26 J1-100

DIMMA_A3 U9-H25 J1-99

DIMMA_A4 U9-C26 J1-98

DIMMA_A5 U9-D26 J1-97

DIMMA_A6 U9-K29 J1-94

DIMMA_A7 U9-G30 J1-92




DIMMA_A8 U9-H22 J1-93

DIMMA_A9 U9-B28 J1-91

DIMMA_BA0 U9-G22 J1-107

DIMMA_BA1 U9-D23 J1-106

DIMMA_BA2 U9-C23 J1-85

DIMMA_CASN U9-M23 J1-113


DIMMA_CK0P U9-E25 J1-30


DIMMA_CK1P U9-F25 J1-164

DIMMA_CKE0 U9-J16 J1-79

DIMMA_CKE1 U9-K14 J1-80

DIMMA_DM0 U9-J29 J1-10

DIMMA_DM1 U9-E31 J1-26

DIMMA_DM2 U9-N26 J1-52

DIMMA_DM3 U9-G29 J1-67

DIMMA_DM4 U9-F14 J1-130

DIMMA_DM5 U9-M16 J1-147

DIMMA_DM6 U9-H16 J1-170

DIMMA_DM7 U9-K15 J1-185

DIMMA_DQ0 U9-J28 J1-5

DIMMA_DQ1 U9-K28 J1-7

DIMMA_DQ10 U9-G31 J1-35

DIMMA_DQ11 U9-F31 J1-37

DIMMA_DQ12 U9-A35 J1-20



DIMMA_DQ15 U9-B33 J1-38


DIMMA_DQ17 U9-L27 J1-45

DIMMA_DQ18 U9-M26 J1-55












DIMMA_DQ26 U9-H28 J1-73



DIMMA_DQ29 U9-D30 J1-64



DIMMA_DQ31 U9-E28 J1-76








DIMMA_DQ39 U9-C14 J1-136






DIMMA_DQ44 U9-N17 J1-140




























DIMMA_DQS0N U9-D33 J1-11

DIMMA_DQS0P U9-E33 J1-13

DIMMA_DQS1N U9-A34 J1-29

DIMMA_DQS1P U9-B34 J1-31

DIMMA_DQS2N U9-B31 J1-49

DIMMA_DQS2P U9-C31 J1-51

DIMMA_DQS3N U9-C29 J1-68

DIMMA_DQS3P U9-D29 J1-70

DIMMA_DQS4N U9-B12 J1-129

DIMMA_DQS4P U9-C12 J1-131

DIMMA_DQS5N U9-A8 J1-146

DIMMA_DQS5P U9-A9 J1-148




DIMMA_DQS6N U9-D10 J1-167

DIMMA_DQS6P U9-E10 J1-169

DIMMA_DQS7N U9-E12 J1-186

DIMMA_DQS7P U9-F12 J1-188

DIMMA_NC0 U9-B24 J1-50

DIMMA_NC1 U9-A24 J1-69

DIMMA_NC2 U9-A23 J1-83

DIMMA_NC3 U9-C25 J1-120

DIMMA_NC4 U9-B25 J1-163

DIMMA_ODT0 U9-J27 J1-114

DIMMA_ODT1 U9-M27 J1-119

DIMMA_RASN U9-M22 J1-108

DIMMA_S0N U9-M17 J1-110

DIMMA_S1N U9-D13 J1-115

DIMMA_SA0 R246-1 J1-198

DIMMA_SA1 R245-1 J1-200

DIMMA_SCL U9-E22 J1-197

DIMMA_SDA U9-F22 J1-195

DIMMA_WEN U9-A28 J1-109

FPGA B (U10) - SODIMM B (J2)

DIMMB_A0 U10-AT26 J2-102

DIMMB_A1 U10-AU26 J2-101

DIMMB_A10 U10-AN25 J2-105

DIMMB_A11 U10-AM25 J2-90

DIMMB_A12 U10-AR24 J2-89

DIMMB_A13 U10-AP24 J2-116

DIMMB_A14 U10-AM24 J2-86



DIMMB_A3 U10-AP25 J2-99

DIMMB_A4 U10-AW27 J2-98

DIMMB_A5 U10-AV27 J2-97





DIMMB_A7 U10-AL27 J2-92


DIMMB_A9 U10-AY28 J2-91

DIMMB_BA0 U10-AL24 J2-107

DIMMB_BA1 U10-AL23 J2-106

DIMMB_BA2 U10-AY23 J2-85

DIMMB_CASN U10-AW23 J2-113


DIMMB_CK0P U10-AV25 J2-30


DIMMB_CK1P U10-AY26 J2-164

DIMMB_CKE0 U10-AK17 J2-79

DIMMB_CKE1 U10-AR13 J2-80

DIMMB_DM0 U10-AP14 J2-10

DIMMB_DM1 U10-AM15 J2-26

DIMMB_DM2 U10-AP16 J2-52

DIMMB_DM3 U10-AU15 J2-67

DIMMB_DM4 U10-AW28 J2-130

DIMMB_DM5 U10-AT28 J2-147

DIMMB_DM6 U10-AK26 J2-170

DIMMB_DM7 U10-AM28 J2-185

DIMMB_DQ0 U10-AN14 J2-5


DIMMB_DQ10 U10-AL17 J2-35


DIMMB_DQ12 U10-AW12 J2-20

DIMMB_DQ13 U10-AY10 J2-22

DIMMB_DQ14 U10-BA9 J2-36


DIMMB_DQ16 U10-AT16 J2-43

DIMMB_DQ17 U10-AR16 J2-45







DIMMB_DQ20 U10-BB11 J2-44







DIMMB_DQ27 U10-AV15 J2-75














DIMMB_DQ4 U10-AU14 J2-4



















DIMMB_DQ54 U10-AM27 J2-174







DIMMB_DQ60 U10-AP29 J2-180





DIMMB_DQ8 U10-AM16 J2-23


DIMMB_DQS0N U10-AV12 J2-11

DIMMB_DQS0P U10-AU12 J2-13

DIMMB_DQS1N U10-AW11 J2-29

DIMMB_DQS1P U10-AW10 J2-31

DIMMB_DQS2N U10-BB9 J2-49

DIMMB_DQS2P U10-BB8 J2-51

DIMMB_DQS3N U10-BA12 J2-68

DIMMB_DQS3P U10-AY12 J2-70

DIMMB_DQS4N U10-BA31 J2-129

DIMMB_DQS4P U10-AY31 J2-131




DIMMB_DQS5N U10-BB35 J2-146

DIMMB_DQS5P U10-BB34 J2-148

DIMMB_DQS6N U10-AW33 J2-167

DIMMB_DQS6P U10-AV33 J2-169

DIMMB_DQS7N U10-AU31 J2-186

DIMMB_DQS7P U10-AT31 J2-188

DIMMB_NC0 U10-BB28 J2-50



DIMMB_NC3 U10-BA27 J2-120

DIMMB_NC4 U10-AT24 J2-163

DIMMB_ODT0 U10-AW13 J2-114

DIMMB_ODT1 U10-AN16 J2-119

DIMMB_RASN U10-AT22 J2-108

DIMMB_S0N U10-AP27 J2-110

DIMMB_S1N U10-AU28 J2-115

DIMMB_SA0 R248-1 J2-198

DIMMB_SA1 R247-1 J2-200

DIMMB_SCL U10-AV22 J2-197

DIMMB_SDA U10-AU22 J2-195

DIMMB_WEN U10-BA28 J2-109

5.1.7 DDR2 PCB Trace Lengths

The DDR2 traces on the DN7002K10MEG Logic Emulation Board are routed to the following lengths refer to Table 19:

Table 19 – DDR2 PCB Trace Lengths

Signal Name Routed Length (mm) Description

DIMMA_CK0N 79.14 Clock group

DIMMA_A0 78.01 Control group

DIMMA_DQ0 80.38 Data byte group

DIMMB_CK0N 82.97 Clock group

DIMMB_A0 81.04 Control group



Signal Name Routed Length (mm) Description

DIMMB_DQ0 83.39 Data byte group

6 LED Indicators

The DN7002K10MEG Logic Emulation board provides various LEDs to indicate that status of the board. The LEDs are turned ON by driving the GATE of the N-MOSFET HIGH, see Figure 30.

Figure 30 - LED IndicatorS

6.1 User LEDs

Numerous LEDs (Green) are provided to the user as a design aid during debugging. The LEDs can be turned ON by driving the corresponding pin HIGH. Table 20 describes the user LEDs and their associated pin assignments on the Stratix-III/IV FPGAs.

Table 20 – User LEDs

Signal Name FPGA Pin LED

FPGA A (U9)

FPGA_A_LED0 U9-B36 Q47-1 (DS9)

FPGA_A_LED1 U9-A36 Q46-1 (DS8)

FPGA_A_LED2 U9-A37 Q45-1 (DS7)

FPGA_A_LED3 U9-C35 Q44-1 (DS6)

FPGA_A_LED4 U9-C37 Q43-1 (DS5)

FPGA_A_LED5 U9-B37 Q42-1 (DS4)

FPGA_A_LED6 U9-F33 Q41-1 (DS3)

FPGA_A_LED7 U9-F32 Q40-1 (DS2)

FPGA B (U10)

FPGA_B_LED0 U10-AR31 Q55-1 (DS17)

FPGA_B_LED1 U10-AN31 Q54-1 (DS16)

FPGA_B_LED2 U10-AP32 Q53-1 (DS15)

R208 150R LEDA_C0LEDA_A0 DS9 GREEN LEDQ47

BSS138

3

1

2

If = 8mA

FPGA_A_LED0

P2.5VD




FPGA_B_LED3 U10-AN32 Q52-1 (DS14)

FPGA_B_LED4 U10-AM31 Q51-1 (DS13)

FPGA_B_LED5 U10-AL31 Q50-1 (DS12)

FPGA_B_LED6 U10-AU37 Q49-1 (DS11)

FPGA_B_LED7 U10-AT37 Q48-1 (DS10)

6.2 Configuration DONE LEDs

After the FPGAs have received all the configuration data successfully, it releases the DONE pin, which is pulled high by a pull-up resistor. A low-to-high transition on the DONE indicates configuration is complete and initialization of the device can begin. DONE pin drives an N-MOSFET and turns ON a blue LED when the DONE pin goes high. Table 21 describes the DONE LED and its associated pin assignment on the FPGAs.

Table 21 – FPGA DONE LEDs


FPGAA_DONE U9-AU38 Q15-1 (DS34)

FPGAB_DONE U10-AU38 Q16-1 (DS35)

CFPGA_DONE U25-AB21 Q12-1 (DS23)

6.3 Power Supply Status LEDs

The LT6700-1 is configured as a simple window comparator to monitor the power supplies. A Power FAULT will be indicated by the SYS_RSTn signal going active (LOW) and turning on the Reset LED (DS36). The SYS_RSTn signal can also be activated by enabling the Reset Switch (S2). Table 22 describes the power supply status LEDs and their associated voltage source.

Table 22 – Power Supply Status LEDs

Signal Name Source Pin LED

P12V J6-10/11 DS1

P2.5VD PSU2-5/6 DS29

P3.3VD PSU13-6 DS31

P5.0V J6-4/6/21/22/23 DS32

P1.1V_VCC_FPGAA PSU4-5/9 DS19

P1.1V_VCC_FPGAB PSU5-5/9 DS21



Signal Name Source Pin LED

P_SODIMM_A PSU3-6 DS25

P_SODIMM_B PSU1-6 DS28

P1.2V_S U23-1 DS23

SYS_RSTn U71-8 DS36

6.4 Miscellaneous LEDs

Table 23 describes the miscellaneous status LEDs and their associated source.

Table 23 – Miscellaneous LEDs

Signal Name Source LED

CONFIG FPGA (U20) – USB/Temp Sensor

LEDS_USBACT# U25-V10 DS41

LEDS_CFACT# U25-U6 DS42

LEDS_HOSTACT# U25-AB11 DS43

LEDS_PCIACT# U25-AB4 DS44

LED_S_ERR_TEMP# U25-AA4 DS45

LED_S_ERR_CONFIG# U25-Y5 DS46

Clock Multipliers – LOL Indicators

SYNTH_LOL_G0 U32-18 DS84



7 RS232 Port

An RS232 serial port (J5/J7) is provided for low speed communication with the MCU and FPGA logic. The RS-232 standard specifies output voltage levels between –5V to –15V for logical 1 and +5V to +15V for logical 0. Input must be compatible with voltages in the range of -3V to -15V for logical 1 and +3V to +15V for logical 0. This ensures data bits are read correctly even at maximum cable lengths between DTE and DCE, specified as 50 feet.

The RS-232 standard has two primary modes of operation, Data Terminal Equipment (DTE) and Data Communication Equipment (DCE). These can be thought of as host or PC for DTE and as peripheral for DCE. The DN7002K10MEG operates in the DCE mode only.



7.1.1 RS232 Circuit Diagram

Figure 31 shows the implementation of the serial port on the DN7002K10MEG Logic Emulation Board.

Figure 31 – MCU/Configuration FPGA Serial Port

There are two signals attached to the all the FPGAs:

Transmit Data - RS232_FPGA_TX

Receive Data - RS232_FPGA_RX

TX and RX provide bi-directional transmission of transmit and receive data. No hardware handshaking is supported. Since these signals are shared between all the FPGAs, only one FPGA can be in control of the bus at any particular time.

7.1.2 Connections between FPGAs and RS232 Port

The RS232 port is shared by all the FPGAs. The connections between the FPGA and the RS232 Port are shown in Table 24.

Table 24 - Connections between FPGAs and the RS232 Port

Signal Name FPGA Pin RS232

RS232_FPGA_RX U9-C36 (FPGA A)

U10-AV37 (FPGA B)

U56-13

RS232_FPGA_TX U9-D36 (FPGA A)

U10-AW37 (FPGA B)

U56-7

8 Temperature Sensors

The MAX1617A is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor—typically a low-cost, easily mounted 2N3904 NPN type—that replaces conventional thermistors or thermocouples. Remote accuracy is ±3°C for multiple

RS232_FPGA_RX

P2.5VD

RS232_MCU_RX

RS232_CPUMP1+

J7

TSM-105-01-T-DV

1 23 45 67 89 10

P5.0V

+5V_LCD

R304 4.7K

GND

RS232_CPUMP2+

C3980.1uF

C4070.1uF

P2.5VD

FPGA

GND

+12V_LCD

RS232_MCU_TX

R320 5.11R

P2.5VD

RS232_FPGA_RXr R268(DNI)

MCU

RS232_CPUMP2-

R267(DNI)

RS232_MCU_RX

C380 0.1uF

RS232_FPGA_TX

RS232_FPGA_RXD

R311 4.7K

RS232SHDN#

R2914.7K

U56

MAX3388ESOP65P638X110-24N

1

2

45

6

3

789

212019

1312

10

1817

16

11 15

22

24

23

14

C1+

V+

C2+C2-

V-

C1-

T1INT2INT3IN

T1OUTT2OUTT3OUT

R1OUTR2OUT

LOUT

R1INR2IN

LIN

SWOUT SWIN

GND

SHDN

VCC

VL

RS232_FPGA_TX

J5

TSM-105-01-T-DV

1 23 45 67 89 10

RS232_VPUMP-

C404 0.1uF

P12V

RS232_MCU_RXD

RS232_CPUMP1-

RS232_MCU_TXDRS232_FPGA_TXD

C3900.1uF

RS232_VPUMP+



transistor manufacturers, with no calibration needed. The remote channel can also measure the die temperature of other ICs, such as microprocessors, that contain an on-chip, diode-connected transistor.

8.1.1 Temperature Sensor Circuit

Each FPGA is connected to a temperature sensor. This sensor measures the temperature of the FPGA silicon die, see Figure 32. The maximum recommended operating temperature of the FPGA is 85ºC. When the configuration circuitry measures the temperature of any FPGA above 80ºC, it will immediately un-configure the FPGA, and prevent it from re-configuring.

Figure 32 - Temperature Sensor (FPGA A)

When the temperature drops below 80 ºC, the configuration circuitry will again allow the FPGA to configure. When this occurs the following message will appear on the CONFIG RS232 port (J7). An example test output is given below, with the threshold temperature set to 25ºC (default is 80 ºC):

U26

MAX1617ASOP63X600-16N

1412

11

106

8

2

15

34

159

1316

7

SMBCLKSMBDATA

ALERT

ADD0ADD1

GND

VCC

STBY

DXPDXN

NCNCNCNCNC

GND

FPGAA_TEMP_P

R648 4.7KTEMPA_SA1

TEMP_ALERT#

C10351000pF

P2.5VD

IIC_SCL pg6

P3.3VD

R649 4.7K

IIC_SDA pg6

P3.3TEMPA

P3.3VD

TEMPA_SA0

R5944.7K R603

4.7K

FPGAA_TEMP_N

R99 100R

C1380.1uF

TEMPA_STBY

C1374.7uF



The FPGA can safely operate as hot as 120 degrees, but timing is not guaranteed. Use the temperature setting in the Quartus place and route tool to make timing allowances for operating the FPGA out-of-range. The temperature limit on the DN7002K10MEG Logic Emulation Board can be changed or disabled by a menu option in the configuration interface (RS232).

8.1.2 Connection between Stratix-III/IV FPGAs and Temperature Sensors

The connection between the Stratix-III/IV FPGAs and the Temperature Sensors are shown in Table 25.

Table 25 - Connection between Stratix-III/IV FPGAs and Temperature Sensors

Signal Name FPGA Pin Sensor Pin

FPGAA_TEMP_P U9-G6 U26-3

FPGAA_TEMP_N U9-H7 U26-4

FPGAB_TEMP_P U10-G6 U36-3

FPGAB_TEMP_N U10-H7 U36-4



9 Miscellaneous FPGA IO Headers

The spare signals on FPGA A and B SODIMM banks are provided as easy-access IO on 10-pin IDC headers. The IO levels need to conform to the VCCIO voltage for the SODIMM IO bank on the FPGAs.

9.1.1 FPGA IO Header Circuit

See Figure 33 for the hardware implementation of the general purpose IO. Note: These signals are not buffered, exercise extreme care to avoid static discharge into these pins.

Figure 33 - Stratix-III/IV FPGA IO Header (FPGA A)

9.1.2 Connections between Stratix-III/IV FPGAs and 10-pin IO Headers

The connection between the Stratix-III/IV FPGAs and the 10-pin IO Headers are shown in Table 26.

Table 26 - Connection between Stratix-III/IV FPGAs and 10-pin IO Headers

Signal Name FPGA Pin IO Header Pin

FPGA A 10-pin IO Header

FPGA_A_IO0 U9-A25 J12-1

FPGA_A_IO1 U9-G23 J12-3

FPGA_A_IO2 U9-G24 J12-5

FPGA_A_IO3 U9-F24 J12-7

FPGA_A_IO4 U9-E24 J12-2

FPGA_A_IO5 U9-H24 J12-4

FPGA_A_IO6 U9-F23 J12-6

FPGA_A_IO7 U9-B27 J12-8

FPGA B 10-pin IO Header

FPGA_B_IO0 U10-AU23 J13-1

FPGA_B_IO1 U10-AW24 J13-3

FPGA_B_IO2 U10-AV24 J13-5

FPGA_B_IO3 U10-AT23 J13-7

FPGA_A_IO2

J12

TSM-105-01-T-DV

1 23 45 67 89 10

FPGA_A_IO0

FPGA_A_IO6FPGA_A_IO1

FPGA_A_IO3 FPGA_A_IO7

FPGA_A_IO5FPGA_A_IO4



Signal Name FPGA Pin IO Header Pin

FPGA_B_IO4 U10-AU24 J13-2

FPGA_B_IO5 U10-BA25 J13-4

FPGA_B_IO6 U10-AY25 J13-6

FPGA_B_IO7 U10-BB25 J13-8

10 Remote Slave SelectMAP Configuration

In order to configure Dini Group Daughter Cards from the mother board, a Slave SelectMAP configuration interface (8-bit configuration bus ―SELECTMAP_D [7..0]‖) is provided via the Mictor header (J25). In Slave SelectMAP, ―FPGA_M_CCLK‖ is an output and must be supplied by the Configuration FPGA (U25). Some MainBus signals are also provided on this Connector.

10.1.1 Slave SelectMAP Mictor Header

Figure 34 shows the pin assignments for the Slave SelectMAP Mictor header (J25).

Figure 34 – Slave SelectMAP Mictor Header

10.1.2 Slave SelectMAP Mictor connections to the Configuration FPGA

Table 27 shows the connection between the Slave SelectMAP Mictor header and the Stratix-III/IV FPGAs.

Table 27 – Slave SelectMAP Mictor connections to the Configuration FPGA

Signal Name Mictor Pin Configuration FPGA Pin

CLK_48_MIC J25-6 U25-J2

MB31

FPGA_M_DONE

MB27

MB16

FPGA_RD/WR#

SELECTMAP_D4

MB24

SELECTMAP_D7

CLK_48_MIC

FPGA_M_PROG#

MB28

SELECTMAP_D2 MB26

MB34MB19

MB17

MB35

GND

CLK

D15

D0

CLK

D0

D15

Do Not Connect

J25

2-767004-2767004-38B

13579

1113151719212325272931333537

2468101214161820222426283032343638

394041

4243

44

135791113151719212325272931333537

2468

101214161820222426283032343638

GNDGNDGND

GNDGND

LOC

FPGA_M_CCLK

MB32

SELECTMAP_D1

MICTOR_CLK_E

SELECTMAP_D6

MB25

MB20

SELECTMAP_D0

MB23

MB30MB29

MB18

SELECTMAP_D5

MB22

SELECTMAP_D3

FPGA15_CS#

MB33

FPGA14_CS#

MB21




MICTOR_CLK_E J25-5 U25-C12

FPGA_M_CCLK J25-12 U20-R2

FPGA_M_DONE J25-10 U20-T3

FPGA_M_PROG# J25-14 U20-Y1

FPGA_RD/WR# J25-8 U20-G20

FPGA14_CS# J25-4 U20-R5

FPGA15_CS# J25-2 U20-R4

MB16 J25-21 U25-W3

MB17 J25-19 U25-T2

MB18 J25-17 U25-T4

MB19 J25-15 U25-W1

MB20 J25-13 U25-N6

MB21 J25-11 U25-T1

MB22 J25-9 U25-P6

MB23 J25-7 U25-U2

MB24 J25-38 U25-V4

MB25 J25-36 U25-M4

MB26 J25-34 U25-N4

MB27 J25-32 U25-N3

MB28 J25-30 U25-N5

MB29 J25-28 U25-W4

MB30 J25-26 U25-M5

MB31 J25-24 U25-U4

MB32 J25-22 U25-P4

MB33 J25-20 U25-U5

MB34 J25-18 U25-M3

MB35 J25-16 U25-M6

SELECTMAP_D0 J25-37 U25-G18

SELECTMAP_D1 J25-35 U25-F19









SELECTMAP_D7 J25-23 U25-K19

11 FPGA Interconnect

11.1 MainBus (MB)

MainBus, MB[71..0] is a 72-bit bus that is routed to all the FPGAs. MB[35:0] is used by the Configuration FPGA to communicate with the Stratix-III/IV FPGAs see Figure 35. These pins implement the Dini Group ―MainBus‖ protocol. MainBus can be disabled in the Configuration FPGA and these pins may be used as general interconnect if MainBus functionality is not required. Contact [email protected] for more information regarding the MainBus interface and available source code and documentation.

Configuration

FPGAXC3S1000

FPGA AEP3SL340

FPGA BEP3SL340

MB[35:0] MB[71:0]

QSE Header

QSE-060-01-L-D-A

MICTOR Header

2-767004-2

MB[35:16]

Figure 35 - MainBus Interconnect

11.1.1 MainBus (MB) Header

A QSE header (J24) is provided for direct connection to the MainBus signals, Samtec P/N QSE-060-01-L-D-A, see Figure 36.

http://www.samtec.com/



Figure 36 - MainBus Header (QSE)

Due to the complexity of the interconnect, reference the board netlist on the Customer CD ROM to determine the connections.

MB56

MB52

MB61

MB49

MB35

CLK_DC_A0_QSEn

MB51

MB19

MB2

P3.3VD

MB33

MB16

CLK_G2_QSEn

MB70

MB18

MB30

MB66

MB4

CLK_MB48_QSEn

P2.5VD

MB67

MB28

MB9

MB15

MB48

MB7

CLK_DC_B0_QSEp

MB5

MB26

MB34

MB53

MB1

MB17

MB58

MB29

MB63

MB46

MB40

MB57

MB6

MB55

MB27

MB14

MB21

MB41

P2.5VD

MB23

MB38

MB11MB13

MB31

MB36

MB20

MB64

MB8

MB59

LVDS

CLOCKS TO

DAUGHTER

CARD

POWER TO

DAUGHTER

CARD

MATES WITH SAMTEC P/N QTE-060-09-L-D-A

J24QSE-060-01-L-D-A

13579

111315171921232527293133353739

4143454749515355575961636567697173757779

81838587899193959799

101103

105107109111113115117119

246810121416182022242628303234363840

4244464850525456586062646668707274767880

828486889092949698100102104

106108110112114116118120

G1

G2

G3

G4

G5

G6

G7

G8

121

122

G9

G1

0G

11

G1

2

MB0MB2MB4MB6MB8MB10MB12MB14MB16MB18MB20MB22MB24MB26MB28MB30MB32MB34MB36MB38


MB80MB82MB84MB86MB88MB90MB92MB94MB96MB98MB100MB102

VCC_MB+3.3VGNDCLKDNCLKDPGNDCLKBNCLKBP

MB1MB3MB5MB7MB9

MB11MB13MB15MB17MB19MB21MB23MB25MB27MB29MB31MB33MB35MB37MB39


MB81MB83MB85MB87MB89MB91MB93MB95MB97MB99

MB101MB103

VCC_MB+3.3VGND

CLKCNCLKCP

GNDCLK_MB_NCLK_MB_P

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

MT

HM

TH

GN

DG

ND

GN

DG

ND

MB10

CLK_DC_A0_QSEp

MB22

MB69

CLK_G2_QSEp

MB12

MB39

MB50

MB54

MB62

MB47

MB0

MB37

MB65

P3.3VD

MB68

CLK_MB48_QSEp

MB25

MB43

CLK_DC_B0_QSEn

MB71

MB42MB45MB44

MB60

MB3

MB24

MB32



11.2 FPGA-FPGA

Multiple point-to-point busses, routed as LVDS pairs, exist between the Stratix-III/IV FPGAs, see Figure 5. Due to the complexity of the interconnect routing, reference the board netlist supplied on the Customer CD ROM to determine the connections.

12 Power Monitors and Reset

The LT6700-1 is configured as a simple window comparator to monitor the power supplies. A Power FAULT will be indicated by the SYS_RSTn signal going active (LOW) and turning on the Reset LED (DS36). The SYS_RSTn signal can also be activated by enabling the Reset Switch (S2). See par 6.3 Power Supply Status LEDs for a description of the power supplies being monitored.

12.1.1 Power Monitor Circuit

The comparators have a built-in 400mV reference and each one has one input available externally, see Figure 37. The comparators are configured as a simple window comparator to detect high/low voltage thresholds. Depending on the FPGA populated, Stratix III/IV, the threshold resistors will be set accordingly.

Figure 37 - Low Voltage Comparator Circuit

12.1.2 Connection between Reset Buffers and FPGAs

The connection between the Reset Buffers and the FPGAs on board are shown in Table 28.

Table 28 - Connection between Reset Buffers and FPGAs

Signal Name Reset Buffer Pin FPGAs

SYS_RSTn_SP_IO U62-7 U25-B16

SYS_RSTn_SP_PROG U62-5 U25-A2 via R654 (Not installed)

SYS_RSTn_MCU U64-5/2 U63-99

1.21VA_trip

C6692.2uF6.3V

R4368.25K

405mV

383mV

U8

LT6700-1SOT95P280-6N

6

15

4

3

2OUTB

OUTAVS

-INB

+INA

GND

P1.1V_VCC_FPGAA

1.1A_FILT

TP39(DNI)COPPERDOT

R446(DNI)

R681K

P3.3VD DS19RED

1.1A_BAD#q

R437300R

P3.3VD

0.99VA_trip

1.1A_BADn

C962.2uF

R43515K

R447

2.0K



13 Power Distribution

The DN7002K10MEG Logic Emulation Board supports a wide range of technologies, from legacy devices like serial ports, to DDR2 SDRAM. This wide range of technologies, including the various FPGA power rails requires a variety of power supplies. These are provided on the DN7002K10MEG Logic Emulation Board using a combination of switching and linear power regulators.

13.1 Stand Alone Operation

An external ATX power supply is used to supply power to the DN7002K10MEG Logic Emulation Board in stand-alone mode, see Figure 39. The external power supply connects to a ―Mini-Fit Jr. Wire-to-Board― header (J6), Molex P/N 39-29-1248.

The user should connect the matching male power connector (24-pin) on the ATX power supply to this header. The DN7002K10MEG Logic Emulation Board has the following shared power supplies; they are generated from the +12V supply on the external power connector (J6).

PSU2 P2.5VD (+2.5V)

PSU4 P1.1V_VCC_FPGAA (+1.1V)

PSU5 P1.1V_VCC_FPGAB (+1.1V)

Any ATX type power supply is adequate. The Dini Group recommends a power supply rated for 300W, see Figure 38.

http://www.molex.com/



Figure 38 - ATX Power Supply

13.1.1 External Power Connector

Figure 39 indicates the connections to the external power connector. This header is polarized to prevent reverse connection and is rated for 600VAC at 6A per contact.

Figure 39 - External Power Connection


P5.0V

P5.0V

P3.3VD

GND

TP41

C3970.1uF

CER

16V20%

C3630.1uF

CER

16V20%

P12V

PS_ONn pg7

C3100.1uF

CER

16V20%


PWR_OKGND

TP1

1

P5.0V

PS_ONn

P3.3VDP3.3VD


GND

TP101

J6

39-29-1248

123456789

10

1314151617181920

2324

11

21

12

22

MTH1MTH2

33G5G5GPOK5SB12

3SNS-12

GEN

GGG-5

5G

12

5

3

5

MTH1MTH2

R2790R

Note: Header J6 is not hot-plug able. Do not attach power while power supply is ON.



14 Daughter Card Headers

The DN7002K10MEG has six 400-pin MEG-Array Daughter Card (DC) headers (P1, P2, P3, P4, P5, and P6), placed on the bottom of the PCB. The DNMEG_INTERCON Daughter Card bridges the expansion signals between two adjacent 400-pin MEG-Array connectors, adding 182 signals for FPGA to FPGA interconnect.

The Stratix III/IV devices support LVDS on both side IO banks and column IO banks. There are true LVDS input and output buffers at side IO banks only. Thus only the Daughter Card banks that connect to the FPGA side IO banks are routed as differential, 50-Ohm transmission lines, see Table 29. These signals are routed as loosely-coupled differential signals, meaning when used differentially, they benefit from the noise-resistant properties of a differential pair, but when used in a single-ended configuration, they do not interfere with each other excessively.

Signals are length matched per Daughter Card header. Other connections on the daughter card connector system include three dedicated, differential clock connections for inputting global clocks from an external source, power connections, bank VCCO power, and a reset signal.

Table 29 - Daughter Card Interconnect

Single-Ended Differential

Daughter Card A0 (P6)

Bank 0 X

Bank 1 X

Bank 2 X

Bank 3 X


Bank 0 X

Bank 1 X

Bank 2 X

Bank 3 X


Bank 0 X

Bank 1 X

Bank 2 X




Bank 3 X

Daughter Card B0 (P3)

Bank 0 X

Bank 1 X

Bank 2 X

Bank 3 X


Bank 0 X

Bank 1 X

Bank 2 X

Bank 3 X


Bank 0 X

Bank 1 X

Bank 2 X

Bank 3 X

14.1 Daughter Card clocking

Refer to par 4.4 Daughter Card (DC) Header Clocks in this User Manual.

14.2 Daughter Card Header Pin Assignments

The pin assignments of the DN7002K10MEG daughter card headers were designed to reduce cross talk to manageable levels while operating at full speed of the Stratix-III/IV LVDS standards.

14.2.1 Daughter Card Header Banks

The daughter card header is divided into four banks, refer to Figure 40. The Stratix-III/IV devices support source-synchronous interfacing with LVDS signaling at up to 1.25Gbps. The ground-to-signal ratio of the connector is 1:1, refer to Figure 40. General purpose IO is arranged in a GSGS pattern to improve signal integrity.

Note: The signal naming convention for the single-ended banks follow differential rules, utilizing p/n format, but are routed as single-ended.



Figure 40 - Daughter Card Header Bank/Pin Assignments



14.2.2 Daughter Card Header to FPGA Interconnect with Stratix-III FPGAs

With the Stratix-III (EP3SL340) FPGAs populated, the Daughter Card Header banks connect to the FPGA banks as shown in Figure 41.

(46)

(46)

DA

UG

HT

ER

CA

RD

(A

0)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

0

BA

NK

1

BA

NK

2

BA

NK

3

TX (12

), R

X (11

)

(44)

DA

UG

HT

ER

CA

RD

(B

0)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

0

BA

NK

1

BA

NK

2

BA

NK

3

DA

UG

HT

ER

CA

RD

(B

1)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

DA

UG

HT

ER

CA

RD

(B

2)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

DA

UG

HT

ER

CA

RD

(A

2)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

DA

UG

HT

ER

CA

RD

(A

1)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

TX (12

), R

X (12

)

(46)

TX (12), RX (11)

TX (1

2), R

X (1

2)

(48)

(44)

(48)

(44)

(46)

TX (12), R

X (11)

TX (12

), R

X (12

)

(46)

(48)

TX (12),

RX (1

1)

TX (12)

, RX (1

2)

(46)

(44)

(48)

(44)

(46)

12

21

22

AB

(12

)-B

A(1

2)

AB

(9)-

BA

(9)

AB

6B

US

(3

8)

AB

(9)-

BA

(9)

AB

(9)-

BA

(9)

AB

(11

)/B

A(1

1)

AB

(6

2)

Pa

irs, B

A (

62

) P

airs

DD

R-I

I S

OD

IMM

4G

B (

20

0P

IN)

SO

DIM

M A

DD

R-I

I S

OD

IMM

4G

B (

20

0P

IN)

SO

DIM

M B

TX

(1

2),

RX

(1

2)

(48

)

Diffe

ren

tia

l T

X/R

X P

airs

Sin

gle

En

de

d S

ign

als

MB

(7

2)

MB

(7

2)

EP

3S

L3

40

F1

76

0

R4

R1

R3

R2

L1

L3

L2

L4

T1

T2

B1

B2

8C

8B

8A

7A

7B

7C

3C

3B

3A

4A

4B

4C

6A

6B

6C

5C

5B

5A

1A

1B

1C

2C

2B

2A

CLK13

CLK15

CLK7

CLK5

CLK4

CLK6CLK12

CLK14

CL

K1

CL

K3

CL

K0

CL

K2

CL

K8

CL

K1

0

CL

K9

CL

K1

1

EP

3S

L3

40

F1

76

0

R4

R1

R3

R2

L1

L3

L2

L4

T1

T2

B1

B2

8C

8B

8A

7A

7B

7C

3C

3B

3A

4A

4B

4C

6A

6B

6C

5C

5B

5A

1A

1B

1C

2C

2B

2A

CLK13

CLK15

CLK7

CLK5

CLK4

CLK6 CLK12

CLK14

CL

K1

CL

K3

CL

K0

CL

K2

CL

K8

CL

K1

0

CL

K9

CL

K1

1

AB

(12)-

BA

(12)

FP

GA

AF

PG

A B

Figure 41 - Daughter Card Header to Stratix-III FPGA Interconnect



14.2.3 Daughter Card Header to FPGA Interconnect with Stratix-IV FPGAs

With the Stratix-IV (EP4SE530) FPGAs populated, the Daughter Card Header banks connect to the FPGA banks as shown in Figure 42.

(46)

(46)

DA

UG

HT

ER

CA

RD

(A

0)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

0

BA

NK

1

BA

NK

2

BA

NK

3

TX (10

), R

X (9)

(28)

DA

UG

HT

ER

CA

RD

(B

0)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

0

BA

NK

1

BA

NK

2

BA

NK

3

DA

UG

HT

ER

CA

RD

(B

1)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

DA

UG

HT

ER

CA

RD

(B

2)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01L

F

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

DA

UG

HT

ER

CA

RD

(A

2)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

DA

UG

HT

ER

CA

RD

(A

1)

ME

G A

RR

AY

– R

ece

pta

cle

(4

00

Pin

)

74

39

0-1

01

LF

BA

NK

3

BA

NK

2

BA

NK

1

BA

NK

0

TX (12

), R

X (12

)

(46)

TX (10), RX (9)

TX (1

2), R

X (1

2)

(48)

(28)

(48)

(28)

(46)

TX (10), R

X (9)

TX (12

), R

X (12

)

(30)

(48)

TX (10),

RX (9

)

TX (12)

, RX (1

2)

(46)

(28)

(48)

(28)

(46)

12

21

22

AB

12

-BA

12

AB

(6)-

BA

(6)

AB

6B

US

(3

8)

AB

(7)-

BA

(7)

AB

(6)-

BA

(6)

AB

(11

)-B

A(1

1)

DD

R-I

I S

OD

IMM

4G

B (

20

0P

IN)

SO

DIM

M A

DD

R-I

I S

OD

IMM

4G

B (

20

0P

IN)

SO

DIM

M B

TX

(1

2),

RX

(1

2)

(48

)

Diffe

ren

tia

l T

X/R

X P

airs

Sin

gle

En

de

d S

ign

als

MB

(4

8)

MB

(4

8)

MB

(4

8)

Re

d in

dic

ate

s s

ign

als

LO

ST

in

Mig

ratio

n fro

m S

tra

tix-I

II (

EP

3S

43

0)

to S

tra

tix-I

V (

EP

4S

E5

30)

EP

4S

E5

30

F1

76

0

R4

R1

R3

R2

L1

L3

L2

L4

T1

T2

B1

B2

8C

8B

8A

7A

7B

7C

3C

3B

3A

4A

4B

4C

6A

6B

6C

5C

5B

5A

1A

1B

1C

2C

2B

2A

CLK13

CLK15

CLK7

CLK5

CLK4

CLK6CLK12

CLK14

CL

K1

CL

K3

CL

K0

CL

K2

CL

K8

CL

K1

0

CL

K9

CL

K1

1

EP

4S

E5

30

F1

76

0

R4

R1

R3

R2

L1

L3

L2

L4

T1

T2

B1

B2

8C

8B

8A

7A

7B

7C

3C

3B

3A

4A

4B

4C

6A

6B

6C

5C

5B

5A

1A

1B

1C

2C

2B

2A

CLK13

CLK15

CLK7

CLK5

CLK4

CLK6 CLK12

CLK14

CL

K1

CL

K3

CL

K0

CL

K2

CL

K8

CL

K1

0

CL

K9

CL

K1

1

AB

(10)-

BA

(10)

AB

(52

) P

airs, B

A(5

2)

Pa

irs

FP

GA

AF

PG

A B

Figure 42 - Daughter Card Header to Stratix-IV FPGA Interconnect



14.3 Special Pins on the Daughter Card Header

14.3.1 GCAp/n, and GCBp/n

The daughter card pin-out defines two bidirectional differential clock pins. These clock signals are intended to be used as differential clock signals. These signals are routed to dedicated clock inputs on the Stratix-III/IV devices and can be used for source-synchronous clocking. Due to clock input constraints on the Stratix-III/IV FPGAs, only GCAp/n is used as a clock on the DN7002K10MEG. This GCAp/n signal pair is routed as differential (LVDS), 100ohm transmission lines, and length matched to the other signals on that specific Daughter Card header.

14.3.2 VCCIO Power Supply

On the Stratix-III/IV FPGA each IO bank has its own VCCIO pins. VCCIO is determined by the IO standard for that particular IO bank. Since a daughter card will not always be present on a daughter card connector, a VCCIO bias generator is used to keep the VCCIO pin on the FPGA within its recommended operating range. The Daughter Card drives VCCIO to the required level for the particular IO standard. The VCCIO impressed by the Daughter Card needs to satisfy the VIH(MAX) of the FPGA on the host board. There are four Adjustable Linear Power Supplies per daughter card header, one for each bank, refer to Figure 43. The bias voltage is set at 1.21V, but can be changed. Reference the datasheet for the LT1963A from Linear Technology on how to adjust the output voltages. R19 allows the user to bypass the power supply if a VCCIO of +3.3V is required, since that voltage can be supplied by the system.

Figure 43 - VCCIO Adjustable Linear Power Supply (x4)

14.3.3 VCCPD Power Supply

VCCPD is either +2.5V, +3.0V, or +3.3V. For a +3.3V IO standard, VCCPD = +3.3V. For a +3.0V IO standard, VCCPD = +3.0V. For +2.5V and below IO standards, VCCPD = +2.5V. Using these power pins to supply the pre-driver power to the output buffers increases the performance of the output pins. There are four VCCPD circuits per daughter card, one for each IO bank, that automatically selects the appropriate VCCPD voltage based on the VCCIO voltage, refer to Figure 44.

R2384.7K

REGDCA0B0ADJ

P3.3VDP2.5VD

C334

4.7uF

R19(DNI)RESC2012N

R18(DNI)RESC2012N

C3334.7uF

C3

51

1000pF

R170RRESC2012N PVIO_DCA0B0

REGDCA0B0BY

C3504.7uF

C327

4.7uFR2425.11R

INSTALL 0

OHM for

3.3V

P3.3REGDCA0B0

TP11(DNI)

Set at 1.21V

1.22V

U45

LT1963CS8SOIC127P600-8N

1

3

6

7

8

4

5

2

OUT

GND1

GND2

GND3

IN

BYP

SHDN#

ADJ

Silkscreen:

"PVIO_DCA0B0"

C315

4.7uF

http://www.linear.com/



Figure 44 - VCCPD Voltage Select Circuit

14.4 Power and Reset

The +3.3V, +5V and +12V power rails can be supplied to the DN7002K10MEG Daughter Card Headers if the fuses are installed, refer to Figure 45. Each pin on the MEG-Array connector is rated to tolerate 1A of current without thermal overload.

Figure 45 - Daughter Card Header Power & RESET

The ―RST_DC_A0n‖ signal is routed from the Configuration FPGA (U25) via an open-drain buffer (U13, U14) and can be used as a RESET to the Daughter Card, refer to Table 30.

Table 30 – Daughter Card Reset

Signal Name OD Buffer Daughter Card Header

RST_DC_A0n U13-7 P6-J2



RST_DC_B0n U14-7 P3-J2


Q3-2FDW2501NZ5

687

R26968R

A0B0

P2.5VD

OUTA_DCA0B0

R2924.7K

405mV

383mV

U47

LT6700-1SOT95P280-6N

6

15

4

3

2OUTB

OUTAVS

-INB

+INA

GND

P12V_FIL_DCA0B0

R293

1K

PVCCPD_DCA0B0

R2564.7K

PVCCPD_DCA0B0R2804.53K

OUTB_DCA0B0

C3810.1uF

CER

16V20%

P12V

Q67-1FDW2501NZ4

2 13

P12V

PVIO_DCA0B0

VTRIP_DCA0B0_2.1V

P12V

GND

TP161

Q3-1FDW2501NZ4

2 13

VTRIP_DCA0B0_2.2V

R2571K

R25 (DNI-0R)

P12V

P3.3VDC_A0

P5.0VDC_A0

F25AFUSE_0429

RST_DC_A0npg7

C14.7uF

P5.0V

P3.3VDF1

5AFUSE_0429

1A per pin

Global

Clock

Pullup required on

daughter card

Stratix III MEG-400

Power/Auxiliary

Section 1 of 6

P6-1

84520-102LF

A1K1

C1H1

B2D2G2

J2

E5F5+12V_1

+12V_2

+5V_1+5V_2

+3.3V_1+3.3V_2+3.3V_3

RSTn

GCCpGCCn

P12VDC_A0CLK_DC_A0nCLK_DC_A0pF6

5AFUSE_0429



Signal Name OD Buffer Daughter Card Header


14.5 FPGA to Daughter Card Header IO Connections

Table 31 lists the input/output interconnect between the Stratix-III/IV FPGAs and the daughter card headers.

Table 31 - FPGA to Daughter Card Header IO Connections

Signal Daughter Card Header FPGA

Daughter Card Header A0 (P6)

DCA0B0NRX0 P6-B4 U9-Y3


DCA0B0NRX10 P6-F13 U9-T5

DCA0B0NRX2 P6-B8 U9-W3

DCA0B0NRX3 P6-B10 U9-V2

DCA0B0NRX4 P6-B12 U9-V1

DCA0B0NRX5 P6-B14 U9-U3

DCA0B0NRX6 P6-B16 U9-T1

DCA0B0NRX7 P6-B18 U9-R1

DCA0B0NRX8 P6-B20 U9-T3

DCA0B0NRX9 P6-F9 U9-V4

DCA0B0NTX0 P6-D4 U9-AA5

DCA0B0NTX1 P6-D6 U9-Y6

DCA0B0NTX10 P6-F7 U9-W11

DCA0B0NTX11 P6-F11 U9-Y12


DCA0B0NTX3 P6-D10 U9-W7


Note: Pins marked with an “x” in the schematic are not available on the Stratix-IV (EP4SE530), see shaded rows in table below:




DCA0B0NTX5 P6-D14 U9-V7

DCA0B0NTX6 P6-D16 U9-U6


DCA0B0NTX8 P6-D20 U9-V9


DCA0B0PRX0 P6-A3 U9-Y4

DCA0B0PRX1 P6-A5 U9-W1

DCA0B0PRX10 P6-E13 U9-T6

DCA0B0PRX2 P6-A7 U9-W4

DCA0B0PRX3 P6-A9 U9-V3

DCA0B0PRX4 P6-A11 U9-U1

DCA0B0PRX5 P6-A13 U9-U4

DCA0B0PRX6 P6-A15 U9-T2

DCA0B0PRX7 P6-A17 U9-R2

DCA0B0PRX8 P6-A19 U9-T4

DCA0B0PRX9 P6-E9 U9-V5

DCA0B0PTX0 P6-C3 U9-AA6

DCA0B0PTX1 P6-C5 U9-Y7

DCA0B0PTX10 P6-E7 U9-W12

DCA0B0PTX11 P6-E11 U9-Y13


DCA0B0PTX3 P6-C9 U9-W8

DCA0B0PTX4 P6-C11 U9-W6

DCA0B0PTX5 P6-C13 U9-V8

DCA0B0PTX6 P6-C15 U9-U7


DCA0B0PTX8 P6-C19 U9-V10

DCA0B0PTX9 P6-C21 U9-Y10

DCA0B1NRX0 P6-J4 U9-J3




DCA0B1NRX1 P6-J6 U9-K3

DCA0B1NRX10 P6-F17 U9-D3

DCA0B1NRX11 P6-F21 U9-F3

DCA0B1NRX2 P6-J8 U9-H3

DCA0B1NRX3 P6-J10 U9-K1

DCA0B1NRX4 P6-J12 U9-J1

DCA0B1NRX5 P6-J14 U9-H1

DCA0B1NRX6 P6-J16 U9-G2

DCA0B1NRX7 P6-J18 U9-F1

DCA0B1NRX8 P6-J20 U9-E3

DCA0B1NRX9 P6-J22 U9-D1

DCA0B1NTX0 P6-G4 U9-R13

DCA0B1NTX1 P6-G6 U9-R11

DCA0B1NTX10 P6-F15 U9-N10

DCA0B1NTX11 P6-F19 U9-P12

DCA0B1NTX2 P6-G8 U9-M8

DCA0B1NTX3 P6-G10 U9-N8


DCA0B1NTX5 P6-G14 U9-L6

DCA0B1NTX6 P6-G16 U9-K5

DCA0B1NTX7 P6-G18 U9-J5


DCA0B1NTX9 P6-G22 U9-G4

DCA0B1PRX0 P6-K3 U9-J4

DCA0B1PRX1 P6-K5 U9-K4

DCA0B1PRX10 P6-E17 U9-C3

DCA0B1PRX11 P6-E21 U9-F4

DCA0B1PRX2 P6-K7 U9-H4

DCA0B1PRX3 P6-K9 U9-K2




DCA0B1PRX4 P6-K11 U9-J2

DCA0B1PRX5 P6-K13 U9-G1

DCA0B1PRX6 P6-K15 U9-G3

DCA0B1PRX7 P6-K17 U9-E1

DCA0B1PRX8 P6-K19 U9-E4

DCA0B1PRX9 P6-K21 U9-D2

DCA0B1PTX0 P6-H3 U9-R14

DCA0B1PTX1 P6-H5 U9-R12

DCA0B1PTX10 P6-E15 U9-N11

DCA0B1PTX11 P6-E19 U9-P13

DCA0B1PTX2 P6-H7 U9-M9

DCA0B1PTX3 P6-H9 U9-N9

DCA0B1PTX4 P6-H11 U9-M7

DCA0B1PTX5 P6-H13 U9-L7

DCA0B1PTX6 P6-H15 U9-K6

DCA0B1PTX7 P6-H17 U9-J6


DCA0B1PTX9 P6-H21 U9-G5

DCA0B2NRX0 P6-B22 U9-D18

DCA0B2NRX1 P6-B24 U9-F20

DCA0B2NRX10 P6-F25 U9-G18

DCA0B2NRX2 P6-B26 U9-B18

DCA0B2NRX3 P6-B28 U9-A19

DCA0B2NRX4 P6-B30 U9-C17

DCA0B2NRX5 P6-B32 U9-F21

DCA0B2NRX6 P6-B34 U9-L19

DCA0B2NRX7 P6-B36 U9-G21

DCA0B2NRX8 P6-B38 U9-C20

DCA0B2NRX9 P6-B40 U9-D16




DCA0B2NTX0 P6-D24 U9-D19

DCA0B2NTX1 P6-D26 U9-J19

DCA0B2NTX10 P6-F27 U9-A15

DCA0B2NTX11 P6-F39 R877-2

DCA0B2NTX2 P6-D28 U9-G19

DCA0B2NTX3 P6-D30 U9-A20

DCA0B2NTX4 P6-D32 U9-D20

DCA0B2NTX5 P6-D34 U9-B15

DCA0B2NTX6 P6-D36 U9-H18

DCA0B2NTX7 P6-D38 U9-A17

DCA0B2NTX8 P6-D40 U9-J18

DCA0B2NTX9 P6-F23 U9-F17

DCA0B2PRX0 P6-A21 U9-E18

DCA0B2PRX1 P6-A23 U9-G20

DCA0B2PRX10 P6-E25 U9-G17

DCA0B2PRX2 P6-A25 U9-C18

DCA0B2PRX3 P6-A27 U9-B19

DCA0B2PRX4 P6-A29 U9-D17

DCA0B2PRX5 P6-A31 U9-K19


DCA0B2PRX7 P6-A35 U9-H21

DCA0B2PRX8 P6-A37 U9-M20


DCA0B2PTX0 P6-C23 U9-E19

DCA0B2PTX1 P6-C25 U9-H19

DCA0B2PTX10 P6-E27 U9-B16

DCA0B2PTX11 P6-E39 R874-2

DCA0B2PTX2 P6-C27 U9-F19

DCA0B2PTX3 P6-C29 U9-A18




DCA0B2PTX4 P6-C31 U9-M19

DCA0B2PTX5 P6-C33 U9-C15

DCA0B2PTX6 P6-C35 U9-K18

DCA0B2PTX7 P6-C37 U9-L18

DCA0B2PTX8 P6-C39 U9-A16

DCA0B2PTX9 P6-E23 U9-F16

DCA0B3NRX0 P6-J24 U9-F7



DCA0B3NRX11 P6-F37 U9-E7

DCA0B3NRX2 P6-J28 U9-A2

DCA0B3NRX3 P6-J30 U9-C4


DCA0B3NRX5 P6-J34 U9-B6


DCA0B3NRX7 P6-J38 U9-B7




DCA0B3NTX1 P6-G26 U9-F8

DCA0B3NTX10 P6-F35 U9-N14


DCA0B3NTX3 P6-G30 U9-F11





DCA0B3NTX8 P6-G40 U9-L13

DCA0B3NTX9 P6-F31 U9-M14




DCA0B3PRX0 P6-K23 U9-F6

DCA0B3PRX1 P6-K25 U9-C6

DCA0B3PRX10 P6-E33 U9-C5

DCA0B3PRX11 P6-E37 U9-E6

DCA0B3PRX2 P6-K27 U9-A3

DCA0B3PRX3 P6-K29 U9-B3

DCA0B3PRX4 P6-K31 U9-B4



DCA0B3PRX7 P6-K37 U9-C8

DCA0B3PRX8 P6-K39 U9-D7

DCA0B3PRX9 P6-E29 U9-E9

DCA0B3PTX0 P6-H23 U9-L12

DCA0B3PTX1 P6-H25 U9-F9

DCA0B3PTX10 P6-E35 U9-M15


DCA0B3PTX3 P6-H29 U9-F10


DCA0B3PTX5 P6-H33 U9-H9



DCA0B3PTX8 P6-H39 U9-K13

DCA0B3PTX9 P6-E31 U9-M13




DCA1B0NRX0 P5-B4 U9-AD1

DCA1B0NRX1 P5-B6 U9-AC3

DCA1B0NRX10 P5-F13 U9-AD5




DCA1B0NRX2 P5-B8 U9-AF3

DCA1B0NRX3 P5-B10 U9-AG3

DCA1B0NRX4 P5-B12 U9-AH1

DCA1B0NRX5 P5-B14 U9-AG1

DCA1B0NRX6 P5-B16 U9-AF1

DCA1B0NRX7 P5-B18 U9-AE2

DCA1B0NRX8 P5-B20 U9-AD3

DCA1B0NRX9 P5-F9 U9-AE4

DCA1B0NTX0 P5-D4 U9-AE6

DCA1B0NTX1 P5-D6 U9-AB5

DCA1B0NTX10 P5-F7 U9-AD11

DCA1B0NTX11 P5-F11 U9-AC12

DCA1B0NTX2 P5-D8 U9-AD13

DCA1B0NTX3 P5-D10 U9-AE9

DCA1B0NTX4 P5-D12 U9-AG5

DCA1B0NTX5 P5-D14 U9-AF6



DCA1B0NTX8 P5-D20 U9-AC9

DCA1B0NTX9 P5-D22 U9-AB7

DCA1B0PRX0 P5-A3 U9-AC1

DCA1B0PRX1 P5-A5 U9-AC4

DCA1B0PRX10 P5-E13 U9-AD6

DCA1B0PRX2 P5-A7 U9-AF4

DCA1B0PRX3 P5-A9 U9-AG4

DCA1B0PRX4 P5-A11 U9-AH2

DCA1B0PRX5 P5-A13 U9-AG2

DCA1B0PRX6 P5-A15 U9-AE1

DCA1B0PRX7 P5-A17 U9-AE3




DCA1B0PRX8 P5-A19 U9-AD4

DCA1B0PRX9 P5-E9 U9-AE5

DCA1B0PTX0 P5-C3 U9-AE7

DCA1B0PTX1 P5-C5 U9-AB6

DCA1B0PTX10 P5-E7 U9-AD12

DCA1B0PTX11 P5-E11 U9-AC13

DCA1B0PTX2 P5-C7 U9-AD14

DCA1B0PTX3 P5-C9 U9-AE10

DCA1B0PTX4 P5-C11 U9-AG6

DCA1B0PTX5 P5-C13 U9-AF7



DCA1B0PTX8 P5-C19 U9-AC10

DCA1B0PTX9 P5-C21 U9-AB8

DCA1B1NRX0 P5-J4 U9-AW14


DCA1B1NRX10 P5-F17 U9-AW11

DCA1B1NRX11 P5-F21 U9-AV12

DCA1B1NRX2 P5-J8 U9-BA12

DCA1B1NRX3 P5-J10 U9-BB14







DCA1B1NTX0 P5-G4 U9-AL18

DCA1B1NTX1 P5-G6 U9-AN16

DCA1B1NTX10 P5-F15 U9-AM15




DCA1B1NTX11 P5-F19 U9-AL17


DCA1B1NTX3 P5-G10 U9-AP16

DCA1B1NTX4 P5-G12 U9-AT16

DCA1B1NTX5 P5-G14 U9-AV15

DCA1B1NTX6 P5-G16 U9-AR15




DCA1B1PRX0 P5-K3 U9-AW13

DCA1B1PRX1 P5-K5 U9-AY14

DCA1B1PRX10 P5-E17 U9-AW10

DCA1B1PRX11 P5-E21 U9-AU12


DCA1B1PRX3 P5-K9 U9-BB13







DCA1B1PTX0 P5-H3 U9-AK17

DCA1B1PTX1 P5-H5 U9-AN17

DCA1B1PTX10 P5-E15 U9-AM16

DCA1B1PTX11 P5-E19 U9-AL16


DCA1B1PTX3 P5-H9 U9-AR16

DCA1B1PTX4 P5-H11 U9-AT15

DCA1B1PTX5 P5-H13 U9-AU15







DCA1B1PTX9 P5-H21 U9-AP14

DCA1B2NRX0 P5-B22 U9-AU4

DCA1B2NRX1 P5-B24 U9-AY3

DCA1B2NRX10 P5-F25 U9-AP3


DCA1B2NRX2 P5-B26 U9-AW1

DCA1B2NRX3 P5-B28 U9-AV1


DCA1B2NRX5 P5-B32 U9-AT1


DCA1B2NRX7 P5-B36 U9-AP1

DCA1B2NRX8 P5-B38 U9-AR3

DCA1B2NRX9 P5-B40 U9-AN3

DCA1B2NTX0 P5-D24 U9-AL11

DCA1B2NTX1 P5-D26 U9-AP5

DCA1B2NTX10 P5-F27 U9-AH13

DCA1B2NTX11 P5-F39 U9-AK12

DCA1B2NTX2 P5-D28 U9-AN5

DCA1B2NTX3 P5-D30 U9-AM6


DCA1B2NTX5 P5-D34 U9-AK7

DCA1B2NTX6 P5-D36 U9-AK9

DCA1B2NTX7 P5-D38 U9-AJ10

DCA1B2NTX8 P5-D40 U9-AH11

DCA1B2NTX9 P5-F23 U9-AJ12

DCA1B2PRX0 P5-A21 U9-AU5




DCA1B2PRX1 P5-A23 U9-AW3

DCA1B2PRX10 P5-E25 U9-AP4

DCA1B2PRX11 P5-E3 U9-AV4




DCA1B2PRX5 P5-A31 U9-AR1

DCA1B2PRX6 P5-A33 U9-AT4

DCA1B2PRX7 P5-A35 U9-AP2


DCA1B2PRX9 P5-A39 U9-AN4

DCA1B2PTX0 P5-C23 U9-AL12

DCA1B2PTX1 P5-C25 U9-AP6

DCA1B2PTX10 P5-E27 U9-AH14

DCA1B2PTX11 P5-E39 U9-AK13

DCA1B2PTX2 P5-C27 U9-AN6

DCA1B2PTX3 P5-C29 U9-AM7


DCA1B2PTX5 P5-C33 U9-AK8



DCA1B2PTX8 P5-C39 U9-AH12

DCA1B2PTX9 P5-E23 U9-AJ13

DCA1B3NRX0 P5-J24 U9-AU7


DCA1B3NRX10 P5-F33 U9-AY4



DCA1B3NRX3 P5-J30 U9-AY8









DCA1B3NRX9 P5-F29 U9-BB3

DCA1B3NTX0 P5-G24 U9-AK15


DCA1B3NTX10 P5-F35 U9-AP9






DCA1B3NTX7 P5-G38 U9-AU11


DCA1B3NTX9 P5-F31 U9-AU9

DCA1B3PRX0 P5-K23 U9-AU6




DCA1B3PRX2 P5-K27 U9-AV9


DCA1B3PRX4 P5-K31 U9-BA6





DCA1B3PRX9 P5-E29 U9-BB2




DCA1B3PTX0 P5-H23 U9-AK14

DCA1B3PTX1 P5-H25 U9-AL13

DCA1B3PTX10 P5-E35 U9-AR9

DCA1B3PTX2 P5-H27 U9-AM13







DCA1B3PTX9 P5-E31 U9-AU8


DCA2B0NRX0 P4-B4 U9-BB28


DCA2B0NRX10 P4-F13 U9-AY26






DCA2B0NRX7 P4-B18 U9-AR25

DCA2B0NRX8 P4-B20 U9-BA28


DCA2B0NTX0 P4-D4 U9-AT24

DCA2B0NTX1 P4-D6 U9-AU23

DCA2B0NTX10 P4-F7 U9-AT26

DCA2B0NTX11 P4-F11 R866-2

DCA2B0NTX11R U9-H40 R866-1

DCA2B0NTX2 P4-D8 U9-AW24




DCA2B0NTX3 P4-D10 U9-BA25




DCA2B0NTX7 P4-D18 U9-AT22



DCA2B0PRX0 P4-A3 U9-BA27

DCA2B0PRX1 P4-A5 U9-BB26



DCA2B0PRX3 P4-A9 U9-BA24

DCA2B0PRX4 P4-A11 U9-AV25



DCA2B0PRX7 P4-A17 U9-AP25

DCA2B0PRX8 P4-A19 U9-AY28


DCA2B0PTX0 P4-C3 U9-AT23

DCA2B0PTX1 P4-C5 U9-AU24

DCA2B0PTX10 P4-E7 U9-AU26

DCA2B0PTX11 P4-E11 R867-2

DCA2B0PTX11R U9-H39 R867-1

DCA2B0PTX2 P4-C7 U9-AV24

DCA2B0PTX3 P4-C9 U9-AY25


DCA2B0PTX5 P4-C13 U9-AR24


DCA2B0PTX7 P4-C17 U9-AR22






DCA2B1NRX0 P4-J4 U9-AV36

DCA2B1NRX1 P4-J6 U9-AV37


DCA2B1NRX11 P4-F21 U9-AU35





















DCA2B1PRX0 P4-K3 U9-AU36















DCA2B1PTX0 P4-H3 U9-AL29


DCA2B1PTX10 P4-E15 U9-AM31

DCA2B1PTX11 P4-E19 U9-AK29











DCA2B2NRX10 P4-F25 U9-BB17

DCA2B2NRX11_GCB P4-F3 U9-AY21













DCA2B2NTX1 P4-D26 U9-AR19

DCA2B2NTX10 P4-F27 U9-BB16

DCA2B2NTX11 R859-1 P4-F39

DCA2B2NTX11R R859-2 U9-AL25


DCA2B2NTX3 P4-D30 U9-AV19






DCA2B2NTX9 P4-F23 U9-AR18



DCA2B2PRX10 P4-E25 U9-BA16

DCA2B2PRX11_GCB P4-E3 U9-AW21














DCA2B2PTX10 P4-E27 U9-BB15

DCA2B2PTX11 R858-1 P4-E39

DCA2B2PTX11R R858-2 U9-AK26


DCA2B2PTX3 P4-C29 U9-AW19





DCA2B2PTX8 P4-C39 U9-AU16

DCA2B2PTX9 P4-E23 U9-AP18













DCA2B3NTX0 P4-G24 U9-AM28













DCA2B3NTX9 P4-F31 U9-AM27

DCA2B3PRX0 P4-K23 U9-AV33











DCA2B3PRX9 P4-E29 U9-AY29



DCA2B3PTX10 P4-E35 U9-AL26











DCA2B3PTX9 P4-E31 U9-AN27

Daughter Card Header B0 (P3)

DCB0B0NRX0 P3-B4 U10-AD1

DCB0B0NRX1 P3-B6 U10-AC3

DCB0B0NRX10 P3-F13 U10-AD5

DCB0B0NRX2 P3-B8 U10-AF3

DCB0B0NRX3 P3-B10 U10-AG3

DCB0B0NRX4 P3-B12 U10-AH1

DCB0B0NRX5 P3-B14 U10-AG1

DCB0B0NRX6 P3-B16 U10-AF1

DCB0B0NRX7 P3-B18 U10-AE2

DCB0B0NRX8 P3-B20 U10-AD3

DCB0B0NRX9 P3-F9 U10-AE4

DCB0B0NTX0 P3-D4 U10-AE6

DCB0B0NTX1 P3-D6 U10-AB5

DCB0B0NTX10 P3-F7 U10-AD11

DCB0B0NTX11 P3-F11 U10-AC12

DCB0B0NTX2 P3-D8 U10-AD13

DCB0B0NTX3 P3-D10 U10-AE9

DCB0B0NTX4 P3-D12 U10-AG5

DCB0B0NTX5 U10-AF6 P3-D14



DCB0B0NTX8 P3-D20 U10-AC9

DCB0B0NTX9 P3-D22 U10-AB7

DCB0B0PRX0 P3-A3 U10-AC1

DCB0B0PRX1 P3-A5 U10-AC4

DCB0B0PRX10 P3-E13 U10-AD6

DCB0B0PRX2 P3-A7 U10-AF4




DCB0B0PRX3 P3-A9 U10-AG4

DCB0B0PRX4 P3-A11 U10-AH2

DCB0B0PRX5 P3-A13 U10-AG2

DCB0B0PRX6 P3-A15 U10-AE1

DCB0B0PRX7 P3-A17 U10-AE3

DCB0B0PRX8 P3-A19 U10-AD4

DCB0B0PRX9 P3-E9 U10-AE5

DCB0B0PTX0 P3-C3 U10-AE7

DCB0B0PTX1 P3-C5 U10-AB6

DCB0B0PTX10 P3-E7 U10-AD12

DCB0B0PTX11 P3-E11 U10-AC13

DCB0B0PTX2 P3-C7 U10-AD14

DCB0B0PTX3 P3-C9 U10-AE10

DCB0B0PTX4 P3-C11 U10-AG6

DCB0B0PTX5 P3-C13 U10-AF7



DCB0B0PTX8 P3-C19 U10-AC10

DCB0B0PTX9 P3-C21 U10-AB8

DCB0B1NRX0 P3-J4 U10-BB20

DCB0B1NRX1 P3-J6 U10-AT20

DCB0B1NRX10 P3-F17 U10-BB16

DCB0B1NRX11 P3-F21 U10-AU18

DCB0B1NRX2 P3-J8 U10-AP20

DCB0B1NRX3 P3-J10 U10-AV19


DCB0B1NRX5 P3-J14 U10-AM18

DCB0B1NRX6 P3-J16 U10-AW20

DCB0B1NRX7 P3-J18 U10-AV21




DCB0B1NRX8 P3-J20 U10-AL20

DCB0B1NRX9 P3-J22 U10-AP18

DCB0B1NTX0 P3-G4 U10-BB19

DCB0B1NTX1 P3-G6 U10-BA18

DCB0B1NTX10 P3-F15 U10-AT17

DCB0B1NTX11 P3-F19 R876-2

DCB0B1NTX2 P3-G8 U10-AU19

DCB0B1NTX3 P3-G10 U10-AW19

DCB0B1NTX4 P3-G12 U10-AN18

DCB0B1NTX5 P3-G14 U10-AY17


DCB0B1NTX7 P3-G18 U10-AV16


DCB0B1NTX9 P3-G22 U10-BA16

DCB0B1PRX0 P3-K3 U10-BB18

DCB0B1PRX1 P3-K5 U10-AN20

DCB0B1PRX10 P3-E17 U10-AM19

DCB0B1PRX11 P3-E21 U10-AU16

DCB0B1PRX2 P3-K7 U10-AR19

DCB0B1PRX3 P3-K9 U10-AV18

DCB0B1PRX4 P3-K11 U10-AW21

DCB0B1PRX5 P3-K13 U10-AT21



DCB0B1PRX8 P3-K19 U10-AY20

DCB0B1PRX9 P3-K21 U10-AN19

DCB0B1PTX0 P3-H3 U10-BA19

DCB0B1PTX1 P3-H5 U10-AY18

DCB0B1PTX10 P3-E15 U10-AU17




DCB0B1PTX11 P3-E19 R875-2

DCB0B1PTX2 P3-H7 U10-AT19

DCB0B1PTX3 P3-H9 U10-AW18


DCB0B1PTX5 P3-H13 U10-AL21

DCB0B1PTX6 P3-H15 U10-AU21


DCB0B1PTX8 P3-H19 U10-BA15

DCB0B1PTX9 P3-H21 U10-BB15

DCB0B2NRX0 P3-B22 U10-AU4

DCB0B2NRX1 P3-B24 U10-AY3

DCB0B2NRX10 P3-F25 U10-AP3

DCB0B2NRX11 P3-F3 U10-AV3

DCB0B2NRX2 P3-B26 U10-AW1

DCB0B2NRX3 P3-B28 U10-AV1

DCB0B2NRX4 P3-B30 U10-AU2

DCB0B2NRX5 P3-B32 U10-AT1

DCB0B2NRX6 P3-B34 U10-AT3

DCB0B2NRX7 P3-B36 U10-AP1

DCB0B2NRX8 P3-B38 U10-AR3

DCB0B2NRX9 P3-B40 U10-AN3

DCB0B2NTX0 P3-D24 U10-AL11

DCB0B2NTX1 P3-D26 U10-AP5

DCB0B2NTX10 P3-F27 U10-AH13

DCB0B2NTX11 P3-F39 U10-AK12

DCB0B2NTX2 P3-D28 U10-AN5

DCB0B2NTX3 P3-D30 U10-AM6

DCB0B2NTX4 P3-D32 U10-AL6

DCB0B2NTX5 P3-D34 U10-AK7




DCB0B2NTX6 P3-D36 U10-AK9

DCB0B2NTX7 P3-D38 U10-AJ10

DCB0B2NTX8 P3-D40 U10-AH11

DCB0B2NTX9 P3-F23 U10-AJ12

DCB0B2PRX0 P3-A21 U10-AU5

DCB0B2PRX1 P3-A23 U10-AW3

DCB0B2PRX10 P3-E25 U10-AP4

DCB0B2PRX11 P3-E3 U10-AV4

DCB0B2PRX2 P3-A25 U10-AW2



DCB0B2PRX5 P3-A31 U10-AR1

DCB0B2PRX6 P3-A33 U10-AT4

DCB0B2PRX7 P3-A35 U10-AP2

DCB0B2PRX8 P3-A37 U10-AR4

DCB0B2PRX9 P3-A39 U10-AN4

DCB0B2PTX0 P3-C23 U10-AL12

DCB0B2PTX1 P3-C25 U10-AP6

DCB0B2PTX10 P3-E27 U10-AH14

DCB0B2PTX11 P3-E39 U10-AK13

DCB0B2PTX2 P3-C27 U10-AN6

DCB0B2PTX3 P3-C29 U10-AM7

DCB0B2PTX4 P3-C31 U10-AL7

DCB0B2PTX5 P3-C33 U10-AK8



DCB0B2PTX8 P3-C39 U10-AH12

DCB0B2PTX9 P3-E23 U10-AJ13

DCB0B3NRX0 P3-J24 U10-AU7





DCB0B3NRX10 P3-F33 U10-AY4

DCB0B3NRX11 P3-F37 U10-AV7


DCB0B3NRX3 P3-J30 U10-AY8

DCB0B3NRX4 P3-J32 U10-BA7


DCB0B3NRX6 P3-J36 U10-AY6


DCB0B3NRX8 P3-J40 U10-BA4

DCB0B3NRX9 P3-F29 U10-BB3

DCB0B3NTX0 P3-G24 U10-AK15

DCB0B3NTX1 P3-G26 U10-AL14

DCB0B3NTX10 P3-F35 U10-AP9



DCB0B3NTX4 P3-G32 U10-AP10

DCB0B3NTX5 P3-G34 U10-AR12

DCB0B3NTX6 P3-G36 U10-AT10

DCB0B3NTX7 P3-G38 U10-AU11

DCB0B3NTX8 P3-G40 U10-AT9

DCB0B3NTX9 P3-F31 U10-AU9

DCB0B3PRX0 P3-K23 U10-AU6


DCB0B3PRX10 P3-E33 U10-AW5

DCB0B3PRX11 P3-E37 U10-AV6

DCB0B3PRX2 P3-K27 U10-AV9


DCB0B3PRX4 P3-K31 U10-BA6





DCB0B3PRX6 P3-K35 U10-AY5


DCB0B3PRX8 P3-K39 U10-BA3

DCB0B3PRX9 P3-E29 U10-BB2

DCB0B3PTX0 P3-H23 U10-AK14

DCB0B3PTX1 P3-H25 U10-AL13

DCB0B3PTX10 P3-E35 U10-AR9

DCB0B3PTX2 P3-H27 U10-AM13

DCB0B3PTX3 P3-H29 U10-AM12

DCB0B3PTX4 P3-H31 U10-AN10


DCB0B3PTX6 P3-H35 U10-AR10

DCB0B3PTX7 P3-H37 U10-AU10


DCB0B3PTX9 P3-E31 U10-AU8


DCB1B0NRX0 P2-B4 U10-Y3

DCB1B0NRX1 P2-B6 U10-Y1

DCB1B0NRX10 P2-F13 U10-T5

DCB1B0NRX2 P2-B8 U10-W3

DCB1B0NRX3 P2-B10 U10-V2

DCB1B0NRX4 P2-B12 U10-V1

DCB1B0NRX5 P2-B14 U10-U3

DCB1B0NRX6 P2-B16 U10-T1

DCB1B0NRX7 P2-B18 U10-R1

DCB1B0NRX8 P2-B20 U10-T3

DCB1B0NRX9 P2-F9 U10-V4

DCB1B0NTX0 P2-D4 U10-AA5




DCB1B0NTX1 P2-D6 U10-Y6

DCB1B0NTX10 P2-F7 U10-W11

DCB1B0NTX11 P2-F11 U10-Y12


DCB1B0NTX3 P2-D10 U10-W9




DCB1B0NTX7 P2-D18 U10-V7

DCB1B0NTX8 P2-D20 U10-U6

DCB1B0NTX9 P2-D22 U10-V9

DCB1B0PRX0 P2-A3 U10-Y4

DCB1B0PRX1 P2-A5 U10-W1

DCB1B0PRX10 P2-E13 U10-T6

DCB1B0PRX2 P2-A7 U10-W4

DCB1B0PRX3 P2-A9 U10-V3

DCB1B0PRX4 P2-A11 U10-U1

DCB1B0PRX5 P2-A13 U10-U4

DCB1B0PRX6 P2-A15 U10-T2

DCB1B0PRX7 P2-A17 U10-R2

DCB1B0PRX8 P2-A19 U10-T4

DCB1B0PRX9 P2-E9 U10-V5

DCB1B0PTX0 P2-C3 U10-AA6

DCB1B0PTX1 P2-C5 U10-Y7

DCB1B0PTX10 P2-E7 U10-W12

DCB1B0PTX11 P2-E11 U10-Y13


DCB1B0PTX3 P2-C9 U10-Y10





DCB1B0PTX5 P2-C13 U10-W8

DCB1B0PTX6 P2-C15 U10-W6

DCB1B0PTX7 P2-C17 U10-V8

DCB1B0PTX8 P2-C19 U10-U7

DCB1B0PTX9 P2-C21 U10-V10

DCB1B1NRX0 P2-J4 U10-J3

DCB1B1NRX1 P2-J6 U10-K3

DCB1B1NRX10 P2-F17 U10-D3

DCB1B1NRX11 P2-F21 U10-F3

DCB1B1NRX2 P2-J8 U10-H3

DCB1B1NRX3 P2-J10 U10-K1

DCB1B1NRX4 P2-J12 U10-J1

DCB1B1NRX5 P2-J14 U10-H1

DCB1B1NRX6 P2-J16 U10-G2

DCB1B1NRX7 P2-J18 U10-F1

DCB1B1NRX8 P2-J20 U10-E3

DCB1B1NRX9 P2-J22 U10-D1

DCB1B1NTX0 P2-G4 U10-R13

DCB1B1NTX1 P2-G6 U10-R11

DCB1B1NTX10 P2-F15 U10-N10

DCB1B1NTX11 P2-F19 U10-P12

DCB1B1NTX2 P2-G8 U10-M8

DCB1B1NTX3 P2-G10 U10-N8


DCB1B1NTX5 P2-G14 U10-L6

DCB1B1NTX6 P2-G16 U10-K5

DCB1B1NTX7 P2-G18 U10-J5


DCB1B1NTX9 P2-G22 U10-G4




DCB1B1PRX0 P2-K3 U10-J4

DCB1B1PRX1 P2-K5 U10-K4

DCB1B1PRX10 P2-E17 U10-C3

DCB1B1PRX11 P2-E21 U10-F4

DCB1B1PRX2 P2-K7 U10-H4

DCB1B1PRX3 P2-K9 U10-K2

DCB1B1PRX4 P2-K11 U10-J2

DCB1B1PRX5 P2-K13 U10-G1

DCB1B1PRX6 P2-K15 U10-G3

DCB1B1PRX7 P2-K17 U10-E1


DCB1B1PRX9 P2-K21 U10-D2

DCB1B1PTX0 P2-H3 U10-R14

DCB1B1PTX1 P2-H5 U10-R12

DCB1B1PTX10 P2-E15 U10-N11

DCB1B1PTX11 P2-E19 U10-P13

DCB1B1PTX2 P2-H7 U10-M9

DCB1B1PTX3 P2-H9 U10-N9


DCB1B1PTX5 P2-H13 U10-L7

DCB1B1PTX6 P2-H15 U10-K6

DCB1B1PTX7 P2-H17 U10-J6


DCB1B1PTX9 P2-H21 U10-G5

DCB1B2NRX0 P2-B22 U10-F7

DCB1B2NRX1 P2-B24 U10-D6


DCB1B2NRX11 P2-F3 U10-J11

DCB1B2NRX2 P2-B26 U10-A2




DCB1B2NRX3 P2-B28 U10-C4


DCB1B2NRX5 P2-B32 U10-B6





DCB1B2NTX0 P2-D24 U10-M12

DCB1B2NTX1 P2-D26 U10-F8

DCB1B2NTX10 P2-F27 U10-N14

DCB1B2NTX11 P2-F39 U10-E7

DCB1B2NTX2 P2-D28 U10-G8



DCB1B2NTX5 P2-D34 U10-J9

DCB1B2NTX6 P2-D36 U10-K10


DCB1B2NTX8 P2-D40 U10-L13

DCB1B2NTX9 P2-F23 U10-M14

DCB1B2PRX0 P2-A21 U10-F6

DCB1B2PRX1 P2-A23 U10-C6

DCB1B2PRX10 P2-E25 U10-C5

DCB1B2PRX11 P2-E3 U10-K11

DCB1B2PRX2 P2-A25 U10-A3

DCB1B2PRX3 P2-A27 U10-B3








DCB1B2PRX8 P2-A37 U10-D7

DCB1B2PRX9 P2-A39 U10-E9

DCB1B2PTX0 P2-C23 U10-L12

DCB1B2PTX1 P2-C25 U10-F9

DCB1B2PTX10 P2-E27 U10-M15

DCB1B2PTX11 P2-E39 U10-E6

DCB1B2PTX2 P2-C27 U10-G9



DCB1B2PTX5 P2-C33 U10-H9

DCB1B2PTX6 P2-C35 U10-J10


DCB1B2PTX8 P2-C39 U10-K13

DCB1B2PTX9 P2-E23 U10-M13


DCB1B3NRX1 P2-J26 U10-A8

DCB1B3NRX10 P2-F33 U10-E12


DCB1B3NRX2 P2-J28 U10-C9




DCB1B3NRX6 P2-J36 U10-B13






DCB1B3NTX10 P2-F35 U10-L16




DCB1B3NTX2 P2-G28 U10-H13

DCB1B3NTX3 P2-G30 U10-E13

DCB1B3NTX4 P2-G32 U10-E15





DCB1B3NTX9 P2-F31 U10-J14


DCB1B3PRX1 P2-K25 U10-A9

DCB1B3PRX10 P2-E33 U10-F12

DCB1B3PRX11 P2-E37 U10-E10

DCB1B3PRX2 P2-K27 U10-B9





DCB1B3PRX7 P2-K37 U10-C12


DCB1B3PRX9 P2-E29 U10-D12



DCB1B3PTX10 P2-E35 U10-L15


DCB1B3PTX3 P2-H29 U10-F13




DCB1B3PTX7 P2-H37 U10-H15





DCB1B3PTX9 P2-E31 U10-J13




DCB2B0NRX10 P1-F13 U10-A17

DCB2B0NRX2 P1-B8 U10-E19

DCB2B0NRX3 P1-B10 U10-J19




DCB2B0NRX7 P1-B18 U10-L18



DCB2B0NTX0 P1-D4 U10-E18


DCB2B0NTX10 P1-F7 U10-C17

DCB2B0NTX11 P1-F11 R865-2

DCB2B0NTX11R U10-AH30 R865-1


DCB2B0NTX3 P1-D10 U10-C18





DCB2B0NTX8 P1-D20 U10-M20

DCB2B0NTX9 P1-D22 U10-H21






DCB2B0PRX10 P1-E13 U10-B16


DCB2B0PRX3 P1-A9 U10-H19


DCB2B0PRX5 P1-A13 U10-F21


DCB2B0PRX7 P1-A17 U10-L19


DCB2B0PRX9 P1-E9 U10-A16

DCB2B0PTX0 P1-C3 U10-D18


DCB2B0PTX10 P-E7 U10-D17

DCB2B0PTX11 P1-E11 R864-2

DCB2B0PTX11R U10-AH29 R864-1


DCB2B0PTX3 P1-C9 U10-B18

DCB2B0PTX4 P1-C11 U10-H18




DCB2B0PTX8 P1-C19 U10-M19





DCB2B1NRX11 P1-F21 U10-E33














DCB2B1NTX10 P1-F15 U10-G31

DCB2B1NTX11 P1-F19 U10-L28







DCB2B1NTX8 P1-G20 U10-F30



















DCB2B1PTX10 P1-E15 U10-H30

DCB2B1PTX11 P1-E19 U10-K28








DCB2B1PTX9 P1-H21 U10-E31




DCB2B2NRX11_GCB P1-F3 U10-C22





DCB2B2NRX6 P1-B34 U10-G22

DCB2B2NRX7 P1-B36 U10-M23

DCB2B2NRX8 P1-B38 U10-F22




DCB2B2NTX10 P1-F27 U10-E25

DCB2B2NTX11 R861-1 P1-F39

DCB2B2NTX11R R861-2 U10-N17




DCB2B2NTX2 P1-D28 U10-E24

DCB2B2NTX3 P1-D30 U10-B24

DCB2B2NTX4 P1-D32 U10-A28





DCB2B2NTX9 P1-F23 U10-M24




DCB2B2PRX11_GCB P1-E3 U10-D22





DCB2B2PRX6 P1-A33 U10-H22

DCB2B2PRX7 P1-A35 U10-M22





DCB2B2PTX10 P1-E27 U10-F25

DCB2B2PTX11 R860-1 P1-E39

DCB2B2PTX11R R860-2 U10-M18


DCB2B2PTX3 P1-C29 U10-C25

DCB2B2PTX4 P1-C31 U10-B28








DCB2B2PTX9 P1-E23 U10-L24

DCB2B3NRX0 P1-J24 U10-F37



DCB2B3NRX11 P1-F37 U10-F36











DCB2B3NTX10 P1-F35 U10-K33








DCB2B3NTX9 P1-F31 U10-H34







DCB2B3PRX11 P1-E37 U10-E36








DCB2B3PRX9 P1-E29 U10-A40

DCB2B3PTX0 P1-H23 U10-N28


DCB2B3PTX10 P1-E35 U10-J33


DCB2B3PTX3 P1-H29 U10-L30






DCB2B3PTX9 P1-E31 U10-G35

14.6 Insertion/Removal of Daughter Card

Due to the high density MEG-Array connectors, the pins on the plug and receptacle of the MEG-Array connectors are very delicate. When plugging in a daughter card, make sure to align the daughter card first before pressing on the connector. Be absolutely certain that both the small and the large keys at the narrow ends of the MEG-Array headers line up BEFORE applying pressure to mate the connectors!



Place it down flat, then press down gently.



14.7 MEG-Array Specifications

Manufacturer FCI

Part Number 84520-102LF – Bottom Plug (P1, P2, P3, P4, P5, P6)

RoHS Lead Free Compatible

yes

Total Number Of Positions 400

Contact Area Plating 0.76 µm (30 µin.) gold over 0.76 µm (30 µin.) nickel

Mating Force 30 grams per contact average

Unmating Force 20 grams per contact average

Insulation Resistance 1000 M ohms

Withstanding Voltage 200 VAC

Current Rating 0.45 amps

Contact Resistance 20 to 25 m ohms max (initial), 10 m ohms max increase (after testing)

Temperature Range -40 °C to +85 °C

Trademark MEG-Array®

Approvals and Certification UL and CSA approved

Product Specification GSe -12-100, from FCI websit

Pick-up Cap yes

Housing Material LCP

Contact Material Copper Alloy

Durability (Mating Cycles) 50



15 Mechanical

15.1 Board Dimensions

The DN7002K10MEG Logic Emulation Board measures approximately 166.5mm x 352.5mm. Two bus bars, MP1 and MP2 are installed to prevent flexing of the PWB. They are connected to the ground plane and can be used to ground test equipment. The user must not short any power rails or signals to these metal bars - they can conduct a lot of current. Mounting holes are provided to allow the PCB to be mounted in a case.



15.2 PCB and Chassis Support

A chassis plate is provided to allow mechanical support for the Daughter Cards, see picture below (an assembly drawing is available upon request):



15.3 Standard Daughter Card Size

The DN7002K10MEG Logic Emulation Board provides mounting hole locations for a Daughter Card with the dimensions given below. The DNMEG_Obs Daughter Card product conforms to these dimensions.

15.4 Daughter Card Spacing

With this host-plate-daughter card arrangement, there is a limited Z dimension clearance for backside components on the daughter card. This dimension is determined by the daughter card designer‘s part selection for the MEG-Array receptacle.

View: Top Side

400-Pin Receptacle on Back

P/N: 74390-101

A1

0.5

00"

0.7

50"

1.950"

3.2

50"

4.2

50"

0.500"

5.0

00"

2.75"

0.5

00

"

0.7

50

"

1.950"

3.2

50

"

4.2

50

"

0.500"

5.0

00"

2.75"

View: Top Side

300-Pin Receptacle on Back

P/N: 84553-101

A1

Type 2 Short Type 0/1/4 Short

http://www.dinigroup.com/DNMEG_Obs.php

http://www.dinigroup.com/DNMEG_Obs.php



Note that the components on the topside of the daughter card and DN7002K10MEG face in opposite directions.

A P P E N D I X


Appendix

16 Appendix A: QSF File

See the Customer CD ROM for the QUARTUS Setting Files (QSF).

17 Using Daughter Card Clocks (main.txt)

Configuring the hardware to select the Daughter Card Clocks using CompactFlash and ―main.txt‖ has not been implemented on this product. The Clock Buffer can be configured using the ―Writes to a configuration Register‖ command. This command can be used to access features that do not have a main.txt command. Example applications include setting clock sources, setting the EXT0 or EXT1 clock buffers to zero-delay mode, or setting the clocks to frequencies lower than 31MHz.

Clock Buffer Registers

DC A0/SMA (U1): 0xDF24

DC B0/SMA (U4): 0xDF41

DC A2/B1 (U37): 0xDF25

DC B2/A1 (U38): 0xDF42

Memory Mapped Register (for all 4 registers below):

[0]: clksel (default 0)

[1]: pllsel (default 0)

[2]: SEL0 (default 1)


Chapter

6




[5:7]: unused

Configuring Clock Buffer

Configuring the clock buffer (U1) to select Daughter Card A0 clock input (CLK_DC_A0p/n), add the following line to the ―main.txt‖ configuration file.

MEMORY MAPPED: 0xDF24 0x00

Please see the datasheet of the Clock Buffer (ICS8745B) for more information on configuring specific device functions.

18 Ordering Information

Request quotes by emailing [email protected]. For technical questions email [email protected].

19 Optional Equipment

The following tools are suggested for use with the DN7002K10MEG Logic Emulation Board.

19.1 Compatible Dini Group Products

The Dini Group supplies standard Daughter Cards and Memory modules that can be use with the DN7002K10MEG. See http://www.dinigroup.com for a complete listing.

19.1.1 Memories

The Memory Module solutions from The Dini Group:

DNSODM200_SRAM Memory module for use in the 200-pin SODIMM sockets. Standard memory configuration: Two GS8320V32 memories (1M x 32 each) Performance up to 175Mhz (SDR) Small EPROM. Contact us about ―zero bus latency‖ type parts.

DNSODM200_RLDRAM Reduced latency DRAM (Micron) 64 bit wide Compatible with the 200-pin SODIMM sockets. Small EPROM.

DNSODM200_MICTOR






DNSODM200_QUADMIC Provides 2 or 4 Mictor-38 connectors. Compatible with the DDR2 SODIMM sockets. User LEDs. Small EPROM.

DNSODM200_DDR1 DDR1 memory module compatible with the 200-pin SODIMM sockets Comes with 512MB standard. Allows use of standard PC2700 modules (up to 1GB) 175Mhz performance

DNSODM200_SDR SDR memory module compatible with 200-pin SODIMM sockets. Accepts PC133 modules up to 512MB. (User is required to install a Jumper) Comes with 256MB standard. 75Mhz performance

DNSODM200_FLASH Spansion S29WS064J memory (x2). Each is 4Mx16 bit flash 16Mb SRAM memory (512k x 32) Compatible with DDR2 SODIMM sockets. 66Mhz performance (read burst) Other SODIMMs include access to the following interfaces: - USB, 3.3V IO, FPGA interconnect

19.1.2 Daughter Cards

Dini Group Daughter Cards connect to the MEG-Array connector (400-pin) using the standard Dini Group interface description.

DNMEG_PCIE 8-lane PCIe express PHY card. Host or downstream mode. DDR2 memory module. Virtex-4 FPGA. (LX40-LX160)

DNMEG_AD-DA High-speed Analog-Digital Daughter Card Virtex-4 FPGA DDR2 memory module 250Msps, 12-bit ADC. 60dB SNR (10 bits) 200kHz-75Mhz

DNMEG_V5T Xilinx Virtex 5 LXT FPGA with high-speed serial interfaces. SMA, SATA, SFP, PCI Express Cable



DNMEG_INTERCON Connects headers for FPGA A and B together.

DNMEG_OBS Adjustable-voltage tenth-inch pitch headers User LEDs Two Mictor-38 connectors. SMA global clock inputs for host board.

19.2 Compatible third-party products

The following products have been shown to work with the DN7002K10MEG.

Standard DDR2 modules (256 MB $15, 512 MB $15, 1GB $25, 2GB $64, 4GB eventually): http://www.crucial.com/store/listmodule/DDRII/list.html

Altera USB Cable (required for JTAG FPGA programming, firmware update, SignalTAP, Synplicity Identify)

http://www.crucial.com/store/listmodule/DDRII/list.html



Mictor Breakout MIC-38-BREAKOUT http://www.emulation.com/catalog/off-the-shelf_solutions/mictor/

20 Compliance Data

20.1 Compliance

20.1.1 EMI

Since the DN7002K10MEG is not intended for production systems, it has not passed EMI testing. Compliance is only done by special request.

20.2 Environmental

20.2.1 Temperature

The DN7002K10MEG is designed to operate within an ambient temperature range of 0ºC to 55ºC.

20.3 Export Control

20.3.1 Lead-Free

The DN7002K10MEG meets the requirements of EU Directive 2002/95/EC, ―RoHS‖. Specifically, the DN7002K10MEG contains no homogeneous materials that:

a) contains lead (Pb) in excess of 0.1 weight-% (1000 ppm) b) contains mercury (Hg) in excess of 0.1 weight-% (1000 ppm) c) contains hexavalent chromium (Cr VI) in excess of 0.1 weight-% (1000 ppm) d) contains polybrominated biphenyls (PBB) or polybrominated dimethyl ethers (PBDE) in excess of 0.1 weight-% (1000 ppm) e) contains cadmium (Cd) in excess of 0.01 weight-% (100 ppm)

No exemptions are claimed for this product.

20.3.2 The USA Schedule B number based on the HTS

8471 60 7080

20.3.3 Export control classification number ECCN

EAR99

http://www.emulation.com/catalog/off-the-shelf_solutions/mictor/

Documents

· Table of Contents INTRODUCTION