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SPARTAN Series
High Volume System Solution
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www.xilinx.com
Spartan/XL
Estimated design size (system gates)
30K5K 180K
XC4000XL/AXC4000XV
Virtex
S05/XL S10/XL S20/XL S30/XL S40/XL 4013XL/A 4020XL/A.. 4062XL/A..4085XL/A
XCV50 XCV100 XCV150 XCV200 XCV300 ...XCV1000
5.0/3.3 Volts 2.5 Volts3.3 Volts/2.5Volts
1M
40110XV...40250XV
FPGA Focus Products for New Designs
Select Family Based on Density
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www.xilinx.com
Xilinx 4000 Heritage
Total Cost Management
Advanced ProcessTechnology
Smallest die size
Low cost packaging Low test cost
100 MHz+ performanceOn-chip SelectRAMSoftware and cores
Xilinx Spartan Series FPGAs
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www.xilinx.com
Spartan/XL Product Matrix5 Volt XCS05 XCS10 XCS20 XCS30 XCS40
3.3 Volt XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K
Logic Cells 238 466 950 1368 1862
Max Logic Gates 3,000 5,000 10,000 13,000 20,000
Flip-Flops 360 616 1120 1536 2016
Max RAM bits 3,200 6,272 12,800 18,432 25,088
Max I/O 77 112 160 192 224
Packages PC84 PC84
VQ100 VQ100 VQ100 VQ100
TQ144 TQ144 TQ144
CS144 CS144
PQ208 PQ208 PQ208
PQ240 PQ240
BG256 BG256
CS280 CS280
CS packages available only in SpartanXL family
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What you want from a high-volume FPGA solution
Family Highlights Spartan (5.0 Volt) family introduced in Jan. 98
— Fabricated on advanced 0.5µ process technology Spartan-XL (3.3 Volt) family introduced in Nov. 98
— Fabricated on advanced 0.35µ process technology— Power management features— Higher performance over Spartan (5.0 Volt)— Entire family of 5 devices under $7.50
Both families offer:— SRAM technology (re-programmable)— Leverage industry standard XC4000 architecture— Lowest cost FPGA families with memory (SelectRAM)— Extensive core support— Broadest density/package/temperature/speed offering
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Spartan-XL: More for Less More:
— Faster performance– Speed grades now -4/-5– Spartan-XL -4x faster than Spartan -4– Fastest speed grade delivers 100+ MHz performance
— Programmable I/O options– Output drive and voltage termination (PCI)– Input latch and output tri-state control register
— Parallel express mode configuration
For Less:— Power-down mode (< 100A typical)
– Ideal for high volume portable applications– No sacrifice in performance
— Lower prices– Competitive with gate arrays at similar I/O counts
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* ICCPD will be dependent on VCC, junction temperature, and part size
Spartan-XL: Power Down Mode
Two power-down modes (ICCPD < 100 mA*)— Power-down pin
– Stops clocks– Disables all output pins– Pulls all inputs low– Asserts Global Set/Reset (resets all flip-flops)
— Customer power-down– Customer stops clocks– Customer brings input pins to rails guaranteeing logic
stops switching– Customer disables I/Os
100uA
FullPower
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Faster Time to Market = $
Advantages over ASICs No costly NRE charges
— Standard product No vector file needed
— Devices 100% tested by Xilinx In system verification vs.
simulation— Saves valuable design time
In-field upgradable— Enabler for product differentiation— Allows additional revenue path for
end product Lower material handling cost
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160 I/O 160 I/O
1998Gate array,
0.5u, 50K gatesSpartan-XL,
0.35u, 20K gates
Gate Array 0.8u, 10K gates
FPGA 1.0u, 5K gates
1995
160 I/O160 I/O
Spartan/XL FPGAs Match Gate Array Die Size and Cost
1995 - FPGAs cannot compete with gate arrays— Older process than ASICs— Larger die— Not I/O pad-limited
1998 - FPGAs compete — FPGAs are fab process
drivers, replace DRAMs— Competitive die size with
similar number of I/O
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www.xilinx.com
Syst
em G
ates
50 100 150 200 250 300
120
100
80
60
40
20
10
0
I/Os
1998
1999
Gate Array TerritoryHigh Density,Low I/O
Spartan FPGAsLow Density,High I/O
Spartan-II
Spartan/XL
Spartan Series Replaces Low-Density Gate Arrays
®
www.xilinx.com100K unit volume price projections
1997 1998 1999 2000 2001
10K
20K
40K
100K unit volume price projections
30K
30K
40K
200K
100K
10K Gates Per Dollar in 1999!10K Gates Per Dollar in 1999!
$10$10$5$5
High-Volume Price Leadership
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www.xilinx.com
Focus: High Volume Customer
Complete, Ready-to-Use Programmable Logic Design
Solution
Xilinx Software Solutions
Focus: High Density Designers
Integrated into the Customer’sChosen EDA Environment
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Standard Bus Interface ProductsPeripheral Component Interconnect Bus (PCI)Other Standard Bus Products
Digital Signal Processing CorrelatorsFilters Transforms DSP Building Blocks
Spartan Core Advantages: Pre-verified in silicon Much lower cost than ASIC cores Simple distribution and licensing
Spartan Series Core Support
Communications & Networking Products Asynchronous Transfer Mode Forward Error Correction
Base-Level Products Basic Elements Math Functions
RISC CPU Cores8-bit RISC Core
Processor Peripherals UARTsOthers
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Core FunctionXCS30XL
PricePercentage of Device Used
EffectiveFunction Cost
UART $5.50 17% $.93
16-bit RISC Processor $5.50 36% $1.98
16-bit, 16-tap Symmetrical FIR Filter
$5.50 27% $1.49
Reed-Solomon Encoder $5.50 6% $0.33
PCI Interface $6.55 45% $2.95
*Prices are for 250K units, plastic package
Effective Function Cost with Spartan
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www.xilinx.com
External PLD15K Gates
Com
pone
nt C
ost 1
00K
Uni
ts
Standard ChipPCI Master I/F
$5
$15
$20
$10
Standard Chip Solution >$20
PCI Master I/F
User Design15K Gates
Xilinx PCI Solution <$10.00
*Prices are for 100K units, plastic package, 3.3v technology
Costs Less Than Standard ICs!
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High Volume SPROMs
XC17Sxx SPROMs — Lowest priced SPROM in the industry— Priced to be competitive along with Spartan FPGAs
against ASIC and FPGA competition— SPROM volume pricing < 25% of the FPGA
All Spartan family SPROMs in production
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Summary
Xilinx has changed the rules!— Gates-only solutions are no longer required— No more compromises
Spartan Series delivers key ASIC requirements — High Performance (100+ MHz system clocks)— On-chip distributed SelectRAM— Low power and power-down mode— Extensive core support— Low prices competitive with ASICs
