© Sean Nicolson, BCTM 2006 Design and Scaling of SiGe BiCMOS VCOs Above 100GHz S. T. Nicolson 1, K.H.K Yau 1, K.A. Tang 1, P. Chevalier 2, A. Chantre 2

© Sean Nicolson, BCTM 2006© Sean Nicolson, BCTM 2006

Design and Scaling of SiGe BiCMOS Design and Scaling of SiGe BiCMOS VCOs Above 100GHzVCOs Above 100GHz

S. T. Nicolson1, K.H.K Yau1, K.A. Tang1, P. Chevalier2, A. Chantre2

B. Sautreuil2, and S. P. Voinigescu1

1) Edward S. Rogers Sr. Dept. of Elec. & Comp. Eng., Univ. of Toronto

2) STMicroelectronics


OutlineOutline

• Motivation for W-band SiGe integrated circuits• VCO design methodology for low phase noise in W-band• Layout considerations• Measurement results• Conclusions and future work


Motivation for W-band SiGe ICsMotivation for W-band SiGe ICs• Typical applications: 77GHz auto radar, 94GHz weather radar, imaging

– Central to these applications is the low phase noise VCO• Process development: NFmin, Rn & Ysopt difficult to measure in W-band

– Use VCO as a process monitor for the noise performance of SiGe technologies• Explore VCO scaling/yield in SiGe


VCO TopologyVCO Topology

• No cascode– lower phase noise, lower supply voltage

• Colpitts topology– maximize fosc relative to other topologies

• Augment Cbe with Cext– Reduces phase noise

• Add negative Miller capacitors– Increases fosc by cancelling C

• Differential tuning– reduces supply induced noise

24mA

CM

VCC

LB

Cext

Cvar

Q1

VTUNE+

VTUNE-LEE

REE CEE

LC

VBB

2.5 V

VTUNE

RB

rcib

E

CBCext


W-Band VCO Design MethodologyW-Band VCO Design Methodology

• Use smallest realizable LB with adequate Q

• Given fosc, maximize tuning range using large Cext

• Negative resistance

• Phase noise formula

• Phase noise trade-off when HBT pushed to limit– Minimize HBT noise bias at NFmin current density

– Maximize Vtank and Cext bias at peak fT current density

22

var

22

tank

2

1

1

12

C

CCCC

V

IS

extext

n

out

CCCC

CCCC

ext

exteq

var

var

eqBosc

CLf

2

1

var2 CVIC

VIRR

TCFext

TCBneg Max. Rneg occurs at

peak fT/fMAX bias


VCO FabricationVCO Fabrication

• Fabricated in three technology splits:

• All VCO layouts and bias currents are identical – no redesign• Directly compare VCOs fabricated in different processes• Use the VCO to optimize HBT profile

– Noise parameters from phase noise– fMAX from VCO output power

BiC9fT = 150GHzfMAX = 160GHz

emitter4×5m×0.17m

BipXfT = 230GHzfMAX = 300GHz

emitter4×5m×0.13m

BipX1fT = 270GHzfMAX = 260GHz

emitter4×5m×0.13m


VCO LayoutVCO Layout

• VCO core area: 100m × 100m• Spiral inductors where necessary to reduce area• Plenty of supply decoupling (MiM and metal-metal)

70m

100m


Technology Overview – fTechnology Overview – fTT/f/fMAXMAX Scaling Scaling• Peak fT/fMAX current density increases at each technology node

– 0.17m SiGe JpeakfT = 7mA/m2 where fT = 150GHz

– 0.13m SiGe JpeakfT = 14mA/m2 where fT = 230GHz (or 250GHz)

• Contrast with CMOS…– JpfT = 0.3mA/m, JpfMAX = 0.2mA/m, JNFmin = 0.15mA/m for 180-65nm nodes


Measurement ResultsMeasurement Results

• VCO performance comparison in 3 SiGe technologies• Phase noise performance• Temperature testing• Wafer mapping


Performance Comparison Across TechnologyPerformance Comparison Across Technology

• LC-oscillator frequency insensitive to technology fT/fMAX

• MOS varactors give less phase noise than HBT (CBC) varactors• Higher fMAX more output power, higher frequency• BipX1 results in lowest phase noise

BiCMOS9MOS var.

BiCMOS9HBT var.

BipXHBT var.

BipX1HBT var.

Tech. fT/fMAX

(GHz)

150/160 150/160 230/300 250/260

Differential Pout (dBm)

+0.7 -1.3 +2.7 +2.5

SSB PN @ 1MHz (dBc/Hz)

-101.6 -80 -98 -101.3

Osc. Freq. (GHz) 96 100 106 104


Phase Noise PerformancePhase Noise Performance• Oscillation frequency of 104GHz• Phase noise of 101.3dBc/Hz @ 1MHz offset

90nm CMOS

fT=200GHz

fmax=275GHz

fT=175

fmax=275

130nm CMOS fT=175

fmax=275fT=205

fmax=290

fT=206

fmax=197

fT=150

fmax=160

fT=270

fmax=260

fT=155

fmax=155

fT=230

fmax=300

-110

-105

-100

-95

-90

-85

-80

65 70 75 80 85 90 95 100 105 110

Oscillation frequency (GHz)

Ph

ase

no

ise

at 1

MH

z o

ffse

t (d

Bc/

Hz)

Averaged Spectral PlotPhase Noise in W-Band

SiGe VCOs

**References provided in abstract**

FMCW modulation


Biasing W-Band VCOs for Low NoiseBiasing W-Band VCOs for Low Noise• NFmin current density scales with technology and fosc

– Emitter width JNFmin (scales with JpeakfT)

– Frequency JNFmin (gets closer to JpeakfT)

– Noise correlation further increases JNFmin [K. Yau, SiRF, 2006]

The B and C shot noise currents are correlated

1exp2* nCnCnB jqIii

c ibC

RB

E

BinB inC


phase noise

JNFMIN increaseswith frequency

output power

CM

VCC

LB

Cext

Cvar

Q1

VTUNE+

VTUNE-LEE

REE CEE

LC

VBB

2.5 V

Phase Noise Performance Across BiasPhase Noise Performance Across Bias• What is the minimum phase noise current density in W-band VCOs?• Measure output power and phase noise w.r.t current density (vary VBB)

• Looks like phase noise is minimum at peak fT current density


-6

-4

-2

0

2

92 96 100 104 108Center frequency (GHz)

Ou

tpu

t p

ow

er (

dB

m)

. 25ºC

70ºC

25ºC

50ºC

125ºC

70ºC

25ºC

BiC9MOS var.

BiC9HBT var. BipX

W-Band Manufacturability ChallengesW-Band Manufacturability Challenges• Manufacturability specifications for automotive radar are stringent

– Outdoors wide temperature variations– Must last for car’s lifetime– Low cost per part requires high yield

• Is SiGe on the way to meeting such challenges?


Wafer Mapping – BiCMOS9Wafer Mapping – BiCMOS9

Wafer 1 2 3 4

Center freq. (GHz) 94.7 94.9 94.9 95.0

Tuning range (GHz) 4.6 4.6 4.6 4.6

Output power (dBm) 0.2 0.7 0.6 0.8

DC power (mW) 133.8 133.2 137.3 132.6

Wafer 1 2 3 4

Center freq. (GHz) 99.6 100.5 100.1 100.5

Tuning range (GHz) 3.4 3.6 3.6 3.7

Output power (dBm) -1.1 -1 -1.4 -0.9

DC power (mW) 133.0 133.0 136.2 132.8

• Tested 120 VCOs on 4 wafers• Summary of BiC9 VCOs with MOS varactors (60 dice averaged)

• Summary of BiC9 VCOs with HBT varactors (60 dice averaged)

• 4 VCOs had significantly below average performance (outliers)• 2 of the 4 outlier VCOs failed to oscillate entirely


Wafer Mapping – BipXWafer Mapping – BipX

VCO not present

Die not tested

< -98 dBc/Hz

-95 – -98 dBc/Hz

-92 – -95 dBc/Hz

> -92 dBc/Hz

Oscillation Frequency Phase Noise at 1MHz offset

VCO not present

Die not tested

104.5-105.0 GHz

104.0-104.5 GHz

103.5-104.0 GHz

103.0-103.5 GHz

Wafer flat

Location of VCO in reticule


Figures of MeritFigures of Merit• Comparison of our work to other state of the art W-Band VCOs

References [1] Huang P. et al, ISSCC 2006 [2] Kobayashi K. W. et al, JSSC 1999 [3] Tang K. W. et al. CSICS 2006 [4] Huang P. et al, ISSCC 2006


ConclusionsConclusions

• Demonstrated a design methodology for low phase noise in W-Band VCOs– Biasing at JpeakfT minimizes phase noise in W-band VCOs

• Performed a direct comparison of identical VCOs fabricated in different technologies– LC-oscillator frequency is insensitive to technology scaling– Higher fT technology yielded VCO with lower phase noise

– Higher fMAX technology yielded VCO with improved output power

• Future work is required to fully support these conclusions– Noise figure measurements in the W-Band (correlate to Y-parameter method)– Verify JNFmin in the W-Band and support biasing near JpeakfT for min. phase noise


Technology Overview – fTechnology Overview – fTT/f/fMAXMAX Scaling Scaling• Improvement in peak fT/fMAX has two contributions

– Layout stripe contact, decreased emitter width 0.17m to 0.13– Vertical profile and processing doping, materials, epitaxy, etc.

• How much of the speed improvement is due to each contribution?– Measure the 0.13m HBT layouts fabricated in the 0.17m process

Documents

© Sean Nicolson, BCTM 2006 Design and Scaling of SiGe BiCMOS VCOs Above 100GHz S. T. Nicolson 1, K.H.K Yau 1, K.A. Tang 1, P. Chevalier 2, A. Chantre 2