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Design and Analysis of a Low-Power High-SpeedCharge-Steering Based StrongARM Comparator
ICM’16Authors: Mostafa M. AyeshSameh IbrahimMohamed M. Aboudina
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Outline
• Charge-steering concept• Proposed StrongARM comparator circuit• Delay analysis of the circuit• Simulation results
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Charge-Steering Concept
• Charge-steering is using chargeredistribution without the need ofa DC path to GND.
• Ultra-low power technique
Charge-steering was introduced in[1]
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Conventional StrongARM vs. Charge-Steering Based StrongARM
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Timing Scheme for The Proposed Circuit
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Different Phases of The Proposed Circuit
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Delay Analysis of The Circuit – (1)
• The main equation governs the delay [2]
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Where β 1,2 is the input transistors current factor, I tail is a function of input common-mode voltage and VDD, gm,eff is the effective transconductance of the back to back inverters and ∆Vin is the input difference voltage.
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Delay Analysis of The Circuit – (2)
• the latch delay time is given in [3]
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where ∆Vout,t0 is the initial difference between the output nodes just after amplification at time t0
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Simulation ResultsPower vs. Sampling Frequency
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Simulation ResultsComparator Outputs
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Input common mode was chosen to get the least power and delay. ICM = 0.6V
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Simulation ResultsComparator Outputs
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Simulation Results Comparison Between Conv. StrongARM and this work
Comparison Point Conventional StrongARM This Work
Power consumption at 5 GHz clock 256 µW 33.3 µW
Max. speed for 5 mV input 5 GHz 14 GHz
Sensitivity at 5 GHz clock 4 mV 1 mV
Offset (excluding the input pair) 11.16 mV 3.8 mV
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Main References
[1] B. Razavi, “Charge-steering: A low-power design paradigm,” Custom Integr. Circuits Conf., pp. 1-8, Sep. 2013
[2] S. Babayan-Mashhadi and R. Lotfi, “Analysis and Design of a Low Voltage Low-Power Double-Tail Comparator,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352, Feb. 2014.
[3] D. Johns and K. Martin, “Analog Integrated Circuit Design,” 2nd edition, New York, USA: Wiley, 2012.
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