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i.MX 6SoloLite ApplicationsProcessor Reference Manual

Document Number: IMX6SLRMRev. 3, 09/2017

i.MX 6SoloLite Applications Processor Reference Manual, Rev. 3, 09/2017

2 NXP Semiconductors

Contents

Section number Title Page

Chapter 1Introduction

1.1 About This Document...................................................................................................................................................121

1.1.1 Audience...................................................................................................................................................... 121

1.1.2 Organization.................................................................................................................................................121

1.1.3 Suggested Reading.......................................................................................................................................122

1.1.3.1 General Information.................................................................................................................122

1.1.3.2 Related Documentation............................................................................................................122

1.1.4 Conventions................................................................................................................................................. 122

1.1.5 Register Access............................................................................................................................................ 124

1.1.5.1 Register Diagram Field Access Type Legend..........................................................................124

1.1.5.2 Register Macro Usage..............................................................................................................125

1.1.6 Signal Conventions...................................................................................................................................... 126

1.1.7 Acronyms and Abbreviations.......................................................................................................................126

1.2 Introduction...................................................................................................................................................................129

1.3 Target Applications.......................................................................................................................................................129

1.4 Features.........................................................................................................................................................................130

1.5 Architectural Overview.................................................................................................................................................133

1.5.1 Simplified Block Diagram........................................................................................................................... 133

1.5.2 Architectural Partitioning.............................................................................................................................134

1.5.3 Endianness Support......................................................................................................................................136

1.5.4 Memory Interfaces....................................................................................................................................... 136

Chapter 2Memory Maps

2.1 Memory system overview.............................................................................................................................................137

2.2 ARM Platform Memory Map....................................................................................................................................... 137

2.3 DMA memory map.......................................................................................................................................................142

Chapter 3


NXP Semiconductors 3


Interrupts and DMA Events

3.1 Overview.......................................................................................................................................................................145

3.2 Cortex A9 interrupts..................................................................................................................................................... 145

3.3 CM4 interrupts..............................................................................................................................................................149

3.4 SDMA event mapping.................................................................................................................................................. 153

Chapter 4External Signals and Pin Multiplexing

4.1 Overview.......................................................................................................................................................................155

4.1.1 Pin Assignments...........................................................................................................................................155

4.1.2 Muxing Options........................................................................................................................................... 203

Chapter 5Fusemap

5.1 Boot Fusemap............................................................................................................................................................... 247

5.2 Lock Fusemap...............................................................................................................................................................254

5.3 Fusemap Descriptions Table.........................................................................................................................................255

Chapter 6External Memory Controllers

6.1 Overview.......................................................................................................................................................................263

6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 263

6.3 EIM-PSRAM/NOR flash controller overview..............................................................................................................264

6.3.1 EIM features.................................................................................................................................................265

6.3.2 EIM boot scenarios...................................................................................................................................... 266

6.3.3 EIM boot configuration................................................................................................................................266

6.3.4 OneNAND requirements..............................................................................................................................266

Chapter 7System Debug

7.1 Overview.......................................................................................................................................................................267

7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 267

7.2.1 Debug Features............................................................................................................................................ 268

7.2.2 Debug system components...........................................................................................................................269




7.2.2.1 AMBA Trace Bus (ATB).........................................................................................................270

7.2.2.2 ATB replicator......................................................................................................................... 270

7.2.2.3 Embedded Cross Triggering.................................................................................................... 270

7.2.2.3.1 Cross-Trigger Matrix (CTM)............................................................................271

7.2.2.3.2 Cross-Trigger Interface (CTI)...........................................................................272

7.2.2.4 Debug Access Port (DAP)....................................................................................................... 272

7.2.3 Chip-Specific SJC Features......................................................................................................................... 273

7.2.3.1 JTAG Disable Mode................................................................................................................ 273

7.2.3.2 JTAG ID...................................................................................................................................273

7.2.4 System JTAG Controller - SJC....................................................................................................................274

7.2.5 System JTAG controller main features........................................................................................................274

7.2.6 SJC TAP Port............................................................................................................................................... 274

7.2.7 SJC main blocks...........................................................................................................................................274

7.3 Smart DMA (SDMA) core............................................................................................................................................275

7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary................................................................. 276

7.3.1.1 Other SDMA Debug Functionality.......................................................................................... 276

7.3.1.2 SDMA ROM Patching............................................................................................................. 277

7.4 Miscellaneous............................................................................................................................................................... 277

7.4.1 Clock/Reset/Power.......................................................................................................................................277

7.5 Supported tools............................................................................................................................................................. 278

Chapter 8System Boot

8.1 Overview.......................................................................................................................................................................279

8.2 Boot modes................................................................................................................................................................... 280

8.2.1 Boot mode pin settings.................................................................................................................................281

8.2.2 High-level boot sequence.............................................................................................................................281

8.2.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)..................................................................................282

8.2.4 Serial Downloader........................................................................................................................................283

8.2.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10)...................................................................................... 284




8.2.6 Boot security settings................................................................................................................................... 285

8.3 Device configuration.....................................................................................................................................................285

8.3.1 Boot eFUSE descriptions............................................................................................................................. 286

8.3.2 GPIO boot overrides.................................................................................................................................... 288

8.3.3 Device Configuration Data (DCD).............................................................................................................. 289

8.4 Device initialization......................................................................................................................................................289

8.4.1 Internal ROM/RAM memory map...............................................................................................................290

8.4.2 Boot block activation .................................................................................................................................. 290

8.4.3 Clocks at boot time...................................................................................................................................... 291

8.4.4 Enabling MMU and caches..........................................................................................................................293

8.4.5 Exception handling...................................................................................................................................... 293

8.4.6 Interrupt handling during boot..................................................................................................................... 294

8.4.7 Persistent bits............................................................................................................................................... 294

8.5 Boot devices (internal boot)..........................................................................................................................................294

8.5.1 NOR flash/OneNAND using EIM interface................................................................................................ 295

8.5.1.1 NOR flash boot operation........................................................................................................ 295

8.5.1.2 OneNAND flash boot operation.............................................................................................. 296

8.5.1.3 IOMUX configuration for EIM devices...................................................................................297

8.5.2 Expansion device......................................................................................................................................... 298

8.5.2.1 Expansion device eFUSE configuration.................................................................................. 298

8.5.2.2 MMC and eMMC boot............................................................................................................ 301

8.5.2.3 SD, eSD, and SDXC................................................................................................................ 309

8.5.2.4 IOMUX configuration for SD/MMC.......................................................................................309

8.5.2.5 Redundant boot support for expansion device.........................................................................310

8.5.3 Serial ROM through SPI and I2C................................................................................................................ 312

8.5.3.1 Serial ROM eFUSE configuration........................................................................................... 312

8.5.3.2 I2C boot....................................................................................................................................313

8.5.3.2.1 I2C IOMUX pin configuration......................................................................... 314

8.5.3.3 ECSPI boot...............................................................................................................................314




8.5.3.3.1 ECSPI IOMUX pin configuration.................................................................... 316

8.6 Program image..............................................................................................................................................................317

8.6.1 Image Vector Table and Boot Data..............................................................................................................317

8.6.1.1 Image vector table structure.....................................................................................................318

8.6.1.2 Boot data structure................................................................................................................... 319

8.6.2 Device Configuration Data (DCD).............................................................................................................. 319

8.6.2.1 Write data command................................................................................................................ 321

8.6.2.2 Check data command............................................................................................................... 322

8.6.2.3 NOP command.........................................................................................................................324

8.6.2.4 Unlock command..................................................................................................................... 324

8.7 Plugin image................................................................................................................................................................. 325

8.8 Serial Downloader........................................................................................................................................................ 326

8.8.1 USB..............................................................................................................................................................327

8.8.1.1 USB configuration details........................................................................................................327

8.8.1.2 IOMUX configuration for USB............................................................................................... 328

8.8.2 Serial Download Protocol (SDP)................................................................................................................. 328

8.8.2.1 SDP commands........................................................................................................................ 329

8.8.2.1.1 READ_REGISTER...........................................................................................329

8.8.2.1.2 WRITE_REGISTER.........................................................................................330

8.8.2.1.3 WRITE_FILE................................................................................................... 330

8.8.2.1.4 ERROR_STATUS............................................................................................ 332

8.8.2.1.5 DCD_WRITE................................................................................................... 332

8.8.2.1.6 JUMP_ADDRESS............................................................................................ 333

8.9 Recovery devices.......................................................................................................................................................... 334

8.10 USB low-power boot.................................................................................................................................................... 334

8.11 SD/MMC manufacture mode........................................................................................................................................336

8.12 High-Assurance Boot (HAB)........................................................................................................................................337

8.12.1 HAB API vector table addresses..................................................................................................................338

Chapter 9




Multimedia

9.1 Display and graphics subsystem................................................................................................................................... 341

9.1.1 Electrophoretic Display Controller.............................................................................................................. 342

9.1.2 PiXel Processing Pipeline (PXP)................................................................................................................. 343

9.1.3 LCD Interface (LCDIF)............................................................................................................................... 343

9.1.4 CMOS Sensor Interface (CSI)..................................................................................................................... 343

9.1.5 2D Graphics Processing Unit (GPU2Dv2).................................................................................................. 344

9.1.5.1 2D feature summary.................................................................................................................344

9.1.5.2 2D Performance....................................................................................................................... 346

9.1.5.3 2D Software............................................................................................................................. 346

9.1.6 Vector Graphics Processing Unit (GPUVGv2)........................................................................................... 346

9.1.6.1 Vector Graphics Features.........................................................................................................346

9.1.6.2 Vector Graphics Performance..................................................................................................346

9.1.6.3 Vector Graphics Software........................................................................................................347

9.2 Audio subsystem...........................................................................................................................................................347

9.2.1 Audio Subsystem Module Overview........................................................................................................... 347

9.2.2 Synchronous Audio Interface (SAI)............................................................................................................ 349

9.2.3 Sony/Philips Digital Interface (SPDIF)....................................................................................................... 349

Chapter 10Clock and Power Management

10.1 Introduction...................................................................................................................................................................353

10.2 Device Power Management Architecture Components................................................................................................353

10.2.1 Centralized components of clock generation and management...................................................................354

10.2.2 Centralized components of power generation, distribution and management............................................. 355

10.2.3 Reset generation and distribution system.....................................................................................................355

10.2.4 Power and clock management framework................................................................................................... 355

10.3 Clock Management....................................................................................................................................................... 356

10.3.1 Centralized components of clock management system............................................................................... 356

10.3.2 Clock generation.......................................................................................................................................... 359




10.3.2.1 Crystal Oscillator (XTALOSC) .............................................................................................. 359

10.3.2.2 Low Voltage Differential Signaling (LVDS) I/O ports........................................................... 359

10.3.2.3 PLLs......................................................................................................................................... 359

10.3.2.3.1 General PLL Control and Status Functions...................................................... 361

10.3.2.4 CCM ........................................................................................................................................362

10.3.2.5 Low Power Clock Gating unit (LPCG)....................................................................................362

10.3.3 Peripheral components of clock management system................................................................................. 363

10.3.3.1 Interface and functional clock..................................................................................................364

10.3.3.2 Block level clock management................................................................................................ 364

10.3.3.2.1 Master clock protocol....................................................................................... 365

10.3.3.2.2 Slave clock protocol..........................................................................................365

10.3.3.3 Clock Domain(s)...................................................................................................................... 366

10.3.3.4 Domain level clock management.............................................................................................366

10.3.3.5 Domain dependencies.............................................................................................................. 366

10.4 Power management.......................................................................................................................................................366

10.4.1 Centralized Components of Power Management System............................................................................367

10.4.1.1 Integrated PMU........................................................................................................................367

10.4.1.1.1 Digital LDO Regulators....................................................................................368

10.4.1.1.2 Analog LDO regulators.....................................................................................369

10.4.1.1.3 USB LDO..........................................................................................................369

10.4.1.1.4 SNVS regulator.................................................................................................370

10.4.1.1.5 Reverse well biasing......................................................................................... 370

10.4.1.2 GPC - General Power Controller............................................................................................. 370

10.4.1.3 SRC - System reset Controller................................................................................................. 371

10.4.1.4 Power domain(s)...................................................................................................................... 371

10.4.1.4.1 Power distribution ............................................................................................372

10.4.1.4.2 Domain Memory and domain logic state retention in case of Power Gating... 373

10.4.1.4.3 Power Gating Domain Management.................................................................374

10.4.1.4.3.1 ARM Core Platform................................................................. 374




10.4.1.4.3.2 GPU2D..................................................................................... 374

10.4.1.4.3.3 SoC........................................................................................... 375

10.4.1.4.4 Power Gating domain dependencies.................................................................375

10.4.1.5 Voltage domains...................................................................................................................... 376

10.4.1.6 Voltage domain management...................................................................................................376

10.4.1.6.1 Dynamic............................................................................................................376

10.4.1.6.1.1 Voltage Scaling........................................................................ 376

10.4.1.6.2 Static ................................................................................................................ 376

10.4.1.6.2.1 Standby Leakage reduction (SLR)........................................... 377

10.4.1.7 System domains layout............................................................................................................ 377

10.4.2 Power management techniques....................................................................................................................379

10.4.2.1 Power saving techniques..........................................................................................................380

10.4.2.2 Thermal-aware power management.........................................................................................380

10.4.2.3 Peripheral Power management.................................................................................................381

10.4.2.3.1 Main memory power management................................................................... 381

10.4.2.3.2 Video-Graphics system power management.................................................... 382

10.4.2.3.3 IO power reduction........................................................................................... 382

10.4.3 Examples of External Power Supply Interface............................................................................................ 383

10.5 ONOFF (Button)...........................................................................................................................................................385

Chapter 11System Security

11.1 Overview.......................................................................................................................................................................387

11.2 Central Security Unit (CSU).........................................................................................................................................389

11.2.1 CSU Overview............................................................................................................................................. 389

11.2.2 CSU Features............................................................................................................................................... 389

11.2.3 CSU Functional Description........................................................................................................................ 390

11.2.3.1 CSU Peripheral Access Policy.................................................................................................390

11.3 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 391

11.3.1 SNVS Overview...........................................................................................................................................391




11.3.2 Tamper Detection.........................................................................................................................................392

11.4 Data Co-Processor (DCP)............................................................................................................................................. 392

11.5 Data Co-Processor (DCP)............................................................................................................................................. 392

11.6 High-Assurance Boot (HAB)........................................................................................................................................393

11.7 System JTAG Controller (SJC).................................................................................................................................... 393

Chapter 12ARM Cortex A9 MPCore Platform (ARM)

12.1 Overview.......................................................................................................................................................................395

12.2 External Signals............................................................................................................................................................ 395

12.3 Platform configuration..................................................................................................................................................397

12.3.1 Platform and SCU configuration..................................................................................................................397

12.3.2 Core configuration....................................................................................................................................... 397

12.3.3 PL310 L2 Cache configuration.................................................................................................................... 398

12.3.4 Endian Modes.............................................................................................................................................. 398

12.3.5 Memory Parity error support .......................................................................................................................399

12.4 Performance and Power................................................................................................................................................ 399

12.4.1 Low-Power design....................................................................................................................................... 399

12.4.1.1 SRPG (State Retention Power Gating).................................................................................... 399

12.4.1.2 Dynamic Voltage and Frequency Scaling (DVFS)..................................................................400

12.4.2 Clocks, frequency goals............................................................................................................................... 400

12.4.2.1 ARM Clock.............................................................................................................................. 400

12.4.2.2 Bus Clocks............................................................................................................................... 400

12.4.2.3 Debug Clocks...........................................................................................................................400

12.5 Core Platform Sub-Blocks details.................................................................................................................................401

12.5.1 ARM Cortex A9 MPCore Processor............................................................................................................401

12.5.2 Media Processing Engine (MPE - NEON).................................................................................................. 401

12.5.3 Generic Interrupt Controller (GIC).............................................................................................................. 402

12.5.3.1 Interrupt Controller Features....................................................................................................402

12.5.3.2 About the Interrupt Controller................................................................................................. 402




12.5.3.3 Interrupt Controller Clock frequency.......................................................................................402

12.5.3.4 TrustZone support.................................................................................................................... 402

12.5.4 Instruction and data caches (L1).................................................................................................................. 403

12.5.4.1 L1 features................................................................................................................................403

12.5.5 L2 Cache and controller (PL310).................................................................................................................403

12.6 Debug and Trace Sub-blocks (CoreSight components)................................................................................................403

12.6.1 Debug Access Port (DAP) .......................................................................................................................... 404

12.6.2 Program Trace Macrocell (PTM).................................................................................................................404

12.6.2.1 Program Flow Trace (PFT)...................................................................................................... 405

12.6.3 Cross Trigger Interface (CTI)...................................................................................................................... 406

12.6.4 Embedded Trace Buffer (ETB)....................................................................................................................406

12.6.4.1 AMBA Trace Bus (ATB) Replicator ...................................................................................... 406

Chapter 13AHB to IP Bridge (AIPSTZ)

13.1 Overview.......................................................................................................................................................................407

13.1.1 Features........................................................................................................................................................ 407

13.2 Clocks........................................................................................................................................................................... 407

13.3 Functional Description..................................................................................................................................................408

13.4 Access Protections........................................................................................................................................................ 409

13.5 Access Support..............................................................................................................................................................409

13.6 Initialization Information..............................................................................................................................................410

13.6.1 Security Block..............................................................................................................................................410

13.7 AIPSTZ Memory Map/Register Definition..................................................................................................................411

13.7.1 Master Priviledge Registers (AIPSTZx_MPR)............................................................................................412

13.7.2 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR)....................................................414

13.7.3 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR1)..................................................417







Chapter 14Digital Audio Multiplexer (AUDMUX)

14.1 Overview.......................................................................................................................................................................429

14.1.1 Features........................................................................................................................................................ 431

14.1.2 Modes and Operations................................................................................................................................. 431


14.3 Clocks........................................................................................................................................................................... 433

14.3.1 Clock Inputs................................................................................................................................................. 433

14.3.2 Clock Diagram............................................................................................................................................. 433

14.3.3 Clocking Restrictions...................................................................................................................................434

14.4 Default Register Configuration.....................................................................................................................................434

14.4.1 Default Port Configuration...........................................................................................................................434


14.5.1 Operating Modes..........................................................................................................................................435

14.5.1.1 Port Receive Data Modes.........................................................................................................436

14.5.1.1.1 Normal Mode....................................................................................................437

14.5.1.1.2 Internal Network Mode.....................................................................................438

14.5.1.1.3 Transmit Data Output Enable Assertion........................................................... 444

14.5.1.2 Tx/Rx Switch and External Network Mode.............................................................................445

14.5.1.3 Timing Modes.......................................................................................................................... 446

14.5.1.3.1 Synchronous Mode (4-Wire Interface)............................................................. 446

14.5.1.3.2 Asynchronous Mode (6-Wire Interface)...........................................................448

14.5.2 Connectivity Between Ports.........................................................................................................................451

14.5.2.1 Internal Port to External Port Connectivity..............................................................................452

14.5.2.2 External Port to External Port Connectivity............................................................................ 453

14.5.2.3 Internal Port to Internal Port Connectivity...............................................................................453

14.5.2.4 Loopback Connectivity............................................................................................................ 454

14.6 AUDMUX Memory Map/Register Definition..............................................................................................................454

14.6.1 Port Timing Control Register 1 (AUDMUX_PTCR1)................................................................................ 455




14.6.2 Port Data Control Register 1 (AUDMUX_PDCR1)....................................................................................457













Chapter 15Clock Controller Module (CCM)

15.1 Overview.......................................................................................................................................................................477

15.1.1 Features........................................................................................................................................................ 477

15.1.2 CCM Block Diagram................................................................................................................................... 478


15.3 CCM Clock Tree...........................................................................................................................................................480

15.4 System Clocks...............................................................................................................................................................483


15.5.1 Clock Generation......................................................................................................................................... 490

15.5.1.1 External Low Frequency Clock - CKIL ..................................................................................490

15.5.1.1.1 CKIL synchronizing to IPG_CLK....................................................................490

15.5.1.2 External High Frequency Clock - CKIH and internal oscillator..............................................490

15.5.1.3 PLL reference clock................................................................................................................. 491

15.5.1.3.1 ARM PLL......................................................................................................... 491

15.5.1.3.2 USB PLLs......................................................................................................... 491




15.5.1.3.3 System PLL.......................................................................................................492

15.5.1.3.4 Audio / Video PLL............................................................................................492

15.5.1.3.5 Ethernet PLL.....................................................................................................492

15.5.1.4 Phase Fractional Dividers (PFD)............................................................................................. 492

15.5.1.5 CCM internal clock generation................................................................................................ 493

15.5.1.5.1 Clock Switcher..................................................................................................494

15.5.1.5.2 PLL bypass procedure.......................................................................................496

15.5.1.5.3 PLL clock change............................................................................................. 496

15.5.1.5.4 Clock Root Generator....................................................................................... 496

15.5.1.5.5 Initial values controlled by the System JTAG Controller (SJC).......................505

15.5.1.5.6 Divider change handshake................................................................................ 506

15.5.1.6 Disabling / Enabling PLLs.......................................................................................................506

15.5.1.7 Clock Switching Multiplexers................................................................................................. 506

15.5.1.8 Low Power Clock Gating module (LPCG)..............................................................................508

15.5.1.9 MMDC handshake................................................................................................................... 509

15.5.2 DVFS support.............................................................................................................................................. 510

15.5.3 Power modes................................................................................................................................................ 510

15.5.3.1 RUN mode............................................................................................................................... 510

15.5.3.2 WAIT mode............................................................................................................................. 510

15.5.3.2.1 Entering WAIT mode ...................................................................................... 510

15.5.3.2.2 Exiting WAIT mode ........................................................................................ 511

15.5.3.3 STOP mode.............................................................................................................................. 511

15.5.3.3.1 Entering STOP mode ....................................................................................... 511

15.5.3.3.2 Exiting STOP mode.......................................................................................... 512

15.6 CCM Memory Map/Register Definition.......................................................................................................................513

15.6.1 CCM Control Register (CCM_CCR)...........................................................................................................515

15.6.2 CCM Control Divider Register (CCM_CCDR)...........................................................................................517

15.6.3 CCM Status Register (CCM_CSR)..............................................................................................................518

15.6.4 CCM Clock Switcher Register (CCM_CCSR)............................................................................................519




15.6.5 CCM Arm Clock Root Register (CCM_CACRR).......................................................................................521

15.6.6 CCM Bus Clock Divider Register (CCM_CBCDR)................................................................................... 522

15.6.7 CCM Bus Clock Multiplexer Register (CCM_CBCMR)............................................................................ 524

15.6.8 CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1).................................................................... 527

15.6.9 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2).................................................................... 529

15.6.10 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)............................................................................530

15.6.11 CCM SSI1 Clock Divider Register (CCM_CS1CDR)................................................................................ 533

15.6.12 CCM SSI2 Clock Divider Register (CCM_CS2CDR)................................................................................ 534

15.6.13 CCM D1 Clock Divider Register (CCM_CDCDR).................................................................................... 536

15.6.14 CCM HSC Clock Divider Register (CCM_CHSCCDR).............................................................................537



15.6.17 CCM Divider Handshake In-Process Register (CCM_CDHIPR)............................................................... 543

15.6.18 CCM Low Power Control Register (CCM_CLPCR).................................................................................. 546

15.6.19 CCM Interrupt Status Register (CCM_CISR)............................................................................................. 549

15.6.20 CCM Interrupt Mask Register (CCM_CIMR).............................................................................................552

15.6.21 CCM Clock Output Source Register (CCM_CCOSR)................................................................................ 554

15.6.22 CCM General Purpose Register (CCM_CGPR)..........................................................................................556

15.6.23 CCM Clock Gating Register 0 (CCM_CCGR0)..........................................................................................557







15.6.30 CCM Module Enable Overide Register (CCM_CMEOR).......................................................................... 567

15.7 CCM Analog Memory Map/Register Definition..........................................................................................................568

15.7.1 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARMn)....................................................... 572

15.7.2 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1n)......................................574




15.7.3 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2n)......................................576

15.7.4 Analog System PLL Control Register (CCM_ANALOG_PLL_SYSn)......................................................578

15.7.5 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn)...................................................580

15.7.6 Numerator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_NUM)....582

15.7.7 Denominator of Audio PLL Fractional Loop Divider Register

(CCM_ANALOG_PLL_AUDIO_DENOM)...............................................................................................583

15.7.8 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEOn)................................................... 584

15.7.9 Numerator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_NUM).....586

15.7.10 Denominator of Video PLL Fractional Loop Divider Register

(CCM_ANALOG_PLL_VIDEO_DENOM)............................................................................................... 587

15.7.11 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENETn).................................................... 588

15.7.12 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480n)......... 590

15.7.13 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528n)......... 592

15.7.14 Miscellaneous Register 0 (CCM_ANALOG_MISC0n).............................................................................. 595



Chapter 16CMOS Sensor Interface (CSI)

16.1 Overview.......................................................................................................................................................................607


16.3 Clocks........................................................................................................................................................................... 609

16.4 Principles of Operation................................................................................................................................................. 610

16.4.1 Data Transfer with the Embedded DMA Controllers.................................................................................. 611

16.4.2 Gated Clock Mode....................................................................................................................................... 613

16.4.3 Non-Gated Clock Mode............................................................................................................................... 613

16.4.4 CCIR656 Interlace Mode............................................................................................................................. 613

16.4.5 CCIR656 Progressive Mode........................................................................................................................ 616

16.4.6 Error Correction for CCIR656 Coding........................................................................................................ 617

16.5 Interrupt Generation......................................................................................................................................................617

16.5.1 Start Of Frame Interrupt (SOF_INT)........................................................................................................... 618




16.5.2 End Of Frame Interrupt (EOF_INT)............................................................................................................618

16.5.3 Change Of Field Interrupt (COF_INT)........................................................................................................618

16.5.4 CCIR Error Interrupt (ECC_INT)................................................................................................................618

16.5.5 RxFIFO Full Interrupt (RxFF_INT)............................................................................................................ 619

16.5.6 Statistic FIFO Full Interrupt (STATFF_INT)..............................................................................................619

16.5.7 RxFIFO Overrun Interrupt (RFF_OR_INT)................................................................................................ 619

16.5.8 Statistic FIFO Overrun Interrupt (SFF_OR_INT)....................................................................................... 619

16.5.9 Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1).................................................619

16.5.10 Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2).................................................619

16.5.11 Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF)..................................................620

16.5.12 AHB Bus Response Error Interrupt (HRESP_ERR_INT)...........................................................................620

16.6 Data Packing Style........................................................................................................................................................620

16.6.1 RX FIFO Path.............................................................................................................................................. 621

16.6.1.1 Bayer Data................................................................................................................................621

16.6.1.2 RGB565 Data...........................................................................................................................621

16.6.1.3 RGB888 Data...........................................................................................................................622

16.6.2 STAT FIFO Path..........................................................................................................................................624

16.7 CSI Memory Map/Register Definition......................................................................................................................... 624

16.7.1 CSI Control Register 1 (CSI_CSICR1)....................................................................................................... 625



16.7.4 CSI Statistic FIFO Register (CSI_CSISTATFIFO).....................................................................................633

16.7.5 CSI RX FIFO Register (CSI_CSIRFIFO)................................................................................................... 634

16.7.6 CSI RX Count Register (CSI_CSIRXCNT)................................................................................................ 634

16.7.7 CSI Status Register (CSI_CSISR)............................................................................................................... 635

16.7.8 CSI DMA Start Address Register - for STATFIFO (CSI_CSIDMASA_STATFIFO)............................... 638

16.7.9 CSI DMA Transfer Size Register - for STATFIFO (CSI_CSIDMATS_STATFIFO)................................638

16.7.10 CSI DMA Start Address Register - for Frame Buffer1 (CSI_CSIDMASA_FB1)...................................... 639

16.7.11 CSI DMA Transfer Size Register - for Frame Buffer2 (CSI_CSIDMASA_FB2)...................................... 640




16.7.12 CSI Frame Buffer Parameter Register (CSI_CSIFBUF_PARA)................................................................ 640

16.7.13 CSI Image Parameter Register (CSI_CSIIMAG_PARA)........................................................................... 641

Chapter 17Debug Monitor (DBGMON)

17.1 Overview.......................................................................................................................................................................643

17.1.1 Features Summary........................................................................................................................................644

17.1.2 Functional Description.................................................................................................................................644

17.1.3 Application...................................................................................................................................................644

17.2 DBGMON Memory Map/Register Definition..............................................................................................................645

17.2.1 HW_DBGMON_CTRL (DBGMON_HW_DBGMON_CTRL).................................................................646

17.2.2 HW_DBGMON_MASTER_EN (DBGMON_HW_DBGMON_MASTER_EN)...................................... 648

17.2.3 HW_DBGMON_IRQ (DBGMON_HW_DBGMON_IRQ)........................................................................649

17.2.4 HW_DBGMON_TRAP_ADDR_LOW (DBGMON_HW_DBGMON_TRAP_ADDR_LOW)................ 650

17.2.5 HW_DBGMON_TRAP_ADDR_HIGH (DBGMON_HW_DBGMON_TRAP_ADDR_HIGH).............. 650

17.2.6 HW_DBGMON_TRAP_ID (DBGMON_HW_DBGMON_TRAP_ID).................................................... 651

17.2.7 HW_DBGMON_SNVS_ADDR (DBGMON_HW_DBGMON_SNVS_ADDR)...................................... 651

17.2.8 HW_DBGMON_SNVS_DATA (DBGMON_HW_DBGMON_SNVS_DATA).......................................652

17.2.9 HW_DBGMON_SNVS_INFO (DBGMON_HW_DBGMON_SNVS_INFO).......................................... 653

17.2.10 HW_DBGMON_VERSION (DBGMON_HW_DBGMON_VERSION)...................................................654

Chapter 18Data Co-Processor (DCP)

18.1 Overview.......................................................................................................................................................................655

18.1.1 DCP limitations for software....................................................................................................................... 657

18.2 Clocks........................................................................................................................................................................... 658

18.3 Operation.......................................................................................................................................................................658

18.3.1 Memory copy, blit, and fill functionality.....................................................................................................659

18.3.2 Advanced Encryption Standard (AES)........................................................................................................ 659

18.3.2.1 Key storage.............................................................................................................................. 660

18.3.2.2 AES OTP key...........................................................................................................................660




18.3.2.3 Encryption modes.................................................................................................................... 660

18.3.3 Hashing........................................................................................................................................................ 662

18.3.4 One-Time Programmable (OTP) key...........................................................................................................663

18.3.5 Managing DCP channel arbitration and performance..................................................................................663

18.3.5.1 DCP arbitration........................................................................................................................ 664

18.3.5.2 Channel-recovery timers.......................................................................................................... 664

18.3.6 Programming channel operations.................................................................................................................665

18.3.6.1 Virtual channels....................................................................................................................... 665

18.3.6.2 Context switching.................................................................................................................... 666

18.3.6.3 Working with semaphores....................................................................................................... 667

18.3.6.4 Work packet structure.............................................................................................................. 668

18.3.6.4.1 Next command address field.............................................................................668

18.3.6.4.2 Control0 field....................................................................................................669

18.3.6.4.3 Control1 field....................................................................................................671

18.3.6.4.4 Source buffer.....................................................................................................671

18.3.6.4.5 Destination buffer............................................................................................. 672

18.3.6.4.6 Buffer size field.................................................................................................672

18.3.6.4.7 Payload pointer................................................................................................. 673

18.3.6.4.8 Status.................................................................................................................673

18.3.6.4.9 Payload..............................................................................................................674

18.3.7 Programming DCP functions....................................................................................................................... 675

18.3.7.1 Basic memory copy programming example............................................................................ 675

18.3.7.2 Basic hash operation programming example........................................................................... 676

18.3.7.3 Basic cipher operation programming example........................................................................ 678

18.3.7.4 Multi-buffer scatter/gather cipher and hash operation programming example........................679

18.4 DCP memory map/register definition...........................................................................................................................682

18.4.1 DCP control register 0 (DCP_CTRL)..........................................................................................................683

18.4.2 DCP status register (DCP_STAT)............................................................................................................... 686

18.4.3 DCP channel control register (DCP_CHANNELCTRL)............................................................................ 688




18.4.4 DCP capability 0 register (DCP_CAPABILITY0)......................................................................................690

18.4.5 DCP capability 1 register (DCP_CAPABILITY1)......................................................................................691

18.4.6 DCP context buffer pointer (DCP_CONTEXT)..........................................................................................692

18.4.7 DCP key index (DCP_KEY)........................................................................................................................692

18.4.8 DCP key data (DCP_KEYDATA)...............................................................................................................693

18.4.9 DCP work packet 0 status register (DCP_PACKET0)................................................................................ 694







18.4.16 DCP channel 0 command pointer address register (DCP_CH0CMDPTR).................................................701

18.4.17 DCP channel 0 semaphore register (DCP_CH0SEMA).............................................................................. 702

18.4.18 DCP channel 0 status register (DCP_CH0STAT)....................................................................................... 703

18.4.19 DCP channel 0 options register (DCP_CH0OPTS).....................................................................................705













18.4.32 DCP debug select register (DCP_DBGSELECT)....................................................................................... 720




18.4.33 DCP debug data register (DCP_DBGDATA)............................................................................................. 721

18.4.34 DCP page table register (DCP_PAGETABLE)...........................................................................................721

18.4.35 DCP version register (DCP_VERSION)..................................................................................................... 722

Chapter 19Enhanced Configurable SPI (ECSPI)

19.1 Overview.......................................................................................................................................................................723

19.1.1 Features........................................................................................................................................................ 724

19.1.2 Modes and Operations................................................................................................................................. 724


19.3 Clocks........................................................................................................................................................................... 728


19.4.1 Master Mode................................................................................................................................................ 729

19.4.2 Slave Mode.................................................................................................................................................. 729

19.4.3 Low Power Modes....................................................................................................................................... 730

19.4.4 Operations.................................................................................................................................................... 730

19.4.4.1 Typical Master Mode............................................................................................................... 730

19.4.4.1.1 Master Mode with SPI_RDY............................................................................731

19.4.4.1.2 Master Mode with Wait States..........................................................................733

19.4.4.1.3 Master Mode with SS_CTL[3:0] Control.........................................................733

19.4.4.1.4 Master Mode with Phase Control..................................................................... 734

19.4.4.2 Typical Slave Mode................................................................................................................. 735

19.4.5 Reset.............................................................................................................................................................736

19.4.6 Interrupts...................................................................................................................................................... 736

19.4.7 DMA ........................................................................................................................................................... 737

19.4.8 Byte Order....................................................................................................................................................738

19.5 Initialization.................................................................................................................................................................. 739

19.6 Applications.................................................................................................................................................................. 739

19.7 ECSPI Memory Map/Register Definition.....................................................................................................................740

19.7.1 Receive Data Register (ECSPIx_RXDATA)...............................................................................................741




19.7.2 Transmit Data Register (ECSPIx_TXDATA)..............................................................................................742

19.7.3 Control Register (ECSPIx_CONREG)........................................................................................................ 742

19.7.4 Config Register (ECSPIx_CONFIGREG)................................................................................................... 745

19.7.5 Interrupt Control Register (ECSPIx_INTREG)........................................................................................... 747

19.7.6 DMA Control Register (ECSPIx_DMAREG)............................................................................................. 748

19.7.7 Status Register (ECSPIx_STATREG)......................................................................................................... 750

19.7.8 Sample Period Control Register (ECSPIx_PERIODREG)..........................................................................751

19.7.9 Test Control Register (ECSPIx_TESTREG)............................................................................................... 753

19.7.10 Message Data Register (ECSPIx_MSGDATA)...........................................................................................754

Chapter 20External Interface Module (EIM)

20.1 Overview.......................................................................................................................................................................755

20.1.1 Features........................................................................................................................................................ 757

20.1.2 Modes of Operation..................................................................................................................................... 757

20.1.2.1 Asynchronous Mode................................................................................................................ 758

20.1.2.2 Asynchronous Page Read Mode.............................................................................................. 758

20.1.2.3 Multiplexed Address/Data Mode............................................................................................. 758

20.1.2.4 Burst Clock Mode.................................................................................................................... 759

20.1.2.5 Low Power Modes................................................................................................................... 760

20.1.2.6 Boot Mode................................................................................................................................760


20.2.1 Other Important Block I/O Signals Internal to the SoC...............................................................................765

20.3 Clocks...................................................................................................

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