© 2008 Altera Corporation—Public How to Facilitate Advanced Digital Signal Processing (DSP) Design When Facing Performance and Time-to- Market Challenges

© 2008 Altera Corporation—Public

How to Facilitate Advanced Digital Signal Processing (DSP) Design When Facing Performance and Time-to-Market Challenges

2


Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

AgendaAgenda

FPGA-based digital signal processing (DSP) trend New Altera® FPGA devices for DSP application Intellectual property (IP) cores that facilitate DSP design FPGA-based DSP design flow A typical application example—repeater application Resources available Conclusion

3



DSP is a strategic area of investment for Altera Large available market FPGAs have excellent DSP performance per $ The market demands high performance

Altera and DSPAltera and DSP

“Digital signal processing (DSP) has become the technology driver for the entire semiconductor industry. The high-performance segment of the DSP market is growing the fastest, led by FPGAs.”

--Will Strauss, Forward Concepts

0200400600800

1,0001,2001,4001,600

2005 2006 2007 2008 2009 2010

DS

P i

n F

PG

A (

$M)

4



Altera and DSPAltera and DSP

Depth of DSP offering and system complexity

2002 2004 2006 2008 2010

DSPFPGA

devices

DSP intellectual

property

DSPtool

flows

Application-specific

referencedesigns

FPGAs become

optimizedfor DSP

Today:General-purpose DSPVideo and image processingWireless functionsFloating-point library

Tomorrow:More efficient IP cores, use in multiple tools

Today:Wireless:RF DDC/DUC

Video monitoring

Tomorrow:

SDR systems and methodology

Compression

Today:Model-based designEmbedded systems designC-based design

Tomorrow:Higher levels of abstraction and QoR

Today:Cyclone® III FPGAsStratix® III FPGAs

Tomorrow:Planning for even more DSP performance into 45 nm and 32 nm

Altera providing complete DSP solutions


New Altera FPGA Devices for DSP Application

6



Announcing Altera’s New 40-nm DevicesAnnouncing Altera’s New 40-nm Devices

6

7



DSP Block Multiplier CapabilitiesDSP Block Multiplier Capabilities

LEs 18x18 multipliers Extended precision (18x36) multipliers

SP floating point(36x36) multipliers

Stratix IV GX FPGA

EP4SGX70 72,600 384 192 96

EP4SGX110 105,600 512 256 128

EP4SGX230 232,750 1,288 644 322

EP4SGX310 306,800 832 416 208

EP4SGX380 374,400 1,040 520 260

EP4SGX570 569,600 1,024 512 256

Stratix IV E FPGA

EP4SE110 105,600 512 256 128

EP4SE230 232,750 1,288 644 322

EP4SE310 306,800 832 416 208

EP4SE380 374,400 1,040 520 260

EP4SE570 569,600 1,024 512 256

EP4SE720 717,600 1,360 680 340

8



Performance Through ParallelismPerformance Through Parallelism

14© 2006 Altera Corporation - Confidential

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Total 18X18 multipliers = 1,360

EP4SE720

Maximum clock frequency = 550 MHz

DSP performance = 1,360 * 550 MHz

748 GMACS

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Stratix II FPGAStratix IV and Stratix III FPGAs

Cascade modes Input cascade Output cascade

Rounding Unbiased and biased

Saturation Asymmetrical and symmetrical

Barrel shifter Arithmetic, logical, and rotation

Basic multiplier modes 8 x (9x9) 6 x (12x12) 4 x (18x18) 4 x (18x36) 2 x (36x36) 2 x complex (18x18)

Multiply and sum modes 4 x sum of two (18x18) 2 x sum of four (18x18)

Accumulation 2 x Acc

Basic Multiplier Modes 8 x (9x9) 4 x (18x18) 1 x (36x36) 1 x complex (18x18)

Accumulation 2 x Acc

Rounding 16-/32-bit biased

Saturation 32-bit asymmetrical

Barrel shifter Partial support

The Stratix DSP Block EvolutionThe Stratix DSP Block Evolution

10



Highest Performance DSP CapabilitiesHighest Performance DSP Capabilities

Up to 1,360 18x18 embedded multipliers with Stratix IV GX FPGA

11




Memory ports (18-/36-bit) in DSP-enhanced families

Stratix III E FPGA

Stratix IV E FPGA

0

400

800

1,200

1,600

2,000

2,400

2,800

3,200

0 100,000 200,000 300,000 400,000 500,000 600,000 700,000 800,000

40% MORE MEMORY BANDWIDTH

Over 3,000 embedded memory ports (18-bit/36-bit) with Stratix IV GX FPGA

12




Registers/multipliers in DSP-enhanced families

Stratix III E FPGA

Stratix IV E FPGA

0

50

100

150

200

250

300

350

400

450

500

0 100,000 200,000 300,000 400,000 500,000 600,000 700,000 800,000

Up to 445 registersPer multiplier

Significant register resources for DSP applications


IP Cores That Facilitate DSP Design

14



General DSP IPs

FIR compiler

CIC compiler

FFT/IFFTcompiler

Errorcorrection

Reed-SolomonEncoder/decoder

compiler

Signalgeneration

NCOcompiler

ViterbiParallel/serial

decoder

Altera DSP IP PortfolioAltera DSP IP Portfolio

Video Imaging Processing Suite

Gamma correctionLine buffer compiler

2D FIR filterBT656 Avalon® ST Video

2D

median filterColor space

converterChroma resampler Avalon ST Video

Alpha blending mixer

Scaler DeinterlacerColor plane sequencer

Frame bufferimage clipper

Filter Transform Errorcorrection

Signalgeneration

NewNew

15



General DSP Design ExamplesGeneral DSP Design Examples

For more information on design examples, visit: www.altera.com

Wireless Polyphase modulation with aliasing for digital up-conversion Cyclic prefix insertion for orthogonal frequency division multiplexing

(OFDM) systems Designing digital down conversion systems using CIC and FIR filters Using CIC decimation filter with multi-channel support

Filters CIC interpolation filter with multi-channel data support

Transforms Achieving unity gain in FFT/IFFT pair using block floating-point arithmetic

scaling

Forward error correction (FEC) Bit-error rate (BER) performance measurement of Viterbi decoder Viterbi decoder with node synchronization

16



FIR CIC

CICFIR

Signal Processing Chain in FPGAsDigital Up and Down Conversion: Wireless, Medical, Test and Measurement, Military

Signal Processing Chain in FPGAsDigital Up and Down Conversion: Wireless, Medical, Test and Measurement, Military

Altera’s DSP cores let you quickly build a complete up/down conversion signal chain

Numerically controlled oscillator (NCO), cascaded integrator comb (CIC), finite impulse response (FIR) filters using the Avalon streaming interface

Optimized Altera DSP blocks (multiplier and accumulator)

NCO ∑

FIRCIC

CIC FIR

NCOTo DAC

FromADC

I

Q

I

Q

Digital up converter Digital down converter

Altera DSP IP Altera DSP blocks

17



IP for Wireless ApplicationsIP for Wireless Applications

Altera’s DSP IP functions allow seamless integration with proprietary wireless chain building blocks Reed-Solomon and Viterbi FEC

Multiple reference designs and design examples are available to give you a jump start and explore your design options Designing digital down conversion systems using CIC and FIR filters Digital predistortion reference design Channel estimation and equalization reference design

Altera DSP IP Altera DSP blocks

FIR CIC

CICFIR

NCO ∑FFT

adc

Channel estimationand symbol demapping

Deinterleaver

FEC decode – Viterbi or

Turbo

18



Using Altera VIP Cores: Quartus II SoftwareUsing Altera VIP Cores: Quartus II Software

VIP cores are configurable using Quartus® design software


FPGA-based DSP Design Flow

20



System-level simulation of algorithm model

MATLAB/Simulink

RTL implementationRTL simulation

Precision, Synplify, Quartus II software, ModelSim® tool

System-Level DesignSystem-Level Design

Development Implementation

System-level verification of hardware implementation

Altera FPGAAltera development kits

Verification

System, algorithm, andFPGA design separated

Algorithm modeling

(C/C++,M,MDL)

Synthesisplace-and-route

simulation(VHDL/Verilog)

System-levelverification

(Programming file)

21



Interactive environment and high-level language

In MATLAB you can: Develop algorithms

and applications Analyze and access data Visualize data Perform numeric calculations Document and publish results

MATLABMATLAB

22



Dynamic graphical modeling environment add-on to MATLAB

In Simulink you can: Dynamically develop

entire systems Simulate and interact

with the system Explore architectures Analyze results Generate device-specific code

SimulinkSimulink

23



Toolboxes

What is DSP Builder?What is DSP Builder? MATLAB and Simulink

An environment for algorithm development and analysis

Provides static and bit-true modelsDevelop and test individual components

A graphical environment for system modellingProvides dynamic and bit/cycle-true modelsTests component interactions and

behavior of whole systems

DSP Builder: library add-on for Simulink Common DSP functions and advanced

IP for FPGA Register transfer level (RTL) generation and

FPGA compilation utilities FPGA debug facilities

Altera DSP-optimized FPGAs Stratix III devices Cyclone III devices

Floating Point Simulation

Signal Compiler

MDL Schematic Generic Simulink

Blocks

Fixed Point Conversion with Altera Blockset

Fixed Point Simulation

Simulink Design Entry

DSP Builder

Floating-point simulation

Signal compiler

MDL schematic generic Simulink

blocks

Fixed-point conversion with Altera blockset

Fixed-point simulation

Simulink design entry

DSP Builder

24



DSP Builder Design FlowDSP Builder Design Flow

MATLAB/Simulink domain(System simulation and verification)

HDL/hardware domain( Hardware implementation/RTL simulation)

25



Design Flow StepsDesign Flow Steps

1. Create a Simulink model using Altera’s library blocks

2. Simulate the design and verify the functionality

3. (Optional) Perform RTL simulation for comparison with the original model

4. Use the signal compiler to compile the FPGA

5. Program a development kit or board

6. Debug the hardware using SignalTap® II logic analyzer or hardware in the loop

26



Step 1: Create a Simulink FPGA ModelStep 1: Create a Simulink FPGA Model

Drag and drop Altera’slibrary blocks into Simulink

Parameterize each block or IP function

27



Parameterize DSP MegaCore IPParameterize DSP MegaCore IP

DSP IP is parameterized through the normal MegaCore® IP flow

28



Step 2: Simulate in SimulinkStep 2: Simulate in Simulink

Using all the facilities of MATLAB and Simulink:

Create design stimulus Run the Simulink simulator Instrument your design

MATLAB and Simulink stimulus

MATLAB and Simulink instruments

29



Step 3: (Optional) Verify the Generated RTLStep 3: (Optional) Verify the Generated RTL

Automatically generate RTL, run in ModelSim, and compare to Simulink

30



Step 4: Compile the FPGAStep 4: Compile the FPGA *.mdl

Synthesis

Placement and routing

Automatically synthesize, perform placement and routing, and generate an FPGA programming file

*.pof

31



Step 5: Program a Device on a BoardStep 5: Program a Device on a Board

Automatically program a device on a development kit or board

*.pof

32



Step 6: Debug with SignalTap II Logic Analyzer Step 6: Debug with SignalTap II Logic Analyzer

Embed a logic analyzer, capture live data, and analyze results in MATLAB/Simulink

JTAG

JTAG

33



Step 6: Debug/Simulate with HILStep 6: Debug/Simulate with HIL

Use a FPGA for simulation acceleration or logical verification Your

design

JTAG

34



Design Flow Steps—ReviewDesign Flow Steps—Review

1. Create a Simulink model using Altera’s library blocks

2. Simulate the design and verify the functionality

3. (Optional) Perform RTL simulation for comparison with the original model

4. Use the signal compiler to compile the FPGA

5. Program a development kit or board

6. Debug the hardware using SignalTap II logic analyzer or hardware in the loop

35



DSP Builder Advanced Blockset AdvantagesDSP Builder Advanced Blockset Advantages

• Automatic pipelining to meet required fmax

• Similar performance as optimized HDL• Easy timing closure• Fewer compile iterations

Effortless FPGA implementation Fast design space exploration

• Fast multi-channel design implementation

• Automatic generation of control plane logic

• Efficient pipelining for multi-channel datapaths

• Ability to update design by editing system-level parameters

• Effortless FPGA device family retargeting

36



Understanding DSPB-AB With a Design Built With PrimitiveUnderstanding DSPB-AB With a Design Built With Primitive Start with a textbook representation of a design Build a Simulink design using identical building blocks

from DSP Builder Simulate the design using Simulink Add the number of channels, simulate Target the right FPGA family and compile

… let’s see this with an example

37



Start with a textbook representation …Start with a textbook representation …

38



Map the Textbook Representation to SimulinkMap the Textbook Representation to Simulink

39



Build the Top-Level Simulink DesignBuild the Top-Level Simulink Design

Christine Young

Quartus reference at bottom left corner needs a descriptor, per our trademark guidelines: should say Quartus II softwareI can't edit this graphic; please make this edit

40



Choose the Top-Level Parameter… SimulateChoose the Top-Level Parameter… Simulate

41



Choose the Target Device Family and CompileChoose the Target Device Family and Compile

42



Design Done in Hardware: >400-MHz PerformanceDesign Done in Hardware: >400-MHz Performance


A Typical Application Example—Repeater Application

44



Wireless Cellular Repeater DefinitionWireless Cellular Repeater Definition

Repeater [from Wikipedia]: A repeater is an electronic device that receives a weak or low-level signal and retransmits it at a higher level or higher power, so that the signal can cover longer distances without degradation

Wireless cellular repeaters: A kind of repeater that receives weak or low-level radio frequency signals from cellular networks and retransmits the signals at higher level or higher power. Wireless cellular repeaters are typically used to boost cell phone reception to areas where signal coverage by the infrastructure cellular network is weak

45



Basestation signal source

Extended coverage

Repeater donor unit

Repeater remote unit

Fiber-Optic RepeaterFiber-Optic Repeater

46



PA

PA

PA

PA

Donor Remote

FPGA implementation

Optical Repeater DiagramOptical Repeater DiagramD

up

lex

er

CP

RI

DDC

DUC

ADC

DAC

SERDES

SERDES

E/O

E/O

O/E

O/E

CP

RI

SERDES

SERDES

DUC

DDC

DAC

ADC

Du

ple

xe

r

47



Reference Design OverviewReference Design Overview

DUC/DDC Provides the link between digital baseband and analog RF front end of

generic transceiver High-throughput signal processing required makes FPGA

ideal platform

RF Front-end

Baseband

processing

ADC DDC

DAC DUC

RF IF Baseband

48



GSM Digital IF SolutionGSM Digital IF Solution


Resources Available

50



DSP Design ExamplesDSP Design Examples

More at http://www.altera.com/support/examples/dsp/exm-dsp.html

Function Design Entry Method

Achieving Unity Gain in Block Floating Point IFFT+FFT Pair

Coefficient Reload FIR Filter

Polyphase Modulation With Aliasing for Digital Up-Conversion

Implementing OFDM Modulation and Demodulation

Designing Digital Down Conversion Systems Using CIC and FIR Filters

Using CIC Decimation Filter With Multi-channel Support

CIC Interpolation Filter With Multi-Channel Data Support

Deinterlacer Using Weave Mode

Deinterlacer Using Bob Mode

Gamma Correction

YCbCr to RGB Color Space Conversion

Image Frame Resizing Using Scaler

Salt and Pepper Noise Removal Using 2D Median Filter

Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer

Chroma Resampler Up-Conversion

2D Sharpening Finite Impulse Response (FIR) Filter

Altera hardware description language (AHDL) VHDL MAX+PLUS® II graphic editor Verilog hardware description language (HDL) Tool command language (Tcl) Quartus II development tool Simulink model

51



Cyclone III Video KitCyclone III Video Kit

http://www.bitec.ltd.uk/ciii_video_dev_kit.html

Altera EP3C120F780 development board

Bitec HSMC quad video daughtercard 8 composite or 4 s-video inputs 1 high-definition (HD) (1080p) digital

video interface (DVI) output port or 1 TV (PAL/NTSC) output with

resolutions to 1024x768 and support for composite, s-video, or SCART (RGB) outputs

Bitec HSMC DVI daughtercard 1 HD (1080p) DVI output port (HDMI

with external adaptor) 1 HD (1080p) DVI input port (HDMI

with external adaptor)

Interfaces directly to the Altera Video and Image Processing (VIP) Suite

52



http://www.altera.com/products/devkits/altera/kit-dsp-professional.html

Stratix II GX Video KitStratix II GX Video Kit Stratix II GX video development

board with an EP2SGX90 Video interfaces

DVI inputs/outputs Four (4) standard definition (SD)/HD

SDI inputs/outputs, including dual-link SDI support

Asynchronous Serial Interface (ASI) inputs/outputs

Audio interfaces AES3 Sony/Phillips digital interface

(S/PDIF) External memory

DDR2 DIMM (72 bit at 266 MHz) 2-Mbyte SRAM 16-Mbyte flash (configuration)

Available now$4,995


Conclusion

54



ConclusionConclusion

DSP-based FPGA market will become $1.6B in 2010 Altera is first with 40-nm FPGAs: Stratix IV FPGAs deliver

highest DSP performance at the lowest power General IP cores and VIP Suite facilitate

customers’ designs Simulink+DSP Builder bridges the gap between algorithm

and hardware development, enhances productivity for FPGA hardware design, and makes FPGAs accessible for non-FPGA-experienced engineers


Backup


Altera Video Design

Example 1

57



Lay Down the Different Functions of the Video Signal ChainLay Down the Different Functions of the Video Signal Chain

Build the first version of your video signal chain using the Altera video IP building blocks

SDI in Function

2Function

3

SDI out

Function1

Function4

58



Connect the Blocks Using the Avalon ST Interface ProtocolConnect the Blocks Using the Avalon ST Interface Protocol

SDI in Function

2Function

3

SDI out

Function1

Function4

Avalon ST video interface

59



Add the Memory Subsystem and Frame Buffer ControllerAdd the Memory Subsystem and Frame Buffer Controller

SDI in

SDI out

Function1

Function4

Avalon Memory Mapped interface and arbitration

DDR memory controller

Function2

Function3

60



Add an On-Chip Micro-ControllerAdd an On-Chip Micro-Controller

SDI in

SDI out

Function4Function

2Function

3

DDR memory controller

Function1

Documents

© 2008 Altera Corporation—Public How to Facilitate Advanced Digital Signal Processing (DSP) Design When Facing Performance and Time-to- Market Challenges