© 2004 Altera Corporation The World’s Most Versatile Processor

© 2004 Altera Corporation

The World’s Most Versatile Processor

The World’s Most Versatile Processor


AgendaAgenda Benefits For Embedded Applications

Nios® II Overview & Background

Hardware Architecture

Software Development Tools

Development Kits

Hardware Acceleration

Customer Successes

Typical Applications

Testing and Quality Assurance


FPGA Benefits For Embedded Systems

FPGA Benefits For Embedded Systems


Product ChallengesProduct Challenges

Flash

SDRAM

CPU

DSP

I/O

I/O

FPGA

I/O I/O I/O

CPU DSP

FPGA

CPU

Obsolete in 2 Years Must Support for 7

Too Expensive, Need to Reduce Cost

I/O

Marketing Requires New Features To Stay Competitive 16 Week Lead Time

Must Qualify 2nd Source

Changing Standard Requires New Device,

Redesign Board

Need to ReduceBoard Size To Meet Form

Factor Requirements



Flash

SDRAM

CPU

DSP

I/O

I/O

FPGA

I/O I/O I/O

CPU DSP

FPGA

CPU

Solution: Replace External Devices with Programmable Logic

I/O



Flash

SDRAM

CPU

DSP

I/O

I/O

FPGA

I/O I/O I/O

CPU DSP


CPUFPGA

CPU

I/O

System-Level Integration


Problem: Reduce Cost, Complexity & PowerProblem: Reduce Cost, Complexity & Power

Flash

SDRAM

FPGA


Success?

StructuredASIC

High Volume ProductionMust Reduce Cost

Success!



Flash

SDRAM

FPGA


StructuredASIC

System Integration Tools Are Critical


Connecting IP BlocksConnecting IP Blocks Not All Blocks Are

Designed With The Same Interface

Design For Reuse Can Lead To Greater Time And Cost!

Blocks Need Integrating For Next Design

Design Block

Design Block

Design Block

Design Block


The Common SolutionThe Common Solution Manually Change The

Interface

Problems Need To Retest The Design Maintenance Of Multiple

Blocks Not Expandable

Design Block

Design Block

Design Block


SOPCBuilder

SOPC BuilderSOPC Builder Automated Integration

Tool Builds Bridges

Between Blocks Design Block Remains

Unchanged Automatically

Resolves Clock Domains Bit Widths Arbitration Etc

Design Block

Design Block

Design Block

Design Block


Development TimelineDevelopment Timeline

Block A

Block B

Block C

S/W Integration

System Test

Integration

H/W Test

Block D

What if there is an issue discovered during integration that requires more hardware?



Block A

Block B

Block C

S/W Integration

System Test

Integration

H/W Test

Block D

New Block

Project Completion


SOPCBuilder

Additional BlocksAdditional Blocks SOPC Builder Is

Always Extendable

No Need To “Hack” Into Existing System

Minimal Disruption To The Rest Of The System

Design Block

Design Block

Design Block

Design Block

Design Block



Block A

Block B

Block C

S/W Integration

System Test

Integration

H/W Test

Block D

New Block

Original Completion



Block A

Block B

Block C

S/W Integration

System Test

Integration

H/W Test

Block D

New Block

Original Completion

6 months saved on 2

year project


Nios II - World’s Most Popular Soft ProcessorNios II - World’s Most Popular Soft Processor

Over 15,000 Development Kits Shipped

Lively Nios Design Community

(www.niosforum.org)

Over 3,000 Active participants

Open Source Hardware & Software

Dozens of Reference Designs


Why Nios II?Why Nios II?

Nios II Helps You Reduce System Cost

Reduce Development Risk

Create a Unique Competitive Advantage


Benefits of Nios IIBenefits of Nios II

Flexible Functionality:

Adapt Quickly To Changing Standards

Add Features Late In Design Cycle To

Accommodate Market Requirements

Add Custom Hardware Functionality to Create

Competitive Barriers

Reduce Risk

Reduce Cost

Create Competitive Barrier



Boost System Performance:

Update System Hardware As Easy As Updating Software

Adapt To Competitive Solutions, Changing Customer and

Marketing Requirements, Evolving Standards

Reduce Risk

Reduce Cost




Reduced Development Time: Accelerate Development Through Design Reuse

Over 60 IP Functions Available

Prototypes in Hours, Not Days or Weeks System Level Design And Debug Tools Provide Rapid

Development and Iteration

Reduce Software Development Costs By Partitioning

Software Across Multiple CPUs Simpler Code Easier to Develop, Debug, And Maintain

Reduce Risk

Reduce Cost




Reduced Costs: Supports All Altera Device Families:

Low Cost FPGA For Rapid Deployment

Structured ASIC For High Volume Cost Reduction

Low Cost License

Royalty Free

Perpetual Use

Only $495

Reduce Risk

Reduce Cost




Extend Design / Product Life Time: IP Design Never Becomes Obsolete

Can Be Easily Adapted For Changes In External Devices

High Volume Option - Migrate To Hardcopy™

Reduce Risk

Reduce Cost



Success StoriesSuccess Stories


Nios Developers (Short List)Nios Developers (Short List)

© 2004 Altera Corporation© 2005 Altera Corporation - Confidential

AethraVoyager StarAethraVoyager Star

Altera Products Chosen:

Altera Value Proposition:Nios Processor + Low Cost

Cyclone FPGA = Perfect Microprocessor Solution

FPGA Flexibility Enables Acceleration via Custom Instructions and Peripherals

Industry:Wireless Communications

Mobile Video Conferencing System

Application:



Altera Value Proposition:High Performance for

Hardware Acceleration of Transport Control Protocols

Nios II Provides Greater Flexibility and Customization than Off-the-Shelf Processors

Industry:Wireline Communications

Network Acceleration Platform

Crescendo NetworksMaestro CN-5000ECrescendo NetworksMaestro CN-5000E

Application:



Industry:Broadcast

Professional Audio Mixing Console

Application:

EuphonixMC Intelligent Application ControllerEuphonixMC Intelligent Application Controller

Altera Value Proposition:Nios II Processor Replaced Existing

Processors for Lower Cost, Higher Performance

Device Integration



Altera Value Proposition:Cyclone Device Performs All

Digital Signal Processing in System

Low Cost Integration of DSP, Data Decoding, Memory Interface, MOST Interface, and Processor Interface

Industry:Automotive

Digital TV Receiver for Automobiles

HirschmannHybrid TV Receiver AntennaHirschmannHybrid TV Receiver Antenna

Application:


IntevacNightVistaIntevacNightVista


Altera Value Proposition:Lower Cost Solution than

DSP ProcessorHigh Integration, Small

Form FactorLow Power

Industry:Industrial

Night Vision Camera Application:



Altera Value Proposition:Higher Performance and Lower

Cost than Off-the-Shelf Processors for 256-bit AES Security

Greater Flexibility than ASSPVertical Migration and Nios

Roadmap Allows Multiple Upgrade Paths

Industry:Wireless Communications

Wi-Fi Security

KoolspanSecurEdge LockKoolspanSecurEdge Lock

Application:


Leica Geosystems TPS1200 Total Station Leica Geosystems TPS1200 Total Station


Altera Value Proposition:FPGA Flexibility at ASIC

CostHigh Component

Integration

Industry:Industrial

Survey Instrument Application:


ToolramaDiabloSport PredatorToolramaDiabloSport Predator




FPGA Flexibility Enables Acceleration via Custom Peripherals

Industry:Automotive

Automotive Diagnostic Tool

Application:





FPGA Flexibility Enables Acceleration via Custom Peripherals

Industry:Industrial

Wireless Energy Consumption Meter

Application:

Wireless Reading SystemsRECAPS Remote Energy MeterWireless Reading SystemsRECAPS Remote Energy Meter


End Black Dot ToolsEnd Black Dot Tools


Nios II OverviewNios II Overview Family of 3 Processor Cores

Performance Over 200 DMIPS Cost As Low as 35¢ of Logic

Powerful New Software Development Tools IDE / Debugger, RTOS,

TCP/IP Stack

Complete Portfolio of Development Kits Stratix® & Cyclone™ Kits Application-Specific

Expansion Boards

4X P

erfo

rman

ce o

f N

ios

¼ C

ost

of

Nio

s


Nios: Most Popular Soft Processor EverNios: Most Popular Soft Processor Ever Over 15,000 Kits Shipped

More Than All Other Soft-Core Processors Combined *

Development Kit Key to Success Complete Kit

Simple, Capable CPU

Easy to Use

Low Cost ($995)

Perpetual License

No Royalties

* Semico: Soft-Core Processor Licensees


Embedded Partners*Embedded Partners* Operating System Support Software Debugger Support

µClinux

Open Sourcewww.niosforum.orgOpen Sourcewww.niosforum.org

Open Sourcewww.niosforum.orgOpen Sourcewww.niosforum.org

code|labMS Visual Studio

WatchPoint Debugger

* http://www.altera.com/literature/po/ss_nios2tools.pdf



Flash

SDRAM

CPU

DSP

I/O

I/O

I/O FPGA

I/O I/O I/O

CPU DSP


FPGA


System-On-a-Programmable-Chip (SOPC)

System-On-a-Programmable-Chip (SOPC)

CPU is a Critical Control Function Required for System-Level Integration

Flash

SDRAM

FPGA


Soft CPUs Lead the Way Soft CPUs Lead the Way “ASIC design costs have more than doubled as we have moved from

0.18-micron to 0.13-micron & 90-nanometer (nm) products, causing a

large number of users to abandon traditional ASIC products . . . The new

breed of FPGA platforms is capturing a large number of new designs &

has the potential to be a major force in the industry.”

“We believe that FPGAs, with soft & hard processor cores, will account for more than one-third of all FPGA designs by the end of the decade . . . We expect that FPGAs with soft processor cores will capture the lion's share of this market, accounting for more than three-quarters of all FPGA platform design starts in 2010. FPGAs with soft processor cores are off to a fast start.”

--Platform

ASICs Jump-Start MarketSource: Gartner Dataquest November 2003


Soft Core AdvantagesSoft Core Advantages

High-PerformanceSOPC

Processor?Processor? How Many Processors?How Many Processors?

Low-Cost Embedded Solution

2,910 Logic Elements



Soft Core AdvantagesSoft Core Advantages

Stratix II EP2S180 & Nios II FastCPU 1% of Device220 DMIPs (each)

Complex Embedded System-on-a-Chip

Processor?Processor? How Many Processors?How Many Processors?

Cyclone Series & Nios II EconomyCPU < 20% of Device

20 DMIPs

Low-Cost Embedded Solution




Hardware ArchitectureHardware Architecture


Nios II ArchitectureNios II Architecture

Classic Pipelined RISC Machine

32-Bit Instruction Set Architecture

32-Bit Data Path

32 General-Purpose Registers

3 Instruction Formats

Separate Instruction & Data Caches

On-Chip Hardware (Multiply, Shift, Rotate)


Binary Compatibility / Flexible PerformanceBinary Compatibility / Flexible Performance

Nios II /fFast

Nios II /sStandard

Nios II /eEconomy

Pipeline 6 Stage 5 Stage None

H/W Multiplier &

Barrel Shifter

1 Cycle 3 Cycle Emulated

In Software

Branch Prediction Dynamic Static None

Instruction Cache Configurable Configurable None

Data Cache Configurable None None

Custom

Instructions

Up to 256


Accelerating SoftwareAccelerating Software Custom Instructions

256 User-Defined Instructions

Fixed & Variable Cycle Operation

User Logic Import Wizard

Called as C Subroutine

Example: CRC Algorithm (64 Kbytes)

0

5,000,000

10,000,000

15,000,000

20,000,000

25,000,000

Clo

ck C

ycle

s

Software Only Custom

Instruction

27 TimesFaster


Accelerating SoftwareAccelerating Software Hardware Acceleration

Processor & Accelerator Run Concurrently

More Work Per Clock

Lower fMAX, Power, Cost

Example: CRC Algorithm (64 Kbytes)

0

5,000,000

10,000,000

15,000,000

20,000,000

25,000,000

Clo

ck C

ycle

s

Software Only Custom

Instruction

HardwareAccelerator

27 TimesFaster

530 TimesFaster

ProgramMemory

Processor

DM

AD

MA

Accelerator

DM

AD

MA

DataMemory

ArbiterArbiter

DataMemory

ArbiterArbiter

AvalonSwitch Fabric


Traditional System DesignTraditional System Design

Data

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Timer16-Bit

UART8-Bit

DDR2

64-Bit

PCI64-Bit

SPI8-Bit

Arbiter

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Clock 1 Clock 2

Large Amount of Complexity


What If…What If…

UART 8-Bit

SPI8-Bit

Timer16-Bit

PCI64-Bit

DDR264-Bit


32-Bit


32-Bit

Arbiter

Play


What If…What If…

UART 8-Bit

SPI8-Bit

Timer16-Bit

PCI64-Bit

DDR264-Bit


32-Bit


32-Bit

Automated System Integration Generator

Basic Integration

• Bus Width Matching

• Address Decoding

• Interrupt Controller

Advanced Tasks

• Arbitration Logic

• Clock Domain Crossing

• Burst Transfers

Optimization

• System Throughput

• Resource Utilization


SOPC Builder System DesignSOPC Builder System DesignSelect IP Select Connections Generate System

Including

SOPC Builder Included in Quartus II Software


SOPC Builder Relieves Customers From Design & Verification TasksSOPC Builder Relieves Customers From Design & Verification Tasks

IP

User Logic

VHDL/Verilog

System Testbench

Header Files

CPU IDE Tools

RTL Simulation

RTL Synthesis

Place & Route

System Components Avalon Switch

Fabric Interconnect


Avalon Switch Fabric – Secret Sauce of SOPC Builder Avalon Switch Fabric – Secret Sauce of SOPC Builder Connects & Integrates

System Components Generated by SOPC

Builder Supports Basic and

Advanced System Integration Tasks

Optimizes Resource Usage Generated Uniquely for

Each System to Conserve FPGA Resources

Optimizes System Performance

Enables Design Reuse

CPU

Data Memory 1

Data Memory 2

Ethernet

Program Memory

I/O

Width-MatchArbiter

Width-Match

Interrupt Controller

Address Decoder

Avalon Switch FabricClock Domain

CrossingBurst

TransfersWait State Generation

Basic Tasks

Advanced Tasks

Faster Time to Market


PeripheralsPeripherals JTAG UART

Single JTAG Connection For:

Device Configuration Code Download Debug Target STDIO (printing) Flash Programming

Compact Flash Interface Mass Storage Support

True IDE Mode Compact Flash Mode

Software Supports Low-Level API MicroC/OS-II File System

Support µCLinux File System

Support


Software Development ToolsSoftware Development Tools


Leading-Edge Development ToolsLeading-Edge Development Tools

Nios II Integrated Development Environment (IDE)*

Target Connections Hardware (JTAG) Instruction Set Simulator ModelSim®-Altera Software

Advanced Hardware Debug Features Hardware Break Points, Data

Triggers, Trace Flash Memory

Programming Support

* Based on Eclipse Project


Nios II IDE: Project Management Nios II IDE: Project Management

Features:• Project Manager• Editor & Compiler• Debugger• Flash Programmer

Software Templates

•

• System Library Customized to Hardware

• Painless configuration

Software Components

• Provide easy-to-use examples

• Users May Add Their Own Templates

Included Software Components

•LWIP TCP/IP Stack

•MicroC/OS-II RTOS*

•Altera ZIP FS

•Nios II Run-Time Library

* MicroC/OS-II requires a separate license for product deployment!

Integrated Software Project Management


Nios II IDE: Editor & Software Tool-Chain Nios II IDE: Editor & Software Tool-Chain

Integrated Editor & Software Tool-chain Functionality

Project Management

• Basic Editing Capabilities

• C/C++ Syntax Highlighting

• Comprehen-sive Search

• Help Feature

Source Editor

• Project Navigation

• Source Files

• Compiler based on GNU tool chain

• Command-line Operation Possible

Compiler



Nios II IDE: Debugger Nios II IDE: Debugger

• Breakpoints

• Code Position

Source View

Basic Debug

• Run Controls

• Stack View

• Active Debug Sessions

•Variables

•Registers

•Signals

Memory View


Debug Targets:

• Hardware (JTAG)

• Instruction Set Simulator

• Logic Simulator (ModelSim)

Debug Scope:

• HW/SW breakpoints

• H/W Data Triggers

• Watchpoints

• Instruction Trace

Debug Scope

Integrated, Broad Capability Debug


Nios II IDE: Flash Programmer Nios II IDE: Flash Programmer

Programming Targets

• Manage & Program Flash Devices

• Utilizes JTAG Download Cable

Functionality

Memory Supported

CFI-Compliant Flash

Altera EPCS Memory Devices

Integrated FlashProgrammer Utility


• FPGA Configuration

• System Firmware


Nios II Processor System Hardware

DeviceDriver

DeviceDriver

DeviceDriver…

Nios II HAL: Runtime LibraryNios II HAL: Runtime LibraryProvides Following Features:

Interrupt Handling

Alarm Facilities

System & Device Initialization

Device Access

HAL Details:

Nios II Run-Time Library

Integrated with Newlib ANSI C Library

Unix-like API Provided for Development

_exit()close()closedir()fstat()getpid()gettimeofday()ioctl()isatty()kill()lseek()

open()opendirread()readdir()rewinddir()sbrk()settimeofday()stat()usleep()wait()write()

HAL API

HAL API

Shared LibraryShared Library

User Program


Software Data TriggersSoftware Data Triggers

Two Data Triggers Address, Data, Bus Cycle Break, Trigger Out, Trace Start/Stop Combine for “Super Trigger”

Address Range, Data Pattern with Mask


Software TraceSoftware Trace On-Chip Trace Buffer

16 Frames of On-Chip Trace Included

Display C Source, Assembly, Mixed Supports Altera Cable

USB Blaster


FS2 Debug UpgradesFS2 Debug Upgrades Software Upgrade ($695)

Add 2 Execution Breakpoints Add 2 Data Triggers Up to 128 Frames of On-Chip Trace Data Trace

External Trace Probe Upgrade ($4,995) 128K Frames of Off-Chip Trace


Supporting Real-Time ApplicationsSupporting Real-Time Applications

Micrium MicroC/OS-II

Real-Time Operating System

Scalable, Preemptive

Full Source Code

Developer’s License Included

Annual Shipper’s License

Subscription

Lightweight IP

Open Source TCP/IP Stack

Small Code Footprint

Berkeley Sockets API

Protocol Support:

IP, ICMP, UDP, TCP

Included with Nios II Development Kit


Product Provider Description Features

*Nios II IDE Altera IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace, FS2 Trace Probe

**code|lab ATI Mentor IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace, FS2 Trace Probe

Trace32 - ICD Lauterbach IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace

ISA-Nios/T First Silicon Solution (FS2)

JTAG Trace Probe

External Trace Capture, Timestamp, Complex Data Triggers

Watchpoint Sophia Systems Debugger Supports FS2 ISA-Nios/T

Debugger SupportDebugger Support

*Full Version Included in Nios II Dev. Kits **Evaluation Version Included in Nios II Dev. Kits


Product Provider Source

Code

Standards TCP/IP

Stack

File

System

Other

* MicroC/OS-II Micrium Yes RTCA/DO-178B Opt. Opt. GUI

Flash

* Lightweight IP

TCP/IP Stack

Open Source Yes Sockets API

IP, ICMP, UDP, TCP

µC/OS-II Support

Nucleus Plus ATI/Mentor Yes OSEK

µITRON

Opt. Opt. GUI, SNMP

RMON, SPAN

µCLinux Open Source Yes Incl. Incl.

NORTi MiSPO Yes µITRON Opt. Opt. PPP, SNMP

HTTP

PrKERNELv4 eSOL Yes µITRON

OSEK

Opt. Opt. USB, Mail

HTTP

RTOS / OS / Middleware SupportRTOS / OS / Middleware Support

* Full Version Included in Nios II Development Kits


Nios II - World’s Most Popular Soft ProcessorNios II - World’s Most Popular Soft Processor

Over 15,000 Development Kits Shipped

Lively Nios Design Community

(www.niosforum.org)

Over 3,000 Active participants

Open Source Hardware & Software

Dozens of Reference Designs


Hardware Acceleration AgendaHardware Acceleration Agenda

Embedded Development Challenges Design Considerations Examples & Results Availability & Road Map Altera Embedded Solutions


Embedded Development Challenges

Embedded Development Challenges


Embedded Development ChallengesEmbedded Development Challenges

Processor Hardware

Software Application

Industry Benches

Because Software Development Is Never Complete… Estimating Performance Is a Guessing Game

Past Experience Industry Benches Clock Frequency


Embedded Development ChallengesEmbedded Development Challenges

Processor Hardware


Risk: Over-Specifying Processor Higher Performance (Clock Frequency) Higher Power Consumption Higher Cost


Embedded Development ChallengesEmbedded Development Challenges Because Product Specs Change Continually…

Performance Requirements Are Not Fixed New Feature Required to Maintain Competitive Advantage Customer Driven Product Enhancements Customization vs. Industry Standards Last Minute Specification Changes

Processor Hardware



Processor Hardware

Embedded Development ChallengesEmbedded Development Challenges Changing Requirements Can Exceed CPU Performance

Force Change to Faster Processor Require Product Redesign Delay Entry Into Market



Solution: Scalable PerformanceSolution: Scalable Performance

Adapt to Changing Software Requirements Minimize Uncertainty Before Code Is Complete

Add Performance as More Software Features Are Added - Without Redesigning the Board

FPGAs Are a Natural Platform for Scalable-Performance Embedded Systems


Hardware/Software PartitioningHardware/Software Partitioning

Control Data Transform

Functions

High Latency: User Interfaces Housekeeping Functions Sequencing Operations Statistics Gathering

Low Latency: Image Processing Signal Processing Complex Math Functions Packet Processing

Software(CPU)

Hardware(Dedicated Logic)


Software Only PerspectiveSoftware Only Perspective When All You Have Is a Processor…


Functions


Software(CPU)

Higher Clock FrequencyIncrease Memory Bandwidth More Expensive Processor

Increased Power Consumption


Hardware Only PerspectiveHardware Only Perspective


Functions


When All You Have Is Logic…

Hardware(Dedicated Logic)

Reduced FlexibilityComplex Design

Longer Development


Hardware/Software PartitioningHardware/Software Partitioning


Functions

Best Performance Integrates Both Technologies



Software(CPU)

Hardware(Dedicated Logic)FPGA


ExternalCPU or

DSP

ExternalCPU or

DSP

3 Ways to Scale Performance3 Ways to Scale Performance

Multi-ProcessorSystem

PC

IP

CI

FPGA

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CustomInstructions

FPGA

HardwareAccelerators

FPGA CPUCPU

HardwareAcceleratorHardware

AcceleratorHardware

AcceleratorHardware

Accelerator

CPUCPUCustom

InstructionsCustom

Instructions

Add Processors(Internal and/or External)

Accelerate Individual CPU Performance (Add Application-Specific Instructions)

Accelerate Data Transformation Algorithms With Application-Specific Hardware


Accelerate With Multiple CPUsAccelerate With Multiple CPUs Additional CPUs Offer Performance

“Insurance Policy” Extend System Performance Even Late in the Design Reduce System Clock Frequency & Power Consumption

By Distributing Application Among Several CPUs Guaranteed Interrupt Performance

Reduce System Cost Use FPGA to Lower Hardware Cost

Replace Existing Processor Augment / Off-Load Existing Processor

Reduces Software Development Cost Transistors Are Cheap, Developers Are Expensive


Multi-CPU Reduce Development TimeMulti-CPU Reduce Development Time Each Processor Runs Fewer Lines of Code Smaller Projects Are Faster to Develop

“Double the Lines of Code (LoC) & Multiply Man-Months by Four” * Improves Reliability & Maintainability

Large Function Error Rates 2 to 6 Times Higher Than Smaller Routines **

* Subtract Software Costs By Adding CPUs-- Jack Ganssle, Embedded Systems Programming, May 2005

** An Empirical Study of Operating System Errors-- Chu, Yang, Chelf, Hallem, Proceedings of the 18th ACM Symposium on Operating System Principles, Oct 2001

0

100

200

300

400

500

600

0 50 100 150 200 250 300

Program Size in Thousands of Lines of Code (KLoC)

Man

-Yea

rs

Single CPUMulti-CPU (Limit 20KLoC / CPU)


Accelerating Software AlgorithmsAccelerating Software Algorithms Example: Cyclic Redundancy Count (CRC)

Useful for Error Detection in Data Transfer Iterative Process of XOR & Shifts Calculate CRC on 64k Byte Block of Data

* Processor Running at 100 MHz

0

1

1.5

2

2.5

3

Itera

tions

/Sec

ond

SoftwareOnly

0.5

3.5

4

4.5

CRC Algorithm

CRC Performance

Bob Garrett

Moved CRC Algorithm diagram from slide 17More appropriate oin this slide since this is where we introduce the CRC example


Extend CPU PerformanceExtend CPU Performance Add CRC Custom Instruction

CPU Fetches Data, Stores Results Ideal for Math & Logical Operations

e.g. Floating Point, Bit Manipulation Hardware Much Faster Than Software

RISC With a Little CISC


0

40

60

80

100

120

Itera

tions

/Sec

ond

SoftwareOnly

CustomInstruction

20

27 TimesFaste

r

27 TimesFaste

rOut<<

>>

&

CustomLogic

+-

A

B

Nios II Embedded Processor

Amy Lee

This slide is too busy. Can we split into two slides or delete one diagram?


Add Hardware AcceleratorAdd Hardware Accelerator Concurrent Data Processing

CPU Starts / Stops Co-Processor Accelerator Fetches Data & Stores Results CPU Continues to Execute Software Ideal for Block Data Operations Application-Specific Co-Processor


CRCAccelerator

CRCAccelerator

ProgramMemory

CPU

DataMemory

ArbiterArbiter

DataMemory

ArbiterArbiter

Co-Processor0

5,000

1,000

1,500

2,000

2,500

Itera

tions

/Sec

ond

SoftwareOnly

CustomInstruction

530 TimesFaster

530 TimesFaster


Altera Provides Hybrid ApproachAltera Provides Hybrid Approach

PacketProcessingAccelerator

PacketProcessingAccelerator

Image ProcessingAccelerator

Image ProcessingAccelerator

CustomInstructions

CustomInstructions

CPUCPU CPUCPUCPUCPU CPUCPU

CPUCPU

Accelerate Control & Data Transform Performance Multiple CPUs Custom Instructions Hardware Accelerators

ControlFunctions

DataTransform


Development KitsDevelopment Kits


Diverse Portfolio of Development KitsDiverse Portfolio of Development Kits Stratix

Altera Microtronix MJL El Camino GmbH

Cyclone Altera Microtronix MJL El Camino

Daughter Cards Microtronix: VGA / PS2 SLS: USB 2.0 El Camino GmbH: RF A/D D/A EasyFPGA: USB 2.0


Altera Nios II Development BoardAltera Nios II Development BoardBoard Information

Common Board Hardware Shared in Three Kits

Common Hardware Configuration: 1 MByte SRAM 16 MBytes SDR SDRAM 8 MBytes Flash Compact Flash Connector & 16 MByte Card 10/100 Ethernet MAC/PHY Two Serial Ports (RS-232) Two Daughter Board Expansion Headers Mictor Connector (Debug & Trace) 50-MHz Crystal (Socket), External Clock Input Two Seven-Segment LEDs, Eight User LEDs, & Four Pushbuttons

Only Difference Between Kits is FPGA

Purchase InformationBoard included in Nios II Development Kits

Altera Nios II Development Kits:

•Cyclone (NIOS-DEVKIT-1C20)

•Stratix (NIOS-DEVKIT-1S10)

•Stratix Pro (NIOS-PROKIT-1S40)

•Stratix II (NIOS-DEVKIT-2S30)

•Cyclone II (NIOS-DEVKIT-2C35)

Altera Corporation


Nios II - Leading The IndustryNios II - Leading The IndustryHighest

PerformanceHighest

Performance

Multi-Processor Hardware Acceleration Custom Instructions

Concept to System in Minutes FPGA > HardCopy Structured ASIC

GreatestFlexibilityGreatest

Flexibility

Most Powerful Design Tools

Most Powerful Design Tools

Fastest Timeto Market

Fastest Timeto Market

Processors Peripherals Optimized Interconnect

On-Chip Processor Debug SignalTap® II Logic Analyzer Performance Analysis Plug-Ins


Nios II: The Perfect-Fit ProcessorNios II: The Perfect-Fit Processor

Features Performance Cost Life Cycle

Stratix II

Stratix

Fast Time toMarket

HardCopy

Hardware Accelerator

Cyclone

3 CPU Cores

Future Proof

Avalon Switch Fabric

Peripherals

256 CustomInstructions


Learn More Through TrainingLearn More Through Training

Speed Time to Market with Latest Software Features & Techniques

Reduce Cost by Learning to Create Smaller, Faster Designs

Take Full Advantage of the Power of Nios Designing with Nios & SOPC Builder Designing a System on a Programmable Chip

Learn More & Register at www.altera.com/training


Thank YouThank You


Customer SuccessesCustomer Successes


Agilent Alcatel Boeing Bosch Canon Casio Cisco Systems Eastman Kodak EMC Fujitsu General Instrument Hewlett Packard Hitachi IBM Kodak LM Ericsson Lucent Technologies SAS Matsushita Matsushita Communications

Motorola Motorola Communications NEC Nintendo Nokia Telecommunications Nortel Philips Research Philips Business Communications Philips Multimedia Rockwell Sanyo Sharp Siemens Siemens Information & Communications Sony Thomson Toshiba

Nios & Nios II Developers (Partial List)Nios & Nios II Developers (Partial List)


Remote Meter ReadingRemote Meter ReadingCustomer: Wireless Reading Systems, Norway

Product: Remote Energy Consumption Acquisition Processor System (RECAPS).

Reasons for Choosing Nios:

Control of Radio Transmitter/OCR Functions

Replace FPGA & Standalone Processor with

Cyclone at 1/5 Cost

Increased Integration Reducing Size

Decrease in System Power

For More Details:www.altera.com/corporate/news_room/releases/products/nr-wireless_meter_reading.html


Medical DiagnosisMedical DiagnosisCustomer: BioMeridian, USA

Product: Stress Measurement Device


More Flexible than Off-the-Shelf Processors

Ease of Use

Custom Instructions

Performance Boost

66% Power Reduction

For More Details:www.altera.com/corporate/news_room/releases/products/nr-nios_delivers_goods.html


Streaming Video InterfaceStreaming Video InterfaceCustomer: Media Works Technology, USA

Product: Video Capture Card


Custom Processor (Exact Fit)

Configurable Feature Allows Future

Extensions of Wireless Interface

Capability to Profile Application to Adjust

Hardware & Software Partitions

Custom Instruction & Hardware Acceleration

Feature

For More Details:www.eetimes.com/in_focus/communications/OEG20021202S0060


SDH/Sonet TransmissionSDH/Sonet TransmissionCustomer: Alcatel, Italy

Product: Optical Multi-Service Node


Power & Flexibility of Soft-Core Embedded

Processor for FPGA

Reliable Platform for Developing Complex

Algorithms

Gigabit Throughput Speeds By Use of Custom

Instruction & Simultaneous Multi-Master Bus

Architecture

For More Details:www.altera.com/corporate/news_room/releases/releases_archive/2002/corporate/nr-alcatel.html


Telephony SystemTelephony SystemCustomer: Philips, France

Product: SOPHO iS3000 series of iSPBX

Reasons for Choosing Nios: Allowed Implementation of Field Upgradable

ISDN Protocol Handler Reconfiguration Lowered Costs for:

Maintenance Development Final Product

Improved Performance & Reliability of Video Conference, IP Gateway Services & Computer Telephony Product Features

For More Details:www.altera.com/corporate/news_room/releases/releases_archive/2002/products/nr-nio_philips_sopho.html


Storage NetworkingStorage NetworkingCustomer: Pirus Networks, USA

Product: PSX 1000 Storage Network Switch


Flexibility to Implement Field Upgrade

Adapt to Changing Standards

Ability to Implement Backplane Solution

Traffic Management Done By Nios Processor

Packet Processing in FPGA

For More Details:www.eet.com/story/OEG20020517S0066


Fibre Optic MeasurementFibre Optic MeasurementCustomer: Finnisar, USA

Product: Fibre Optic Network Performance Systems


Nios Performance

Time Saved in Having “Ready to Use” IP

Support for Stratix FPGA

For More Details:www.altera.com/corporate/news_room/releases/products/nr-nio_kit_stratix.html


Automotive AV SystemAutomotive AV SystemCustomer: Johnson Controls Inc, USA

Product: Automotive AV System


“For our new automotive audio video system, we have selected Altera's FPGAs because their performance, quality, & temperature specifications meet our automotive requirements. The flexibility & programmability of Altera's devices combined with its powerful Nios embedded processor provide us with the perfect solution for developing new products”

For More Details:www.altera.com/corporate/news_room/customer_quotes/cqt-index.html


All Optical SwitchAll Optical SwitchCustomer: Lucent Technologies Optical Networking, USA

Product: All Optical Switch for Routers


Flexibility

Performance from 32-Bit Nios Implementation

Altera’s Ability to Enhance Next-Generation

Products

Aid to Delivering Cost-Effective & High-

Performance Systems



Bluetooth Printer InterfaceBluetooth Printer InterfaceCustomer: Celestica, USA

Product: Bluetooth Printer Interface


Rapidly Modify Prototypes to Respond to

Evolving Customer Needs

Performance: Handling of Complex Nested

Software Code

Standard GNU Tools Simplified Porting

Same Code Could Be Used for Bluetooth

Application Running on PC & Nios Target



Access RouterAccess RouterCustomer: Telena Communications, USA

Product: Access Router

Reasons for Choosing Nios: Nios Development Board Enabled Early

Prototyping of Software Became Part of First Prototype

Availability of Software & Hardware to Support LCD Interface Enabled Internal Status to Be Read

Efficient On-Chip Interfacing to L2 & L3 Hardware Features of the ATM & Packet Over-SONET Design



Industrial Control TerminalIndustrial Control TerminalCustomer: AltaCom, France

Product: Flexible Industrial Control Terminal

Reasons for Choosing Nios: Flexibility to Implement Custom Options

240*128 Pixel Graphics Control 40*16 Character Mode Display Up to 512K SRAM 1 M Flash 2 UART, RS232/485 1 SPI 10-BaseT

For More Details:www.altacom.fr


Board TestBoard TestCustomer: EL Camino, Germany

Product: PCB & ASIC Test System

Reasons for Choosing Nios:Flexibility to Implement Custom Options for Board Interface Testing

Ease of Implementing On-Chip Test Pattern Generation for ASIC Prototying

“You’ll never again have to worry about discontinued processors or peripherals & the associated hassle with last-time buys, major re-designs, or re-writing software”

For More Details:www.ecal.de


IP Switch RouterIP Switch RouterCustomer: Marconi

Product: BXR-48000 IP & Multiservice Switch Router

Reasons for Choosing Nios:Unprecedented Versatility with Stratix FPGAs Performance & Cost Savings128-bit High-speed Transceiver Logic (HSTL) Bus at 200 MHz.

“Our Development Team Determined That Altera FPGAs Were The Only Devices That Could Perform These Tasks, Given That They Combine Significant Embedded Memory With Exceptional Speed”

For More Details:www.altera.com/corporate/news_room/releases/releases_archive/2003/products/nr-marconi.html


Night Vision CameraNight Vision CameraCustomer: Intevec Inc, USA

Product: Night Vision Camera Image Processing & Control

Reasons for Choosing Nios:Replace DSP with Cyclone & Nios

Reduced Cost By 20%Reduce Power Consumption (1/5 Previous System)

Form Factor Reduction of 50%Reduce 5 Separate Boards to OneLower Manufacturing CostsHigher Reliability

Rapid Development (4 Months)Field Upgrade Enabled Expanded Roadmap

For More Details:www.altera.com/corporate/news_room/releases/products/nr-NightVista-Intevac.html


Video ProcessingVideo ProcessingCustomer: Avvida Systems Inc, Canada

Product: Tsunami PCI Video Processing Engine


Provides Ability to Mange Hardware

Accelerators Implemented in FPGA to Process

Video in Real Time

Accelerators Make Use of DSP Capability In

Stratix FPGA

High Integration SOPC Systems

For More Details:www.altera.com/corporate/news_room/releases/releases_archive/2002/products/nr-avvida_pci.html


Typical ApplicationsTypical Applications


Typical ApplicationsTypical Applications

Custom Microcontroller Offload Main Processor Replacement for State Machine I/O Processor Board Bring-up & System Test


VGAVGAControllerController


Custom MicrocontrollerCustom Microcontroller

CPUCPUCPUCPU

USBUSBUSBUSB

SDRAMSDRAM

10/10010/100EthernetEthernet

MACMAC


MACMAC

Multiple Discrete Off-the-Shelf Devices.Vulnerable to Obsolescence.

before Nios Processor

10 UARTs10 UARTs10 UARTs10 UARTs


NiosCPU

Altera FPGA


MACMAC


System-on-a-Programmable-Chip Solution.Architecture Never Goes Obsolete.

UARTUART

after Nios ProcessorCustom MicrocontrollerCustom Microcontroller

UARTUART

UARTUART UARTUART

UARTUART UARTUART

UARTUART UARTUART

UARTUART UARTUART

CustomLogic

SDRAM

USBUSBControllerController

SDRAMSDRAMControllerController

Ava

lon

Sw

itch

Fab

ricJT

AG

Host PC


Offload Existing CPUOffload Existing CPU

PowerPCPowerPC

I/OI/OI/OI/OI/OI/O

CPU Performance Limited by I/O Processing

UserUserDesignDesignUserUser

DesignDesign

Stratix FPGA

before Nios Processor


PowerPCPowerPCPowerPCPowerPC

I/OI/OI/O


DesignDesign

Offload Existing CPUOffload Existing CPU

Improved CPU PerformanceImproved CPU Performance

NiosNios

after Nios Processor

I/OI/OI/O

Stratix FPGA


Augment Existing CPUAugment Existing CPU

Greater I/O Bandwidth Capacity thanMain CPU Alone

PowerPCPowerPCPowerPCPowerPCImproved CPU PerformanceImproved CPU Performance

I/OI/OI/O


DesignDesign

NiosNiosI/OI/OI/O

I/OI/OI/O

NiosNios

after Nios Processor


System A

Development Complexity High

Development Time High

Resource Utilization High

Design Flexibility Low

State Machine ReplacementState Machine ReplacementSystem A

Control Control

ControlControl

Circuit2

Circuit4

Circuit3

System B

Circuit1

Circuit2

Circuit3

Circuit4

Nios

System A B

Development Complexity High Lower

Development Time High Lower

Resource Utilization High Lower

Design Flexibility Low Higher

Circuit1


APEX 20K

I/O ProcessingI/O Processing

Scalable Solution.Custom I/O Stream Processing Not Available in

ASSPs.

AlteraFPGA

Nios

MACPacketBuffer

DMA

Nios

MACPacketBuffer

DMA

Nios

MACPacketBuffer

DMA

Nios

MACPacketBuffer

DMA

Nios

UserLogic


Board Bring-Up & System TestBoard Bring-Up & System Test

MAC/PHY

ASSP

I/O

I/O

Flash

SDRAM

JTAGByteBlaster II Cable

NiosNiosSystemSystem

Download Hardware & Software via JTAG

Status & stdio Outputvia JTAG


Testing & Quality Assurance

Testing & Quality Assurance


Nios II IP Verification OverviewNios II IP Verification Overview Functional Testing – Self-Checking Test Benches

Verify That Product Functions As Specified All Modes of Operation All Architectural Variations Corner Cases User Interface

Compile C-Code, Run in Hardware & Instruction Set Simulator Test Farm: 28 PCs Connected To Development

Boards Suite of Standard Software Designs (Simple to

Complex) Random Instruction Testing


Test EnvironmentTest Environment We Use the Same Tools Our Customers Use…

SOPC Builder ModelSim (OEM) (SE) (PE) Quartus II Nios, Nios II & Associated Executable Images Development Kit Boards

. . . to Generate the Same Kinds of Systems in: Hardware Software Simulation


Test FlowTest Flow

SOPCBuilderSOPC

Builder

Quartus IIQuartus IIModelSimModelSim

C CompilerC Compiler

ptf

C

HDL

elf

stf

sof

hex

dat

Nios II ISSNios II ISS

Hardware

Software

HardwareTest

HardwareSimulation

Software Simulation


Hardware TestHardware Test Self-Testing Nios II Systems Running in

Hardware Directed Tests

Functional Coverage to Specification

Random System Tests Interrupt Frequency / All IRQs Memory Location (Base Address) & Latency Inclusion Or Exclusion Of Various Components 100’s of Millions of Random Instructions in Random Order

Self-Testing Nios II Systems Running in ModelSim Software


Daily TestingDaily Testing Run 24 Hours/Day,

7 Days/Week Automated &

Regression Errors Generate SPR

Fixed or Added to Errata

Errata Included with Each Release

Bug Fixes Added to Regression Tests Run On All Future

Builds


BackupBackup

Documents

© 2004 Altera Corporation The World’s Most Versatile Processor