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© 1998 Altera Corporation
1
®
Achieving High Performance and Optimal Utilization
in Altera's FLEX 10K Family
2
© 1998 Altera Corporation ®
Course Outline
DISCUSSIONS LABS
FLEX 10K Family Overview
FLEX 10 Family Devices– Architecture Construction– Architectural Features 2– Designing with FLEX 10K Family 1
FLEX 10K Family In-System Considerations
FLEX 10K Family Configuration
© 1998 Altera Corporation
3
®
FLEX 10K Family Overview
4
© 1998 Altera Corporation ®
Altera Offering
MAX7000
MAX 7000E, S, A, AE
MAX 9000
100
2000 5000 12,000
FLEX 8000 FLEX 6000
FLEX 10K
24,000 500,000
200
Use
r I/
O
Usable Gates
5
© 1998 Altera Corporation ®
FLEX Families Overview
Look-up Table (LUT)-Based Architecture
Register-Rich Architecture
Fabricated in SRAM Process
Flexible Logic Element MatriX (FLEX)
6
© 1998 Altera Corporation ®
FLEX 5.0 V, 3.3 V, 2.5 V Offerings
5.0 V, 3.3 V, and 2.5 V Devices in FLEX 10K Family
Voltage Process Technology Device(s)
5.0 V 0.50- 3LM FLEX 10K
3.3 V 0.30- 3LM FLEX 10K50V
0.35- 3LM FLEX 10K130V
3.3 V 0.30-, 0.35- 4LM FLEX 10KA
2.5 V 0.25 - 5LM FLEX10K100B
2.5 V 0.25 - 5LM FLEX 10KE
7
© 1998 Altera Corporation ®
FLEX 10K/V/A/B Devices
All Devices Have JTAG BST Circuitry(IEEE Std. 1149.1-1990 Compliant)
Available at No Logic Cost
Refer to www.altera.com for Latest Packaging Information
Typical Gates
Features
Registers
Max. UserI/O
10,000
EPF10K10
EPF10K10A
720
134
20,000
EFP10K20
1,344
189
30,000
EFP10K30
EPF10K30A
1,968
246
40,000
EFP10K40
2,576
189
50,000
EFP10K50EPF10K50VEPF10K50A
3,184
310
70,000
EFP10K70
4,096
358
100,000
EFP10K100
EPF10K100AEPF10K100B
5,392
406
130,000
EPF10K130VEPF10K130A
7,120
470
250,000
EPF10K250A
LogicElements
576 1,152 1,728 2,304 2,880 3,744 4,992 6,656 12,160
RAM Bits 6.144 12,288 12,288 16,384 20,480 18,432 24,576 32,768 40,960
12,624
470
8
© 1998 Altera Corporation ®
FLEX 10KE Devices
Typical Gates
Features
Registers
Max. User I/O
30,000
EPF10K30E
1,968
246
50,000
EPF10K50E
3,184
310
100,000
EPF10K100E
5,392
406
130,000
EPF10K130E
7,120
470
EPF10K250E
LogicElements
1,728 2,880 4,992 6,656
RAM Bits 24,576 40,960 49,152 65,536
250,000
12,160
81,920
12,624
470
EPF10K200E
200,000
9,984
98,304
10,448
470
All Devices Have JTAG BST Circuitry(IEEE Std. 1149.1-1990 Compliant)
Available at No Logic Cost
Refer to www.altera.com for Latest Packaging Information
9
© 1998 Altera Corporation ®
Growing Your Design: Vertical Migration
Vertical Migration– GND & VCC Pins in Same Locations– Dedicated Inputs & Configuration Pins in Same
Locations– Remaining Pins Are User I/O or No-Connects (N.C.)– Possible Only within Each FLEX Family
All Devices within a Given Package Vertically Migratable
• Even When Moving among Devices of Different Voltages
See Vertical Migration within In-System Appendix for More Information
10
© 1998 Altera Corporation ®
Growing Your Design: SameFrame Pin-Out
Altera’s FineLine BGA Packages Offer Migration– Among Densities– Among Packages
Mutual Power & Ground(Smaller & Larger BGA Packages)
Mutual I/O & Configuration(Smaller & Larger BGA Packages)
Additional I/O & Configuration(Larger Package)
Additional Power & Ground(Larger Package)
Refer to www.altera.com for Latest Packaging Information
11
© 1998 Altera Corporation ®
Altera MultiVolt™ Circuitry
VCCINT
GNDINT
Core
VCCIO
GNDIO
5.0-VSystem
3.3-VSystem
MultiVoltTM Circuitry Separates Power & Ground for Device Core & I/O;Allows FLEX Device to Bridge between Systems of Different Voltages
12
© 1998 Altera Corporation ®
Altera MultiVolt™ Circuitry
Refer to Data Sheets for packages that do / do not feature MultiVoltTM
* These voltages not tolerated on individual inputs clamped to VCCIO with Individual Logic Option PCI_I/O (See In-System Appendix for More Information)
FLEX 10K
FLEX 10KA
EPF10K50V, EPF10K130V
EPF10K100B
EPF 10KE
Device
5.0
3.3
3.3
2.5
2.5
VCCINT
5.0
3.3
3.3
2.5
3.3
3.3
2.5
3.3
2.5
VCCIO
X
X
X
2.5
X
X
X
X
X
3.3
X
X
X
X
X
X
5.0
X
X
X
X
X
X
2.5 3.3 5.0
Drives (TTL) Driven by
X
X
X
X*
X
X
X*
X
X*
X
X
X*
X*
X
X*
X*
X*
X*
13
© 1998 Altera Corporation ®
Altera MultiVolt™ Circuitry
More Information Regarding– MAX+PLUS® II Considerations– Configuration Considerations– System Hardware Considerations– Device Timing Information
14
© 1998 Altera Corporation ®
EPF10K50RC240-3
EPF Family Signature
10K50 Device Type
R Package Type (L = PLCC, R = RQFP, etc.)
C Operating Temperature (Commercial, Industrial)
240 Pin Count (Number of Pins on Package)
-3 Speed Grade (-1, -2, -3, -4, -5)(Smaller Speed Grade = Faster Device)
FLEX Device Part Numbers
© 1998 Altera Corporation
15
®
FLEX 10K FamilyArchitecture & Features
16
© 1998 Altera Corporation ®
Architecture & Features
Dedicated Inputs, Dedicated Clocks Logic Array Block (LAB) Logic Element (LE)
– Register Packing– Carry Chain– Cascade Chain
FastTrack Interconnect™
I/O Element (IOE) Embedded Array Block (EAB)
17
© 1998 Altera Corporation ®
Device Terminology
Logic Element (LE)– FLEX Logic Cell (LC)– Grouped into LABs (Logic Array Blocks) of 8 LEs Each
FastTrack Interconnect– Continuous Routing Structure of a FLEX Device– Grouped into Row, Column, & LAB Local
Interconnects
18
© 1998 Altera Corporation ®
FLEX 10K Family Block Diagram
4 Dedicated Inputs,2 Dedicated Clocks
Chip-Wide Reset,Chip-Wide Output Enable
EmbeddedArrayBlock(EAB)
EmbeddedArrayBlock(EAB)
I/O Element(IOE)
Logic ArrayBlock
LocalInterconnect
ColumnFastTrackInterconnect
LogicElement
RowFastTrackInterconnect
Peripheral Control Bus
19
© 1998 Altera Corporation ®
Global Nets Appendix Contains Important Device Details & Instructions for Assigning Signals to
Global Nets Using MAX+plus II
Dedicated Inputs, Clocks
4 Dedicated Inputs Drive 4 Global Control Nets that Can Drive– Any LE Control Signal (Clock, Clear, Enable)– Four Nets of the “Peripheral Control Bus”
(Clock, Clear, Output Enable)– Data– Any Combination of Above
4 Global Control Nets Can Also Be Driven by Internal Logic
2 Dedicated Clocks Drive 2 Global Clock Nets that Can Drive– LE Clock Signals– IOE Clock Signals– Data– Any Combination of Above– Cannot Serve as Any Other Control Signal
20
© 1998 Altera Corporation ®
FLEX 10K Family Block Diagram
EmbeddedArrayBlock(EAB)
EmbeddedArrayBlock(EAB)
EmbeddedArrayBlock(EAB)
A1
B1
A2
B2
A
B
1 2
Rows Are Designated by Letters
Columns Are Designated by Numbers
21
© 1998 Altera Corporation ®
Row Interconnect
Global Control Nets,Dedicated Clocks
LABControlSignals
FLEX 10K Family LAB
LABLocal
Interconnect
ColumnInterconnect
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
22
© 1998 Altera Corporation ®
Each LAB Supports for its Registers– 2 Clock Signals
– 2 Clear/Preset Signals
FLEX 10K Family LAB Control Signals
Global Control Nets
LAB Clock 1
LAB Clock 2
LAB Clear/Preset 1
LAB Clear/Preset 2
4
4
LABLocal
Interconnect
DedicatedClocks
2
23
© 1998 Altera Corporation ®
FLEX 10K Family Logic Element
Look-UpTable(LUT)
CarryChain
CascadeChain
Carry-In Cascade-In
DATA1
DATA2
DATA3
DATA4
LAB Clear/Preset 1
LAB Clear/Preset 2
ClockSelect
LAB Clock 1
LAB Clock 2
Carry-Out Cascade-Out
Clear/PresetLogic
PRN
CLRN
To Row,Column
InterconnectsD Q
Chip-Wide Reset
ENA
Multiplexer for Register Packing
To LABLocal
Interconnect
24
© 1998 Altera Corporation ®
Combinatorial Logic
Look-UpTable(LUT)
CarryChain
CascadeChain
Carry-In Cascade-In
DATA1
DATA2
DATA3
DATA4
ClockSelect
Carry-In Cascade-Out
D
To LABLocal
Interconnect
4-Input LUT LUTs Implement
Complex Functions in 1 Level of Logic
To Row,Column
Interconnects
25
© 1998 Altera Corporation ®
Sequential Logic
DATA1
DATA3
DATA4
LAB Clear/Preset 1
LAB Clear/Preset 2
ClockSelect
LAB Clock 1
LAB Clock 2
Clear/PresetLogic
PRN
CLRN
D Q
Chip-Wide Reset
ENA
To LABLocal
Interconnect
Register Controls– Asynchronous CLRN– Asynchronous PRN– Active High ENA
To Row,Column
Interconnects
26
© 1998 Altera Corporation ®
Preset Emulation
For Registers That Have a Preset Signal & No Clear Signal Connected a Design
MAX+plus II Emulates Preset with “Not-Gate-Push-Back”
Preset Net Connected to CLRN Port of Register
Both Register Output & Input Inverted
Inversions Are Implemented in LUTs or IOEs: No Impact on Timing or Utilization
PRN
D Q
Preset
CLRN
D Q
Preset
27
© 1998 Altera Corporation ®
Preset Emulation
For Registers on which Both Preset & Clear Signals Are Present, Preset Emulated with Asynchronous Loading of a “1”– DATA3 Input from LUT Is Connected to VCC
– When Preset Signal Is Active, DATA3 Is Loaded in Register
Look-UpTable(LUT)
DATA1
DATA2
VCC
DATA4
LDN
CLRN
D Q
DATA
Preset
Clear
28
© 1998 Altera Corporation ®
Architecture Features
Controlling These Features Controls Design Performance & Utilization
Register Packing– Allows Using LUT & Register of Same LE Separately
Carry Chain– Arithmetic Functions
Cascade Chain– Wide Fan-in Functions
Features are Controlled through MAX+plus II
29
© 1998 Altera Corporation ®
Register Packing
Look-UpTable(LUT)
CarryChain
CascadeChain
Carry-In Cascade-In
DATA1
DATA2
DATA3
DATA4
LAB Clear/Preset 1
LAB Clear/Preset 2
ClockSelect
LAB Clock 1
LAB Clock 2
Carry-Out Cascade-Out
Clear/PresetLogic
PRN
CLRN
D Q
Chip-Wide Reset
ENA
Multiplexer for Register Packing
To LABLocal
Interconnect
Allows LUT & Register of a LE to Be Used Separately
Can Improve Utilization
To Row,Column
Interconnects
30
© 1998 Altera Corporation ®
Look-UpTable(LUT)
CarryChain
CascadeChain
DATA1
DATA2
DATA3
DATA4
To Row,Column, and/orLAB LocalInterconnects
D Q
Non-Register-Packed LE
For Purely Combinatorial Logic, Register of an LE Is Bypassed LE Has One Output that Drives:
– Row and/or Column Interconnects– LAB Local Interconnect– Possibly All Simultaneously
Register Bypass Path
31
© 1998 Altera Corporation ®
To LABLocal
Interconnect
Look-UpTable(LUT)
CarryChain
CascadeChain
Register Bypass Path
DATA1
DATA2
DATA3
DATA4
PRN
CLRN
D Q
ENA
Register-Packed LE
Register Can Have an Independent Input– Input Can Be Shared with LUT
LE Has Two Outputs: One from LUT, One from Register– One Must Drive Row and/or Column Interconnects– One Must Drive LAB Local Interconnect
To Row,Column
Interconnects
32
© 1998 Altera Corporation ®
Register Packing
Register Packing Can Improve Utilization
– May Cause Routing Congestion• Both Row/Column & LAB Local
Interconnects Used– May Increase Compilation Time– When Used, Provides MAX+plus II
the Option of Register Packing LEs wherever Optimal
• Not All LEs Register Packed– “Off” by Default
5% - 15% Improvement
33
© 1998 Altera Corporation ®
Carry Chain
Look-UpTable(LUT)
CarryChain
CascadeChain
Carry-In Cascade-In
DATA1
DATA2
DATA3
DATA4
LAB Clear/Preset 1
LAB Clear/Preset 2
ClockSelect
LAB Clock 1
LAB Clock 2
Carry-Out Cascade-Out
Clear/PresetLogic
PRN
CLRN
D Q
Chip-Wide Reset
ENA
To LABLocal
Interconnect
To Row,Column
Interconnects
34
© 1998 Altera Corporation ®
Without Carry Chain
With Carry Chain
8 x 8 MultiplierEPF10K10-3
168
135
Logic Used(LEs)
56.7
33.6
Longest Delay(ns)
Carry Chain
Using the Carry Chain Can:– Improve Performance– Improve Utilization
35
© 1998 Altera Corporation ®
LE Modes & Carry Chain
Logic Elements Can Operate in 4 Possible Modes:– Normal– Arithmetic– Up/Down Counter– Clearable Counter
MAX+plus II Automatically Configures LE Mode Based on Design Logic & Use of the Carry Chain
Each Mode Uses LE Resources Differently, Has Unique Advantages
36
© 1998 Altera Corporation ®
FLEX LE Normal Mode
One LUT with Four Independent Inputs
Normal Mode Is Configuration of the LE
– For General Combinatorial Logic
– Arithmetic Functions When the Carry Chain Is Not Used
Data 1
Data 2
Data 3
Data 4
Carry Chain
Cascade Chain
LUT D Q
CarryIn
Cascade In
Cascade Out
CLRN
PRN
Data Result(To Interconnect)
37
© 1998 Altera Corporation ®
Using the Carry Chain Allows MAX+plus II To Configure LEs In
– Arithmetic Mode
– Counter Modes
Based on Design Logic In Arithmetic and Counter Modes, an LE Contains
– Two LUTs, Each with Three Inputs, at Least Two of which Are Shared
FLEX LE Arithmetic, Counter Modes
LUT
Carry In
(Dedicated Routing Resource)
LUT
Carry Out(Dedicated Routing Resource)
Arithmetic Result(To Interconnect)
38
© 1998 Altera Corporation ®
FLEX LE Arithmetic Mode
Cascade Chain
D Q
Cascade In(Dedicated
Routing Resource)
Cascade Out(Dedicated
Routing Resource)
CLRN
PRN
LUT
Carry In
(Dedicated Routing Resource)
LUT
Carry Out(Dedicated Routing Resource)
Data1
Data2
Two LUTs, Each with Same Three Shared Inputs - Carry, Data1, Data2– First LUT Generates Sum Result– Second LUT Generates Carry for Next Stage of Arithmetic Function
Sum Bit Result(To Interconnect)
39
© 1998 Altera Corporation ®
Y2A2B2
Example: Normal & Arithmetic Modes
CARRY1
Y1A1B1
CARRY2
A + B = Y
40
© 1998 Altera Corporation ®
Example: Normal & Arithmetic Modes
Y1
LE
LUTA1
B1
CARRY1
CARRY2(To Interconnect)
LE
LUTA1
B1
CARRY1
Normal Mode
Y1
LE
LE
LUTA2B2
CARRY1
Arithmetic Mode
LUT
Y2LUTA2B2
CARRY2
LUT
CARRY2(Dedicated Resource)
Normal Mode: Logic Uses 2 LEs Arithmetic Mode: Result & Carry Generated in 1 LE
41
© 1998 Altera Corporation ®
FLEX LE Up/Down Counter Mode
Two LUTs, Each with Three Inputs - Carry & Register Feedback Shared– First LUT Generates Counter Bit Result– Second LUT Generates Carry for Next Stage of Counter– Feedback from Register Output into LUT a Dedicated Resource within LE
D Q
CLRN
PRN
LUT
Carry In
(Dedicated Routing Resource)
LUT
Carry Out(Dedicated Routing Resource)
Enable
DataCounter Bit Result (To Interconnect)
U/D Control
Load Control
Cascade Chain
Cascade In(Dedicated Routing Resource)
Cascade Out(Dedicated Routing Resource)
42
© 1998 Altera Corporation ®
FLEX LE Clearable Counter Mode
D Q
CLRN
PRN
LUT
Carry In
(Dedicated Routing Resource)
LUT
Carry Out(Dedicated Routing Resource)
Enable
Data
Clear Control
Load Control
Two LUTs, Each with Three Inputs - Carry & Register Feedback Shared– First LUT Generates Counter Bit Result– Second LUT Generates Carry for Next Stage of Counter– Feedback from Register Output into LUT a Dedicated Resource within LE
Counter Bit Result (To Interconnect)
43
© 1998 Altera Corporation ®
Counter Modes
16-Bit Loadable Counter with Count Enable & Up/Down Control– Using LE Modes (Carry Chain) Can Improve Utilization, Performance– Using “Free” Controls of Counter Modes Maximizes LE Efficiency
Without Carry Chain (Normal Mode) 43 33.67
With Carry Chain(Up/Down Counter Mode) 16 125.00
Additional Synchronous Clear(Up/Down Counter Mode) 29 105.26
Logic Used(LEs)
fMAX
(MHz)
EPF10K10-3
44
© 1998 Altera Corporation ®
Carry Chain Construction
Starts in First LE (LE1) of Every LAB
– Function’s Carry Chain Can Begin in Any LE of a LAB
Runs Downward through LEs of a LAB
At End of LAB, Continues to Top of Second-Next LAB in Same Row
Stops at EAB
Stops at End of Row
EAB
45
© 1998 Altera Corporation ®
Using Carry Chains in Your Design
Number of Chains– No More Than 20% of FLEX Device Should Use Carry and/or
Cascade Chains Length of Each Chain
– Maximum Length Should Be 32 LEs for Performance– For Ripple-Carry Longer than 32 LEs, Consider Carry Look-
Ahead or Carry-Select Implementations to Improve Performance– Carry Chains Longer Than 32 LEs May Still Provide Utilization
Advantages Further Reading
– AN 36: Designing with FLEX 8000 Devices– MAX+plus II Online Help: Search on “Carry”
46
© 1998 Altera Corporation ®
Cascade Chain
Look-UpTable(LUT)
CarryChain
CascadeChain
Carry-In Cascade-In
DATA1
DATA2
DATA3
DATA4
LAB Clear/Preset 1
LAB Clear/Preset 2
ClockSelect
LAB Clock 1
LAB Clock 2
Carry-Out Cascade-Out
Clear/PresetLogic
PRN
CLRN
To Row,Column
InterconnectsD Q
Chip-Wide Reset
ENA
To LABLocal
Interconnect
47
© 1998 Altera Corporation ®
Cascade Chain
LUT
LE
in[3..0]
LUT
LE2
in[7..4]
LUT
LEn
in[4n-1 .. 4(n-1)]
Cascades LUT Outputs, Implementing High-Performance, Wide Fan-in Functions
Result of Inputsin[0] to 4[n-1]
48
© 1998 Altera Corporation ®
in0
in2in1
in3in4in5in6in7
result
8-Input AND Gate
Cascade Chain Example
Without Cascade Chains: 3 LEs
LE
LUTin[2..0]
LE
LUTin[5..3]
LE
LUT
in[7..6]
result
Using Cascade Chains: 2 LEs
result
LUT
LE
in[3..0]
LUT
LE2
in[7..4]
49
© 1998 Altera Corporation ®
Cascade Chain Construction
Starts in First LE (LE1) of Every LAB
– Function’s Cascade Chain Can Begin in Any LE of a LAB
Runs Downward through LEs of a LAB
At End of LAB, Continues to Top of Second-Next LAB in Same Row
Stops at EAB
Stops at End of Row
EAB
50
© 1998 Altera Corporation ®
Cascade Chain
Cascade Chains Can Improve Density, Performance LEs Placed Contiguously, Challenging Fitting of Logic Recommendations
– No More Than 20% of the FLEX Device Should Use Carry and/or Cascade Chains
– Maximum Length Should Be 2 Cascades for Performance– Cascade Chains Longer Than 2 Cascades May Still Provide
Utilization Advantages Further Reading3:
– MAX+plus II Online Help: Search on “Cascade”
51
© 1998 Altera Corporation ®
Architecture Features
Carry Chain (LE Modes) & Cascade Chain Are Controlled in MAX+plus II– Logic Options– Synthesis Styles
52
© 1998 Altera Corporation ®
Synthesis Styles Can Be Assigned
Globally, to the Project/Design Individually, to a Subdesign
Synthesis Styles & FLEX Features
Styles Synthesize for:– Normal - Fit
– Fast - Performance
– WYSIWYG - Minimal Synthesis
– User-Defined Styles
Default Style Is Normal
53
© 1998 Altera Corporation ®
WSIWYG Will Use Only Carry & Cascade Primitives Manually Entered in Design
FAST Will Use Carry & Cascade Primitives Manually Entered in Design & Automatically Synthesize More Where Appropriate
NORMAL Will Ignore Any Carry or Cascade Chains
Synthesis Styles & FLEX Features
NORMAL
FAST
WYSIWYG
54
© 1998 Altera Corporation ®
Individual Logic Options for Carry & Cascade Chains Can Be Assignedin Subdesigns without Altering the Synthesis Style
Accessing Carry & Cascade Chains
55
© 1998 Altera Corporation ®
Default Lengths (in LEs) for Chains
Carry: 32
Cascade: 2
Default Lengths Can Be Edited in Both
Synthesis Styles & Individual Logic Options
Accessing Carry & Cascade Chains
56
© 1998 Altera Corporation ®
Carry and Cascades in Design
How Carry and Cascade Primitives Manually Entered– Primitives Entered in a Schematic or Instantiated in HDL– Altera Module Libraries for Third-Party Tools
• Written into EDIF Netlist
– Altera’s LPM Library Elements
57
© 1998 Altera Corporation ®
Carry and Cascades in Design
Altera’s LPM Library Elements– Library of Parameterized Modules
• Modules you can customize for your design– Edit
• Ports
• Parameters– Optimized for All Altera Architectures– Utilize the Architectural Features of All Altera Devices
58
© 1998 Altera Corporation ®
MegaWizard & LPMs
Altera’s LPM Library Elements Accessed and Edited through MAX+plus II’s MegaWizard Manager
59
© 1998 Altera Corporation ®
MegaWizard Manager Output
Selection of Output Files:– AHDL File– VHDL Component to Instantiate– Verilog Component to Instantiate
Automatically Generated– Symbol for Schematic– Include File
60
© 1998 Altera Corporation ®
Exercise 1: Goals
Learn How To– Utilize Carry Chains
Compare– Logic Utilization
• Without Carry Chains
• With Carry Chains
– Performance of Design• Without Carry Chains
• With Carry Chains
61
© 1998 Altera Corporation ®
Exercise 1: Review
How Did We Access Carry Chains?– Fast Synthesis Style
How Did We Know the Carry Resource Was Used?– Floorplan Editor
– Report File
The Resource Usage section of the Report File reveals how many LEs are used in carry and cascade chains so that the percentage of the device using carry and cascade chains can be calculated.
62
© 1998 Altera Corporation ®
FLEX Internal Tri-State Emulation
Altera Devices Do Not Contain Tri-State Buffers Internally– IOEs Contain Tri-State Buffers for Output Enables
Benefits:– Eliminates Possible Bus Contention– Location in Device a Non-Issue– Cost Savings to Customer
• Don’t Pay for Unused Tri-State Buffers• Less Testing Required of Devices
63
© 1998 Altera Corporation ®
FLEX Internal Tri-State Emulation
Tri-State Buffers Implemented as Multiplexers in LUTs– MAX+plus II Converts Automatically
– Larger Muxing Operations (Greater Than 8:1) May Be More Efficient Implemented as Multiplexers in Original Design
DATA
LE
B1A1
SEL LUT
© 1998 Altera Corporation
64
®
FastTrack Interconnect™
65
© 1998 Altera Corporation ®
FastTrack Interconnect™
Continuous Lines of Metal Predictable Timing & Performance Three Levels of Routing
– LAB Local Interconnect Connects LEs within an LAB– Row Interconnect Connects LABs within a Row– Column Interconnect Connects Rows
66
© 1998 Altera Corporation ®
FastTrack Interconnect
LAB LocalInterconnect
ColumnFastTrackInterconnect
RowFastTrackInterconnect
67
© 1998 Altera Corporation ®
As Device Density Grows, Number of Row & Column Interconnects Grows
Number of Channels per Row & Column Interconnect Grows
Interconnect Resources
Rows 3 6 6 8 10 9 12 16 24 20
Channels 144 144 216 216 216 312 312 312 312 456per Row
Columns 24 24 36 36 36 52 52 52 52 76
Channels 24 24 24 24 24 24 24 32 32 40per Column
EP
F10K
10/A
EP
F10K
20
EP
F10K
30/A
/E
EP
F10K
40
EP
F10K
50/V
/A/E
EP
F10K
70
EP
F10K
100/
B/A
/E
EP
F10K
130/
V/A
/E
EP
F10K
250A
/E
EP
F10K
200E
68
© 1998 Altera Corporation ®
As Inputs, Each IOE Can Drive up to Two Channelsin Its Row or Column
Inputs to FastTrack Interconnect
Column Interconnect
IOE1 IOE2
22
IOE1
IOE82
2
Row Interconnect
69
© 1998 Altera Corporation ®
Row
Partially-Populated Multiplexers *
Every Row Channel Is Not Connected to Every Multiplexer. Each Row Channel Is Connected to 2 Multiplexers. This Provides 2 Paths into Any LAB.
LAB LocalInterconnect
* Number of Multiplexers Is Device-Dependent
EPF10K10/A - EPF10K50/V/A/E 22
EPF10K70 - EPF10K250A/E 26
Row Interconnect into LAB
70
© 1998 Altera Corporation ®
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LABLocal
Interconnect
Row
8
LAB Local Interconnect - LE to LE
LAB Local Interconnect– Signals Entering from Row Interconnect– Feedback from LEs in LAB
Any Signal in the LAB Local Interconnect Can Drive into Any LE in Its LAB
Number of LAB Local Interconnect Signals Is Device-Dependent– EPF10K10/A - EPF10K50/V/A/E: 30– EPF10K70 - EPF10K250A/E: 34
71
© 1998 Altera Corporation ®
* LE Driver Swapping
Every LE Can Drive
– Up to 2 Row Channels
– Up to 2 Column Channels
– LAB Local Interconnect
– All Simultaneously
LE Output, Column-Row
72
© 1998 Altera Corporation ®
LE Driver Swapping
Transparent to User, Increases Routability of Device
73
© 1998 Altera Corporation ®
Row Structure
1/3 of Row Interconnect Channels in FLEX 10K Family Devices Are Half-Length Channels– Allows LEs in Same Half of Device to Communicate without
Consuming Entire Channel– LEs & Column Channels Can Drive Either Half- or Full-Length Lines
74
© 1998 Altera Corporation ®
Each Row Output Is Driven by m:1 Multiplexer
Row Interconnect to Output
Device n
EPF10K10/A - EPF10K20EPF10K30/A/E - EPF10K50/V/A/EEPF10K70 - EPF10K130/V/A/EEPF10K250A/E
144216312456
m
18273957
Row Interconnect, n channels
IOE1m
IOE2m
IOE3m
IOE4m
IOE5m
IOE7m
IOE6m
IOE8m
75
© 1998 Altera Corporation ®
Each Column Output Is Driven by m:1 Multiplexer
Column Interconnect to Output
m
IOE2
m
IOE1
Column Interconnect,n Channels
Device n
EPF10K10/A - EPF10K100/A/B/EEPF10K130/V/AEPF10K200EEPF10K250A/E
m
24324840
16244032
© 1998 Altera Corporation
76
®
Input/Output Element (IOE)
77
© 1998 Altera Corporation ®
Location of IOEs
EmbeddedArrayBlock(EAB)
EmbeddedArrayBlock(EAB)
Peripheral Control Bus
78
© 1998 Altera Corporation ®
I/O Element
79
© 1998 Altera Corporation ®
IOE Data Paths
Pins Can Be Inputs, Outputs, or Bi-directional I/O Register Can Be Bypassed In Case of Bi-directional I/O, Register Cannot Be Used for
Both Incoming & Outgoing Signals
80
© 1998 Altera Corporation ®
Output Enables
Available Output Enables 8 from Peripheral Control Bus 1 Unique Output Enable per Pin
– Driven from Row or Column Interconnect Chip-Wide Output Enable
81
© 1998 Altera Corporation ®
IOE Register Controls
Clocks– 2 from Dedicated Clocks– 2 from Peripheral Control Bus
Enables– 6 from Peripheral Control Bus– 1 Unique Enable per IOE
Driven from Row or Column Interconnect
Clears– 2 from Peripheral Control Bus – Chip-Wide Clear
Preset Emulation Not Supported in IOE Registers
82
© 1998 Altera Corporation ®
Peripheral Control Bus
12-Bit Bus Sources
– All Nets Can Be Driven by Internal Logic– All Nets Can Be Driven by Any Row or Column Input– 4 Nets Can Also Be Driven by Any of the 4 Dedicated Inputs
Can Possibly Drive– 2 Clocks for the IOE Registers– 2 Clears for the IOE Registers– 6 Enables for the IOE Registers– 8 Output Enables
2 + 2 + 6 + 8 = 18 > 12– Six Nets of Peripheral Control Bus Have Dual, Exclusive
Functions
83
© 1998 Altera Corporation ®
net 0IOE Register Clock
IOE Register Enable
net 1IOE Register Enable
Output Enable
net 2IOE Register Enable
Output Enable
net 3IOE Register Clock
IOE Register Enable
net 4IOE Register Clock
IOE Register Clear
net 5IOE Register Enable
IOE Register Clear
nets 6 - 11 Output Enables6
Can Be Driven byDedicated Input
Can Be Driven byDedicated Input
Can Be Driven byDedicated Input
Can Be Driven byDedicated Input
Six Nets of the Peripheral Control Bus Have Dual Functions
They Can Only Serve One of These Functions at a Time
All Nets Can Be Driven by Internal Logic or an I/O Pin
Four of the Dual-Purpose Nets Can Also Be Driven by Any of the Four Dedicated Inputs
Peripheral Control Bus
84
© 1998 Altera Corporation ®
Peripheral Control Bus
When a Global Control Net is Internally Driven, a Peripheral Control Signal is Traded
IOE Register Clock
IOE Register Enable
Can Be Driven by
Dedicated Input net 3
Global Control Net 3
Output Enable
Can Be Driven by
Dedicated Input net 2
Global Control Net 2
Output Enable
Can Be Driven by
Dedicated Input net 1
Global Control Net 1
IOE Register Enable
Can Be Driven by
Dedicated Input net 0
Global Control Net 0
IOE Register Enable
IOE Register Enable
IOE Register Clock
85
© 1998 Altera Corporation ®
Peripheral Control Bus
The Peripheral Control Bus Is Typically Transparent to the User
– MAX+plus II Automatically Places Signals on The Bus
The Peripheral Control Bus Needs Examining Only if a Fitting Issue Arises– If a Fitting Issue of Too Many Output Control Signals Arises,
Examine the Number of Possible Signals and Functions of the Peripheral Control Bus
86
© 1998 Altera Corporation ®
FLEX 10K/V/A/B/E “Per Pin” IOE Controls
Available per Pin Slew-Rate Control Open-Drain Emulation
In System Appendix Contains Device Timing Information, Instructions for Using MAX+plus II to Set Slew Rate on a Pin & Implementing Open-Drain Pins
87
© 1998 Altera Corporation ®
In System Appendix Contains Instructions for Using MAX+PLUS II to Set Individual Logic Option PCI_I/O
FLEX 10KA/B/E “Per Pin” IOE Controls
Additionally Available per Pin forFLEX 10KA/B/E Devices
Individual Logic Option PCI_I/O
– Clamps Voltage of Pin to VCCIO to Prevent Ringing on Bus
– Pins to which PCI_I/O Have Been Assigned Cannot Tolerate Voltages above VCCIO
Although Not Available on 10K/V Devices, Perhaps Not Necessary– Other Devices on Bus May Clamp
Voltage
© 1998 Altera Corporation
88
®
Implementing Memory&
Embedded Array Block (EAB)
89
© 1998 Altera Corporation ®
EAB and Memory Implementation
Memory Can Be Implemented in EAB– Synchronous and Asynchronous RAM– Synchronous and Asynchronous ROM– FIFOs (control logic implemented in LEs)
Memory Can Be Implemented Entirely in LEs– Synchronous and Asynchronous RAM– Synchronous and Asynchronous ROM– FIFOs
EAB Can Implement Logic– EAB becomes a large LUT (ROM)
90
© 1998 Altera Corporation ®
EAB
EAB
EAB
A Large Block of Embedded RAM– 10K/V/A/B - 2048 Bits, Single-Port RAM– 10KE - 4096 Bits, Dual-Port RAM
91
© 1998 Altera Corporation ®
One EAB per Row in all FLEX 10K Family Devices
Available RAM in FLEX 10K Family Devices
EPF10K10/A 3 6,144
EPF10K20 6 12,288
EPF10K30/A/E 6 12,288 24,576
EPF10K40A 8 16,384
EPF10K50/V/A/E 10 20,480 40,960
EPF10K70 9 18,432
EPF10K100/A/B/E 12 24,576 49,152
EPF10K130/V/E 16 32,768 65,536
EPF10K200E 24 98,304
EPF10K250A/E 20 40,960 81,920
Device Rows 10K/V/A/B 10KE
RAM Bits
92
© 1998 Altera Corporation ®
EAB
FLEX 10K/V/A/BEAB
2,048 Bits RAM
256 x 8
512 x 4
1,024 x 2
2,048 x 1
FLEX 10EEAB
4,096 Bits RAM
256 x 16
512 x 8
1,024 x 4
2,048 x 2
EAB Can Be Configured Four Ways:
93
© 1998 Altera Corporation ®
Cascading EABs for Memory
EABs Cascaded to Create Wider RAM EABs Cascaded, Multiplexed to Create Deeper RAM No Speed Penalty up to
– 10K/V/A/B - 2,048 Bits Deep– 10KE - 2,048 Bits Deep
MAX+plus II Configures RAM in Fastest Way Possible
256 x 16
256 x 16
256 x 32
94
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB - Single Port
Global Control Nets, Dedicated Clocks
EABControlSignals
EABLocal
Interconnect
ColumnInterconnect
Row Interconnect
EAB2,048 Bits RAM
Data In
Address
Write Enable
In Clock
Out Clock
Data Out
Width of Buses
Data In/Out Address
1 112 104 98 8
95
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB
Out Clock
In Clock
WriteEnable
WritePulseCircuit
RAM/ROM2,048 Bits
256 x 8
512 x 4
1,024 x 2
2,048 x 1D
11, 10, 9, 8Address
1, 2, 4, 8Data In
D
D 1, 2, 4, 8
Data OutD
EAB contains registers for incoming and outgoing signals
96
© 1998 Altera Corporation ®
FLEX 10KE EAB - Dual PortGlobal Control Nets, Dedicated Clocks
EABLocal
Interconnect
ColumnInterconnect
Row Interconnect
EAB4,096 Bits RAM
Write Address
Read Enable
Clock 1
Clock 2
Data Out
Write Enable
Read Address
Clock 1 Enable
Clock 2 Enable
Width of Buses
Data Addresses In/Out Write/Read
2 114 108 9
16 8
EAB Control Signals
Data In
Asynchronous Clearfor EAB Registers
97
© 1998 Altera Corporation ®
RAM/ROM4,096 Bits
Clock 2Clock 2 Enable
256x16512x8
1024x42048x2
Data OutDENAData In D
ENA
Write PulseCircuit
Write Enable DENA
Read Enable DENA
Write Address DENA
Read Address DENA
Clock 1Clock 1 Enable
10KE EAB
EAB contains registers for incoming and outgoing signals
98
© 1998 Altera Corporation ®
MAX+plus II’s MegaWizard
Memory Elements are Created with MAX+plus II’s MegaWizard Manager
– Dual-Port RAM– FIFO– LPM_FF– LPM_LATCH– LPM_RAM_DQ– LPM_RAM_IO– LPM_ROM– LPM_SHIFTREG
99
© 1998 Altera Corporation ®
Memory Elements and Implementation
Elements Implemented in LEs: – LPM_FF - An Array of D Flip-Flops (DFFEs in LEs)– LPM_LATCH - An Array of Latches (LUTs in LEs)– LPM_SHIFTREG - Shift Register
Elements Implemented in LEs and/or EABs:– Dual-Port RAM– FIFO– LPM_RAM_DQ (Separate Read & Write Data Ports)
• Recommended over LPM_RAM_IO
– LPM_RAM_IO (Single, Bi-directional Data Port)– LPM_ROM
100
© 1998 Altera Corporation ®
Memory Elements and Implementation
LPM_ ROM– Synchronous or Asynchronous ROM– Can Register Data out of ROM– Initialize ROM Contents
• Initializes to All “0”s if No Initialization File Specified
101
© 1998 Altera Corporation ®
Memory Elements and Implementation
LPM_ RAM_DQ– Synchronous or Asynchronous Single-Port RAM– Can Register Data out of RAM– Initialize RAM Contents
• Initializes to All “0”s if No Initialization File Specified
102
© 1998 Altera Corporation ®
Memory Elements and Implementation
LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM– Automatically Implemented in EABs for All FLEX 10K
Family Devices• Cannot Target LE-Only Implementation with
LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM through the MegaWizard
• Can Force LE-Only Implementation of LPM_RAM_DQ, LPM_ROM_DQ
– Consult Altera Applications Regarding Methodology
– Cannot Initialize RAM Implemented in LEs to Non-0 Values
– Built of Registers which are Cleared upon Power-up
• Consider LE-Only Implementation When Implementing Shallow & Wide Memory in 10K/V/A/B Devices
103
© 1998 Altera Corporation ®
FLEX 10K/V/A/B - Shallow & Wide RAM
LE-Only Implementation of LPM_RAM_DQ– 8x32 Synchronous RAM
ena ena ena ena ena
weadr[2..0]
clk
din[31..0]
dout[31..0]
Decoderen
D D D D D
104
© 1998 Altera Corporation ®
Memory Elements and Implementation
Dual-Port RAM– Four Clocking Schemes
• Single Clock
• Separate Read and Write Clocks
• One Clock for Reading and Writing with a Second Clock for Registering Data Outputs
• No Clock (Asynchronous Dual-Port RAM)
105
© 1998 Altera Corporation ®
Memory Elements and Implementation
Dual-Port RAM– Based on Clocking Scheme, Can Selectively Register
Various Input and Output Signals
106
© 1998 Altera Corporation ®
Memory Elements and Implementation
Dual-Port RAM– FLEX 10K/V/A/B
• An Array of DFFEs For Synchronous RAM• An Array of Latches For Asynchronous RAM
– FLEX 10KE• By Default, Implemented in EABs• Can Select an LE-Only Implementation
– May hold a performance advantage for very small RAMs(i. e. 4x4)
107
© 1998 Altera Corporation ®
Memory Elements and Implementation
FIFO– Two Clocking Schemes
• Single Clock for Reading and Writing
• Separate Read and Write Clocks
108
© 1998 Altera Corporation ®
Memory Elements and Implementation
FIFO– Single Clock for Reading and Writing
• One Set of Full/Empty Signals
– Separate Read and Write Clocks• Set of Full/Empty Flags for Each Clock
109
© 1998 Altera Corporation ®
Memory Elements and Implementation
FIFO– Can Select Whether rdreq Acts as a
• Read Request
• Read Acknowledge
110
© 1998 Altera Corporation ®
Memory Elements and Implementation
FIFO– Optimize for
• Area
• Speed
• Allow Optimization To Be Set in Design Options
111
© 1998 Altera Corporation ®
Memory Elements and Implementation
FIFO– Single Clock for Reading and Writing
• Any FLEX 10K Family Device– EAB Utilized by Default– Can Select LE-Only Implementation
– Separate Read and Write Clocks• FLEX 10K/V/A/B
– Array of DFFEs
• FLEX 10KE– EAB Utilized by Default– Can Select LE-Only Implementation
112
© 1998 Altera Corporation ®
Memory Elements and Implementation
FIFO– Consider LE-Only Implementation When Implementing
Very Small FIFOs (i. e. 4x4)• May Yield a Performance Advantage over EAB-
Implementation
113
© 1998 Altera Corporation ®
Memory Elements- GENMEM Utility
An Altera-Provided Utility that Generates for All Memory Elements– Functional Simulation Model (VHDL, Verilog HDL)
Pre-Synthesis & Post-Synthesis, Pre-Place-&-Route Simulation (-.vhd, -.v)
– Library Timing ModelTiming-Driven Synthesis & Timing Estimation (-.lib)
– Component DeclarationFor Synthesis & Simulation (-.cmp)
GENMEM Necessary for– Pre-Place-&-Route Timing Simulation with Third-Party Simulators
– EDA Tools that Do Not Support LPM Functions (Instantiate & Black-Box the Memory)
Where Is GENMEM?– Installed with MAX+plus II in the Same Directory As MAX+plus II
114
© 1998 Altera Corporation ®
GENMEM
At DOS or UNIX prompt, type
genmem memory_type memory_size - format
ASYNRAM Asynchronous RAMASYNROM Asynchronous ROMSYNRAM Synchronous RAMSYNROM Synchronous ROMCSFIFO Cycle-Shared FIFOCSDPRAM Cycle-Shared Dual-Port RAMSCFIFO Single Clock FIFOSYNDPRAM Synchronous Dual-Port RAMASYNDPRAM Asynchronous Dual-Port RAMDCFIFO Dual Clock FIFO
depth x widthoutput format of simulation model– vhdl– verilog
Menu follows regarding registering of signals
On Altera’s web page,search on GENMEM for more information
115
© 1998 Altera Corporation ®
Implementation Within the EAB
Selections in the MegaWizard Manager and GENMEM Control within the EAB– Implementation of Memory– Registering of Signals
116
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB
FLEX 10K/V/A/B EAB– Synchronous and Asynchronous ROM– Synchronous and Asynchronous RAM
117
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EABGlobal Control Nets, Dedicated Clocks
EABControlSignals
EABLocal
Interconnect
ColumnInterconnect
Row Interconnect
EAB2,048 Bits RAM
Data In
Address
Write Enable
In Clock
Out Clock
Data Out
Width of Buses
Data In/Out Address
1 112 104 98 8
118
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB - ROM
Out Clock
In Clock
RAM/ROM2,048 Bits
256 x 8
512 x 4
1,024 x 2
2,048 x 1
11, 10, 9, 8Address D
1, 2, 4, 8
Data OutD
For Synchronous ROM, Address Registered
For Asynchronous ROM, Address Not Registered
Can Register Data Out (optional)
119
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB - Asynchronous RAM
Out Clock
WriteEnable
RAM/ROM2,048 Bits
256 x 8
512 x 4
1,024 x 2
2,048 x 1
11, 10, 9, 8Address
1, 2, 4, 8Data In 1, 2, 4, 8
Data OutD
Can Register Data Out (optional)
120
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB - Synchronous RAM
Out Clock
In Clock
WriteEnable
WritePulseCircuit
RAM/ROM2,048 Bits
256 x 8
512 x 4
1,024 x 2
2,048 x 1D
11, 10, 9, 8Address
1, 2, 4, 8Data In
D
D 1, 2, 4, 8
Data OutD
Data In, Address, WE Registered
Writing Synchronized to In Clock
Can Register Data Out with Out Clock (optional)
121
© 1998 Altera Corporation ®
FLEX 10K/V/A/B EAB Details– EAB Registers Cleared by Chip-Wide Clear Only– All Or No of Data In Must Be Registered– All Or No of Data Out Must Be Registered
FLEX 10K/V/A/B EAB Details
122
© 1998 Altera Corporation ®
FLEX 10KE EAB - Dual Port RAM
FLEX 10KE EAB - Dual-Port RAM– Independent Read and Write Data Ports– Independent Read and Write Addresses– Can Use a Single Clock for Reading and Writing– Can Use Two Independent Clocks
• Independent Read and Write Clocks
• Same Clock for Reading and Writing– Second Clock for Registering Data Outputs of EAB
123
© 1998 Altera Corporation ®
FLEX 10KE EABGlobal Control Nets, Dedicated Clocks
EABLocal
Interconnect
ColumnInterconnect
Row Interconnect
EAB4,096 Bits RAM
Write Address
Read Enable
Clock 1
Clock 2
Data Out
Write Enable
Read Address
Clock 1 Enable
Clock 2 Enable
Width of Buses
Data Addresses In/Out Write/Read
2 114 108 9
16 8
EAB Control Signals
Data In
Asynchronous Clearfor EAB Registers
124
© 1998 Altera Corporation ®
FLEX 10KE EAB - ROM
RAM/ROM4,096 Bits
Out Clock
Out Clock Enable
256x16512x8
1024x42048x2
Data OutDENA
Enable DENA
Address DENA
In Clock
In Clock Enable
For Synchronous ROM, Address Registered
For Asynchronous ROM, Address Not Registered
Can Register Enable (optional)
Can Register Data Out (optional)
125
© 1998 Altera Corporation ®
FLEX 10KE EAB - Asynchronous, Single-Port RAM
RAM/ROM4,096 Bits
Out ClockOut Clock Enable
256x16512x8
1024x42048x2
Data OutDENAData In
Write Enable
Address
Can Register Data Out (optional)
126
© 1998 Altera Corporation ®
FLEX 10KE EAB - Synchronous, Single-Port RAM
RAM/ROM4,096 Bits
Out ClockOut Clock Enable
256x16512x8
1024x42048x2
Data OutDENAData In D
ENA
Write PulseCircuit
Write Enable DENA
Address DENA
In ClockIn Clock Enable
Data In, Address, WE Registered
Writing synchronized to In Clock
Can Register Data Out with Out Clock (optional)
127
© 1998 Altera Corporation ®
FLEX 10KE EAB - Asynchronous, Dual-Port RAM
RAM/ROM4,096 Bits
256x16512x8
1024x42048x2
Data OutData In
Write Enable
Read Enable
Write Address
Read Address
128
© 1998 Altera Corporation ®
FLEX 10KE EAB - Single Clock
RAM/ROM4,096 Bits
ClockClock Enable
256x16512x8
1024x42048x2
Data OutDENAData In D
ENA
Write PulseCircuit
Write Enable DENA
Read Enable DENA
Write Address DENA
Read Address DENA
Used for Synchronous Dual-
Port RAM with Single Clock for Reading and Writing
– Registering various ports optional through MegaWizard
Single Clock FIFOs– Registers
utilized by Altera’s FIFO elements
129
© 1998 Altera Corporation ®
FLEX 10KE EAB - Independent Input, Output Clocks
RAM/ROM4,096 Bits
Out ClockOut Clock Enable
256x16512x8
1024x42048x2
Data OutDENAData In D
ENA
Write PulseCircuit
Write Enable DENA
Read Enable DENA
Write Address DENA
Read Address DENA
In ClockIn Clock Enable
Synchronous Dual-Port RAM with Single Clock for Reading and Writing
Reading and Writing synchronized to In Clock
Data Out Registered with Out Clock
Registering various input ports optional through MegaWizard
130
© 1998 Altera Corporation ®
FLEX 10KE EAB - Independent Read, Write Clocks
RAM/ROM4,096 Bits
Read ClockRead Clock Enable
256x16512x8
1024x42048x2
Data OutDENAData In D
ENA
Write PulseCircuit
Write Enable DENA
Read Enable DENA
Write Address DENA
Read Address DENA
Write ClockWrite Clock Enable
Used for Synchronous
Dual-Port RAM Independent Read, Write Clocks
– Registering various ports optional through MegaWizard
Dual-Clock FIFOs– Registers
utilized by FIFO elements
131
© 1998 Altera Corporation ®
FLEX 10KE EAB Details
FLEX 10KE EAB Details– Can Register EAB Ports Individually
• All Or No Data Inputs Must Be Registered
• All Or No Data Outputs Must Be Registered
– Can Asynchronously Clear EAB Registers Individually• All Or No Data Inputs Must Be Cleared
• All Or No Data Outputs Must Be Cleared
D
ENA
CLR
Asynchronous Clearfor EAB Registers
Global Control NetsEAB Local Interconnect
132
© 1998 Altera Corporation ®
For All FLEX 10K Family Devices– For Synchronous RAMs, a Write Pulse Circuit is
Activated by Address and WE Being Registered• Must Register Both Address and WE
FLEX 10K/V/A/B/E EAB Details
Write PulseCircuit
Write Enable
Write Clock
Write Clock Enable
DENA
Write Address DENA
133
© 1998 Altera Corporation ®
Data In
Address
WE
setup hold
In Clock
Synchronous RAM - FLEX 10K/V/A/B/E
All Signals Edge-Triggered by In Clock All Signals Triggered by Same Edge of In Clock
– Positive-Edge Triggered– Negative-Edge Triggered
Can Change Address after It Is Clocked into RAM Can Write to Multiple Addresses without Toggling WE
134
© 1998 Altera Corporation ®
data in
address
we
datasetup
datahold
writeaddress
setup
writeaddress
holdAddress Cannot
Change Here
Asynchronous RAM - FLEX 10K/V/A/B/E
Setup, Hold Times with Respect to Both Edges of WE Cannot Change Address while WE Is Active
135
© 1998 Altera Corporation ®
For Synchronous RAM in all FLEX 10K Family Devices– If Design Does Not Read Data from the EAB As It Is
Written, Analyzing the Path out of the Write Enable Register May Cause Misleading, Slower Timing Results
– Invoke the Timing Analyzer OptionCut Off Read During Write Paths
Synchronous RAM Timing Analysis
Write Clock
Write PulseCircuit
Write Enable DENA
• Prevents Analysis of the Delay Path out of the Write Enable Register, through the EAB, to Any Destination Registers
• “Off” by Default
136
© 1998 Altera Corporation ®
See PIB 21: Implementing Logic with the Embedded Array in FLEX 10K Devices
Using EAB for Logic: Examples
Constant Multiplier 2-D Convolver Reconfigurable Logic Transcendental Functions / Waveform Generator 8- to 10-Bit Encoder
137
© 1998 Altera Corporation ®
Using EABs for Logic
EAB Becomes a Large LUT (ROM)
1 EAB Is Same Die Size (& Cost) as 20 Logic Elements
1 EAB Can Perform, in One Logic Level, Complex Functions Possibly Requiring More than 20 Logic Elements
Functions of X Inputs & Y Outputs Can Be Implemented in 1 EAB
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
EAB=X Inputs
89
1011
Y Outputs
8421
10K/V/A/B 10KE
16842
138
© 1998 Altera Corporation ®
Using EABs for Logic
EABs Can Be Cascaded & Combined with LEs for Larger Functions– 4x4 Multiplier
• 33 LEs Using “Fast” Style Synthesis• Can Be Implemented in 1 EAB• LE Implementation Slightly Faster
– 8x8 Multiplier• 135 LEs Using “Fast” Style Synthesis• Can Be Implemented in 4 EABs & 29 LEs Using “Fast”
Synthesis Style– Saving 107 LEs over LE-Only Implementation
• LE Implementation Slightly Faster
139
© 1998 Altera Corporation ®
Using EABs for Logic
Isolate the Logic– Subdesign, Component, LPM, Macrofunction– Assign the Individual Logic Option
All or No Inputs are Registered
All or No Outputs are Registered
No Feedback within Subdesign– Cannot Have Feedback
within ROM
140
© 1998 Altera Corporation ®
Using EABs for Logic
Selecting the Global Option Implement in EAB allows MAX+plus II to automatically place appropriate logic in EABs
– Assigning the Individual Logic OptionImplement in EAB to subdesigns is the preferred method
141
© 1998 Altera Corporation ®
Exercise 2: Goals
Learn How to– Build a RAM of Desired Width & Depth– Implement Synchronous RAM– Register RAM Data Inputs & Outputs in the EAB– Initialize RAM Contents
Explore– How the RAM Is Implemented in Device
142
© 1998 Altera Corporation ®
Note - Single Port Memory in FLEX 10KE
When Targeting FLEX 10KE Device Using – LPM_RAM_DQ– LPM_RAM_IO– LPM_ROM
Cannot Access• Clock Enable Port on EAB Registers
• Clear Port on EAB Registers
To Access These Controls, Must Use MegaWizard’s “Dual-Port RAM”
© 1998 Altera Corporation
143
®
Designing with FLEX 10K Family Devices
144
© 1998 Altera Corporation ®
Designing with FLEX 10K Family Devices
Discussion of Controlling Fitting, Utilization, and Performance– In Design– In Architecture / MAX+plus II
Analyzing Utilization and Performance in MAX+plus II
Strategy For Improving Utilization and Performance
145
© 1998 Altera Corporation ®
FLEX 10K Family Devices - Usable Gates
EPF10K10/A 6,912 30,912
EPF10K20 13,824 61,824
EPF10K30/A/E 20,736 68,736 119,000
EPF10K40A 27,648 91,648
EPF10K50/V/A/E 34,560 114,560 199,000
EPF10K70 44,928 116,928
EPF10K100/A/B/E 59,904 155,904 257,000
EPF10K130/V/E 79,872 207,872 342,000
EPF10K200E 119,808 311,808 513,000
EPF10K250A/E 145,920 305,920 474,000
FLEX 10K/V/A/B FLEX 10KE
Device From To To
Usable Gate Range
146
© 1998 Altera Corporation ®
FLEX 10K Family Devices - Usable Gates
Using LSI Logic’s LCA300K family equivalent Over 100 designs compiled
– Average 12 gates per LE
– EAB equivalent gate count
• As logic: average 150 gates per EAB• As memory: average 4 gates per memory bit
Low-end Gate Count– 100% LE + 100% EAB for logic
Typical Gate Count– 100% LE + 20% EAB as Memory + 80% EAB as Logic
High-end Gate Count– 100% LE + 100% EAB as Memory
147
© 1998 Altera Corporation ®
FLEX 10K Family Devices- Performance
Design Performance Considerations– Setup & Hold Times for Signals Coming On-Chip– Clock-to-Out for Signals Going Off-Chip– Maximum Clock Frequency, Internal Register-to-
Register Performance
LogicLogicD QLogicLogicD QLogicLogic
Clock-to-Output TimeSetup Time, Hold Time Clock Frequency
148
© 1998 Altera Corporation ®
In Design
Design Hierarchically– Simulate Subdesigns– Fine-Tune Subdesigns for Performance, Logic Usage– Assignments Made Easily & Clearly in MAX+plus II– Subdesigns Should Be 80 - 130 LEs– Terminate Subdesigns at Register Outputs
• Best Opportunities For Optimization between Registers
149
© 1998 Altera Corporation ®
In Design
Subdesign u1 Is Terminated at Combinatorial Outputs
Assign Fast Synthesis Style to u1 Remainder of design on Normal
Synthesis Style
+
u1 u2
acc
in
clear clock
out
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© 1998 Altera Corporation ®
In Design
Compiler Will Follow User Assignment and Boundary Settings– Will Not Optimize Adder and Synchronous Clear into One LUT– Arithmetic Mode Used Rather Than Counter Mode
• Feedback Implemented within Row, Column, LAB Local Interconnect
– acc Uses 21 LEs
D Q
CLRN
PRN
LUT
carry
LUT
carry
inLUT
clear
D Q
CLRN
PRNout
clockclock
LE1 LE2
151
© 1998 Altera Corporation ®
In Design
Subdesign in One Module, Terminated at Register Outputs Fast Synthesis Style Assignment Will Apply to All of acc
+
acc
clear(synchronous)
in
clock
out
152
© 1998 Altera Corporation ®
In Design
Compiler Will Follow User Assignment and Boundary Settings– Up/Down Counter Mode Is Used
• Adder and Synchronous Clear Optimized into One LUT
• Feedback within Logic Element
– acc Uses 9 LEs
D Q
CLRN
PRN
LUT
carry
LUT
carry
in
clear
out
in
clear
Cascade Chain
clock
LE
153
© 1998 Altera Corporation ®
In Design
Explore– LPM Functions– Drop-In and Reference Designs
• AMPPSM
• MegaCore™ Functions• On-Line Help, Literature, Catalogs, Web Page
– Functionally Correct and Efficient in Altera Architecture
154
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In Design
Use D Flip-Flops Rather than Latches– Latches Are Implemented in LUTs, Impairing Utilization
Use “Free” Control Signals/Ports of Registers– “Free” Asynchronous Clear, Preset– Synchronous Clear and Preset Will Use LUT Inputs
Balance Registers to Maximize Performance
Logic
Logic
Logic
Logic
Logic
Logic
10 ns 5 ns5 ns
66 MHz
Logic
Logic
Logic
Logic
Logic
Logic
10 ns 10 ns
100 MHz
155
© 1998 Altera Corporation ®
In Design
“Free” Control Signals of Counter Modes– Up/Down Counter Mode - Up/Down, Counter Enable,
Synchronous Load– Clearable Counter Mode - Counter Clear, Counter Enable,
Synchronous Load– Extra Control Logic = Extra LUTs Used Overall and Along
Paths
One-Hot State Machine Encoding is Usually Most Efficient– Register-Rich Architecture– Results Depend on Quality of One-Hot Optimization within
HDL Synthesis Tool
156
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In Design
HDL Issues– Cover All Possibilities in if-else and case structures
• Uncovered Possibilities Infer Latches– Will a case, if, or if-else Structure Synthesize Best for
Speed and/or Utilization?• Depends on Design Logic and Synthesis Tool
157
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Global Nets Appendix Contains Important Device Details & Instructions for Using MAX+plus II to Assign Signals
to Global Nets
In Architecture / MAX+plus II
Global Control, Clock Nets Are Designed to Tolerate High Fan-out Signals– High Speed
– Low Skew
– Maximize Performance
Routing Resource in Addition to FastTrack Interconnect™
– Improve Routability and Hence Overall Utilization
158
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In Architecture / MAX+plus II
If Assigning a Device, Allow for Future Growth and Fitting– 10% of the Device LEs Unused– 10% of the Device Pins Unused
If You Must Assign Pins, for Optimal Routability and Performance:– Assign Bi-directional I/O to Row Pins– Assign Speed Critical, Low Fan-out Inputs to Row Pins– Assign High Fan-out Inputs to Column Pins– Assign Wide Buses to Row Pins
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Assign Bi-directional I/O to Row Pins
– More Channels in Row Interconnect than Column Interconnect
In Architecture / MAX+plus II
144 - 456
24 - 40
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Consider Cliquing Logic & Assigning Logic, Pins to Same Row of Device
In Architecture / MAX+plus II
Assign Speed-Critical, Low Fan-out Inputs to Row Pins– A Low Fan-out Input Drives into Only One Row
– Avoid Additional Column Delay (tCOL) to Driven Logic
LEtROW LE LEtROW LE
t CO
L
161
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In Architecture / MAX+plus II
Try First to Assign High Fan-out Inputs to Dedicated Inputs– A High Fan-out Input Drives to Multiple Rows
If Dedicated Inputs Impossible, Assign High Fan-out Inputs to Column Pins
– Avoid Added Row Delay (tROW)
LEtROW LE
LEtROW LE
LEtROW LE
LEtROW LE t CO
LLEtROW LE
LEtROW LE
t CO
L
162
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Consider Cliquing Logic & Assigning Logic, Pins to Same Row of Device
In Architecture / MAX+plus II
For Best Performance– Bus Processed in Rows with
High Speed
– Low Skew between Bus Bits
For Easy Fitting– More Pins per Row than per Column
– More Channels in Row Interconnect than in Column Interconnect
Assign Wide Buses to Row Pins
163
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In Architecture / MAX+plus II
MAX+plus II On-Line Help Reveals on What Rows or Columns Pins are Located
164
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Device Timing: Setup & Hold Times
Register Setup / Hold Time (See ) Clock Delay: Depends on Resource Used
– Dedicated Inputs/Clocks Drive Global Nets
– I/O Pins Drive Row & Column Interconnects
Data Delay Factors– Resource Used for Data Input
• Dedicated Inputs/Clocks Drive Global Nets
• I/O Pins Drive Row & Column Interconnects
– Proximity of Input Pin & Register
D QLogicLogic
Data Delay
Clock Delay
tSU = Data Delay - Clock Delay + Register Setup Time
tHOLD = Clock Delay - Data Delay + Register Hold Time
165
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In Architecture / MAX+plus II
All FLEX 10K Family Devices (tsu)
Fastest A Dedicated Input for data, registered in an LE, but a hold time may exist
Fast Data input on a row or column pin, registered in an LE; hold time is zero *
Least fast Data input registered in an IOE register; hold time is zero
Fast Data input registered in an IOE register; hold time is zero
Least fast Data input on a row or column pin, registered in an LE; hold time is zero *
* Refer to guidelines regarding pin placement for speed, fan-out of nets
– Using the IOE register for inputs excludes combinatorial logic between the input pin and register
– Data registered in an LE or driven-in on a Dedicated Input may go through one LUT with no penalty to set-up time
166
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Device Timing: Clock-to-Output
Register Clock-to-Q Time (See Data Book) Clock Delay Depends on Resource Used
– Dedicated Inputs/Clocks Drive Global Nets
– I/O Pins Drive Row & Column Interconnects
Data Delay Factors– Proximity of Output Pin & Register
tCO = Clock Delay + Register Clock-to-Q Time + Data Delay
D Q LogicLogic
Clock Delay
Data Delay
167
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In Architecture / MAX+plus II
IOE Register Always Provides Fastest Clock-to-Output
Using the IOE register for outputs excludes combinatorial logic between the register and output pin
168
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In Architecture / MAX+plus II
The Logic Option Fast_I/O Will Utilize IOE Registers
169
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Utilizing IOE Registers
Selecting the Global Option Automatic Fast I/O is Equivalent to Assigning the Individual Logic Option Fast I/O to All Input Pins
– Assigning the Individual Logic Option Fast I/O to Specific Registers and/or Input/Output Pins is the Preferred Method
170
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In Architecture / MAX+plus II
Utilizing the IOE Registers for Inputs Or Outputs May Reduce fMAX
Use IOE Registers Only When Necessary to Meet System Conditions
D QLogicLogicD Q
LE IOE
fMAX tCO
D QLogicLogicD Q
LE IOE
fMAX tCO
171
© 1998 Altera Corporation ®
Device Timing: Clock Frequency
Register Clock-to-Q Time (See Data Book) Register Setup Time (See Data Book) Clock Skew Depends on
Resource Used– Dedicated Inputs/Clocks
Drive Global Nets– I/O Pins Drive Row &
Column Interconnects
Data Delay Factors– Logic Delay between Registers– Proximity of Registers
fMAX =1
Register Clock-to-Q + Data Delay + Register Setup + Clock Skew
D QLogicLogicD Q
Data Delay
Clock Skew
172
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In Architecture / MAX+plus II
Carry Chains for Arithmetic Functions and Cascade Chains for Any Wide Fan-In Function Reduce– LEs Used Overall, Improving Utilization– LEs Used along Critical Paths, Improving Performance
“Fast” Synthesis Style Improves Performance by Utilizing– Carry Chains
– Cascade Chains
– Speed-Enhancing MAX+plus II Synthesis Options
No More Than 20% of the FLEX Device Should Use Carry and/or Cascade Chains for Ease-of-Fit (Routability)
173
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In Architecture / MAX+plus II
Cliquing Logic Shortens the Routing Delays Between LEs To Improve Performance– Logic Will Be Placed in Same LAB– If Placement in Same LAB Impossible, Same Row
– Over-Cliquing Challenges Fitting
• Don’t Clique Too Much Logic Together
• Don’t Create Too Many Cliques
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Timing Requirements Can Be AssignedIndividual Assignments are Recommended
Globally, to the Project/Design Individually, to a Subdesign
In Architecture / MAX+plus II
De-select Ignore Timing Assignments
– “On” by Default
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In Architecture / MAX+plus II
When Timing Requirements Are Entered, MAX+plus II Compiles To Meet the Entered Requirements– Influences Both Synthesis and Fitting (Placement)
Requirements That May Be Entered– fMAX: Minimum Internal Register-to-Register Frequency
– tSU: Maximum Set-up Time for Registered Inputs
– tCO: Maximum Clock-to-Output Time for Registered Outputs
– tPD: Maximum Input-to-Output Delay for Purely Combinatorial Paths
176
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In Architecture / MAX+plus II
tSU and tCO Timing Requirements Will Use Only LE Registers, Placing the LE Close to the Pin– Only the Logic Option Fast_I/O Will
Utilize IOE Registers
Entered fMAX Timing Requirement Should Be within 25% of Design’s Current Measured Frequency
Highly recommended information in MAX+plus II on-line help– Specifying Global Project Timing Requirements– Timing Requirements Command– Guidelines for Timing Assignments
177
© 1998 Altera Corporation ®
In Architecture / MAX+plus II
Don’t Over-Constrain Clock Signals– Multicycle Paths Supported for Timing-Driven Compilation
• Assign fMAX Globally or Individually For Slower Paths
• Assign fMAX Individually For Faster Paths– Assigned to a Register,
fMAX Applies to the Data Pathout of the Register to theNext Register
Logic
Logic
Logic
Logic
Logic
Logic
fMAX=50MHz fMAX=50MHz fMAX=50MHz
fMAX=50MHz fMAX=50MHz fMAX=Global fMAX
178
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In Architecture / MAX+plus II
Don’t Over-Constrain Clock Signals– Individual Paths Can Be Excluded from Timing-Driven Compilation– Assigned to a Register,
“Cut” Applies to theData Path out of thatRegister to the NextRegister
Logic
Logic
Logic
Logic
Logic
Logic
fMAX=50MHz fMAX=50MHz Excluded
Cut
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Don’t Over-Constrain Clock Signals– Are Paths with Inverted Clocks Being Considered?
• Assign “Cut” to “Upstream” Register of Opposite-Edge-Triggered Registers with a Data Path between Them
• Make Individual fMAX Timing Requirements As For Multicycle Paths; Relax Data Path out of “Upstream” Register
In Architecture / MAX+plus II
Clock Frequency without Inverted Edge
Clock Frequency with Inverted Edge
clock
Logic
Logic
180
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In Architecture / MAX+plus II
The Optimize Bar Guides Synthesis For– Smaller Area (0)– Balance of Fit & Performance (5)– Higher Performance (10)
Effectiveness Is Design-Dependent
– The Bar Should Be Set to 0, 5, or 10
181
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In Architecture / MAX+plus II
When the Optimize Bar Is Set to 10, Synthesis Is Performed To Reduce the Levels of Logic between Registers– LEs Used Overall May Increase
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
fMAX
182
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Analyzing and Improving Results
To Achieve Optimal Utilization and Performance1 Do Everything Presented in “In Design” Section2 If Assigning Pins, Follow Advice Presented in “In
Architecture / MAX+plus II” Section3 First Compile with No Or Minimal Assignments
• Are Utilization Goals Met? (Report File)
• Are Performance Goals Met? (Timing Analyzer)– fMAX - Internal Registered Performance
– tSU- On-Chip Paths
– tCO - Off-Chip Paths
183
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Analyzing and Improving Results
Analyzing Utilization– Look in Report File
– No Fit
184
© 1998 Altera Corporation ®
Analyzing and Improving Results
Too Many LEs? Try ...1 Carry and Cascade Chains2 Register Packing3 Setting the Optimize Bar to “0”4 Placing Some Logic into EABs
Consider Re-Compiling and Re-Analyzing Results after Each Suggestion
185
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Analyzing and Improving Results
Analyzing tSU - Set-up and Hold
– If tSU For An Input to A Register Is Too Long, “List Paths”
• Highlight the Data Path
• Check-Off “Locate in Floorplan Editor”
• Click on “Locate All”
186
© 1998 Altera Corporation ®
Analyzing and Improving Results
Analyzing tSU - Set-up and Hold
– Observe Path Between Input Pin and Register
187
© 1998 Altera Corporation ®
Analyzing and Improving Results
Analyzing tCO - Clock to Output
– If tCO For A Register to An Output Is Too Long, “List Paths”
• Highlight the Data Path
• Check-Off “Locate in Floorplan Editor”
• Click on “Locate All”
188
© 1998 Altera Corporation ®
Analyzing and Improving Results
Analyzing tCO - Clock to Output
– Observe Path between Register and Output Pin
189
© 1998 Altera Corporation ®
Analyzing and Improving Results
tSU Or tCO Goals Not Met? Try ...
1 FAST_I/O Assignment on Necessary Individual Pins2 tSU or tCO Timing Requirements Individually on Necessary
Pins• If FAST_I/O Will Decrease fMAX below Target fMAX
• If Combinatorial Logic between Pin and Register Prevents Use of IOE Register
• If Target Device is EPF10K10 - EPF10K50 or EPF10K50V, LE Register Provides Better Set-up Time than IOE Register
3 Placement Assignments for Pins and/or Registers
Consider Re-Compiling and Re-Analyzing Results after Each Suggestion
190
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Analyzing and Improving Results
Analyzing Internal fMAX (Registered Performance)
– Edit Desired fMAX in Registered Performance Options
191
© 1998 Altera Corporation ®
Analyzing and Improving Results
If fMAX < Desired, “List Paths”
All Paths “Missing” Desired fMAX Will Be Listed
192
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Analyzing and Improving Results
Verify Validity of Paths Being Measured– Are Slower Portions of Multicycle Paths Being Measured?
– Are Paths with Inverted Clocks Being Measured?
– Are “Don’t-Care” Paths Being Measured?
– Are Invalid Memory “Read During Write” Paths Being Measured?
– Paths Relaxed or Cut forTiming-Driven CompilationAre Still Measured byTiming Analyzer
• Can “Cutoff” Paths fromTiming Analysis
– Assigned to a Register,“Cutoff” Applies to theData Path out of that Register to the Next Register
193
© 1998 Altera Corporation ®
Analyzing and Improving Results
Globally or on Individual Design Modules, Try1 Carry & Cascade Chains, “Fast” Synthesis Style
2 fMAX Timing Requirement
• no more than 25% of current fMAX
3 Setting the Optimize Bar to “10”
Consider Re-Compiling and Re-Analyzing Results after Each Suggestion
194
© 1998 Altera Corporation ®
Analyzing and Improving Results
fMAX Goals Still Not Met?
– Work on Individual Paths May Be Necessary
– Note How Many Paths Are “Missing” Desired fMAX
195
© 1998 Altera Corporation ®
Analyzing and Improving Results
Number of “Missing” Paths, Source of Delay Determines Approach to Solution1 Only a Few Paths Missing
• Due To Routing Delay - Try Cliquing Those Paths, Relevant Logic
• Due To Logic Delay - Redesign, Pipeline– Balance Registers
2 Many Paths Missing• May Have to Redesign or Pipeline, but Observe How
Much of Path Delay is Due to
– Logic Delay
– Routing Delay
196
© 1998 Altera Corporation ®
Analyzing and Improving Results
Analyzing Individual PathsHighlight a Path
Check-Off “Locate in Floorplan Editor”
Note Number of “Levels of Logic” along the Path (Logic Delay)
Click on “Locate All”
197
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Analyzing and Improving Results
Floorplan Editor Opens Turn on “Show Paths between Selected Items”
– Observe Routing Path (Routing Delay)• Does Path Cross Many Rows Many Times?
• Are Routes between LEs along Path Long?
198
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Analyzing and Improving Results
Ideas for Re-design
DecodeValue
x-1
DecodeValue
x-1LogicLogic
20 ns 20 ns
DecodeValue
x
DecodeValue
x
Counter,State
Machine
LogicLogic
40 ns
Counter,State
Machine
199
© 1998 Altera Corporation ®
Exercise 3: Goals
Learn How to– Analyze Setup/Hold for Inputs– Analyze Clock-to-Out for Outputs– Analyze Internal Frequency (Registered Performance)
Explore– Effects of Pin Assignments on Input Setup/Hold– Effects of Utilizing IOE Registers on Clock-to-Output– Steps to Improve Internal Frequency
200
© 1998 Altera Corporation ®
Note - Timing Analyzer
Registered Performance (fMAX) Does Not Measure on-Chip or off-Chip Delays– Measure Internal Register-to-Register Performance
with Registered Performance– Measure on-Chip Delays with Setup/Hold Analysis– Measure off-Chip Delays with Delay Matrix
Longest Delay Determines Device fMAX
tSU/HOLD fMAX tCO
Logic
Logic
Logic
Logic
Logic
Logic
201
© 1998 Altera Corporation ®
Note - Timing Analyzer
In MAX+plus II’s Timing Analyzer– Post Place-and-Route
• Logic Delay along a Path Accurately Calculated
• Distance of Routes Considered
• Loading on a Signal Considered
– Worst-Case Voltage and Temperature Assumed
© 1998 Altera Corporation
202
®
Configuration
203
© 1998 Altera Corporation ®
FLEX Configuration Overview
FLEX Devices Are SRAM-Based– Must Be Reconfigured with Every Power-up
Can Configure the FLEX Device via EPROM, Intelligent Host
FLEX 10K Family Allows Configuration through Its JTAG Port
204
© 1998 Altera Corporation ®
Configuration Control and/or Data
EPROM– FLEX 10K Family Devices Must Use EPC1 or EPC1441
• EPC1, EPC1441 Provides Oscillator for Configuration Process
• EPF10K40 and Higher Density Devices Must Use EPC1
Intelligent Host– Microcontroller
– Microprocessor
Downloading Cable– BitBlaster™
• Uses Serial Port (“COM” Port) of PC or Workstation
– ByteBlaster™, ByteBlasterMV™
• Uses Parallel Port (“LPT” Port) of PC
205
© 1998 Altera Corporation ®
Configuration Modes
Altera EPC1, EPC1441 EPROM
Download Cable, Intelligent Host, Memory
Intelligent Host, Memory
Intelligent Host, Memory
Mode
Configuration EPROM
Passive Serial
Passive Parallel Synchronous
Passive Parallel Asynchronous
Hardware Possibilities for Configuration Control &/or Data
Passive– External Host Controls Configuration
(Download Cable, Microprocessor, Microcontroller)
Configuration EPROM– EPC1, EPC1441 & FLEX Device Control Configuration Together
206
© 1998 Altera Corporation ®
Choosing Appropriate Mode
Purpose
Prototyping & DevelopmentBitBlasterTM, ByteBlasterTM , ByteBlasterMVTM
System with Intelligent HostPossible to Store Configuration Data in Mass-Storage Medium to Reduce ICs on Board
Real-Time Reconfiguration NeededMultiple Sources of Configuration Data Supported
Field Upgrades AnticipatedNew Configuration Data Can Be Supplied on Disks, Tapes
EasiestNo External Intelligence Required
Consider Using This Mode
Passive Serial
Passive
Passive
Passive
Configuration EPROM
207
© 1998 Altera Corporation ®
Multiple FLEX 10K Family Devices
FLEX Device Chain– Devices within a FLEX Family Can Be Chained Together
– FLEX 10K Family & FLEX 6000 Devices Can Be Chained Together
Can Configure a Chain of FLEX 10K Family Devices through JTAG Ports
Configuration Files for Chained Devices Must Be Combined in MAX+plus II
Configuration Application Note 59 Contains Extensive, Detailed Information on FLEX 10K Family Device Chains
208
© 1998 Altera Corporation ®
Configuration Application Notes, Data Sheets
AN 59: Configuring FLEX 10K Devices
Data Sheets– BitBlasterTM Serial Download Cable– ByteBlasterTM Parallel Port Download Cable– ByteBlasterMVTM Parallel Port Download Cable– Configuration EPROMs for FLEX Devices– Altera Programming Hardware
209
© 1998 Altera Corporation ®
Configuration Application Notes
AN 59: Configuring FLEX 10K Devices– Configuration Circuit Diagrams for Each Mode
• Including Multiple Devices
– Timing Parameters for Configuration Control Signals
– Timing Waveforms for Each Mode
– Descriptions of MAX+plus II Device Options
– Descriptions of Configuration Pin Functions
– Descriptions of Configuration Files
– Steps of Configuring with PROMS & Cables• With Hardware & within MAX+plus II Software
– Configuration Reliability
210
© 1998 Altera Corporation ®
During Compilation, MAX+plus II Generates the Following File Types for Each Device in a Project
Configuration Data
SRAM Object File (.sof)– Can Be Loaded Directly Through BitBlaster, ByteBlasterTM, or
ByteBlasterMVTM Cables
Programming Object File (.pof)– Used by Altera Programming Hardware to Program EPC1, EPC1441
Tabular Text File (.ttf, ASCII)– Allows Configuration Data to be Included as Intelligent Host Source Code
– Data Can Be Accessed from EPROM or Mass-Storage Device
Hexadecimal (Intel-format) File (.hex)– Allows Third-Party Programmers to Program EPC1, EPC1441 EPROMs
211
© 1998 Altera Corporation ®
Configuration Data
MAX+plus II Can Convert SOFs to Other File Types for Various Configurations– Serial Bitstream File (.sbf)
• Used When Downloading from DOS or UNIX Prompt to BitBlaster™, ByteBlaster™, ByteBlasterMV™ Cables
• Can Be Used without MAX+plus II
– Raw Binary File (.rbf)• Allows Storage of Configuration Data in Mass Storage Device• Data Loaded into FLEX Device by Intelligent Host During Configuration
For FLEX Device Chain– Configuration Data Files of Chained FLEX Devices Can Be Combined &
Converted to Another File Type in One Step
212
© 1998 Altera Corporation ®
Configuration Data
JAM File (.jam)– Can Be Created from Other Programming Files (.sof, .pof, etc.)– For the Purpose of Configuring the FLEX Device through its JTAG Port
• BitBlaster™, ByteBlaster™, ByteBlasterMV™ Cables
• Intelligent Host
– For Devices in a JTAG Chain, Combine the Programming Files as the JAM File Is Created
213
© 1998 Altera Corporation ®
Configuration Reliability
Configuration Data Is Split into Frames Each Frame Has a CRC (Cyclic Redundancy Code)
Checksum If the Computed Checksum Does Not Equal the
Transmitted Checksum, Configuration Data Has Been Corrupted– FLEX Device Drives nSTATUS Low & Halts
Configuration
214
© 1998 Altera Corporation ®
Configuration Pins
Dedicated Configuration Pins– Device Pins Dedicated to Configuration
– Not Available as User I/O in User Mode During Device OperationnSTATUSCONF_DONE MSEL DCLK
nCONFIG nCE nCEO DATA0
Dual-Purpose Configuration Pins– Device Pins Used During Configuration
– Available as User I/O in User Mode During Device Operation
– Specific to Configuration ModeINIT_DONECLK_USR DATA[7..1] RDYnBUSY
nWS nRS nCS CS
Rdclk SDOUT Add[17..0]
215
© 1998 Altera Corporation ®
General Steps of Configuration
Configuration– Process of Loading Configuration Data into Device
Initialization– Performed after Configuration– FLEX Device
• Resets Its Registers• Enables the I/O Pins• Begins Operation
Command Mode– Configuration & Initialization Processes Together
User Mode– Normal In-Circuit Device Operation
216
© 1998 Altera Corporation ®
2 3 4, 5 6
General Steps of Configuration
nCONFIG Is Driven Low to High, Starting Configuration– MSEL Pins Are “Polled” to Determine Configuration Mode
Pull-up Resistor Pulls nSTATUS High Configuration Data Is Clocked in by DCLK on:
– DATA0 (Serial)
– DATA[7..0] (Parallel)
nSTATUS Drives Low if an Error Occurs All User I/O Pins Are Tri-Stated During Configuration
1
217
© 1998 Altera Corporation ®
3 4, 5 6
General Steps of Configuration
CONF_DONE Releases, Pulled High when Configuration Is Complete FLEX Device Still Needs to be Clocked 10 Times for Initialization
– Registers Reset
– User I/O Enabled
– Operation Begins
Device Enters User Mode To Reconfigure Device, Pulse nCONFIG Low then High
– All User I/O Pins Will Tri-State
21
218
© 1998 Altera Corporation ®
General Steps of Configuration
INIT_DONE– A Dual-Purpose Pin that Can Be Used to Monitor Initialization
– As a Configuration Pin,
• Drives Low During Configuration and Initialization
• Released at End of Initialization
3 4, 5 621
For more information and instructions on enabling INIT_DONE pin in MAX+plus II,refer to description of Device Option “Enable INIT_DONE Output” in
Configuration appendix
219
© 1998 Altera Corporation ®
Just as Logic Options Allow Control over the Synthesis of a Design,
Device Options Allow Control over Configuration & Initialization of Device
Device Options in MAX+plus II
Device Options Can Be Assigned
Globally, to the Project/Design Individually, to a Device
220
© 1998 Altera Corporation ®
Configuration Scheme (Mode) Should Be Set in MAX+plus II Device Options
– Setting This Device Option Will Not Determine the Configuration Mode of the FLEX Device on the Circuit Board
– Values of MSEL Pins at nCONFIG Low-to-High Transition Determine Configuration Mode of the FLEX Device
Configuration Device Options
See Configuration Appendix for More Information & Detailed Descriptions of Device
Options that Control Configuration
221
© 1998 Altera Corporation ®
Configuration Appendix Contains More Details about the Configuration Scheme
(Mode) in MAX+plus II
Configuration Device Options
Setting Configuration Scheme (Mode) in MAX+plus II– Allows User to Control User-Mode State of the Dual-Purpose
Configuration Pins– Allows Pins Unique to a Configuration Mode to Be Reported in
the Device Summary Section of Report File
© 1998 Altera Corporation
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®
FLEX In-System
223
© 1998 Altera Corporation ®
Always Refer to the Device Summary Portion of the Report File for Details on How Every Pin on a FLEX Device Should Be Connected on Board
In-System Considerations
Refer to the In-System Appendix for Detailed Description of the Legend for This Section of the Report File
224
© 1998 Altera Corporation ®
Unused User I/O Pins (Appear as Reserved Pins in Report File) Will Drive Out; Leave Them Unconnected on Board.
In-System Considerations
Refer to the In-System Appendix for a Detailed Description of the Legend for This Section of the Report File
225
© 1998 Altera Corporation ®
All FLEX 10K Family Devices Have Dedicated JTAG Pins.
If Not Used, JTAG Pins Should Be Tied as Described in AN 39, JTAG Boundary-Scan Testing in Altera Devices. Device Summary of Report File Shows which Pins Are Dedicated JTAG Pins
Unused Dedicated Inputs/Clocks Should Be Grounded as Reflected in the Device Summary of the Report File.
(In This Example, Pin 20 Is a Dedicated Input that Is Not Used)
FLEX In-System Considerations
226
© 1998 Altera Corporation ®
As the Configuration Scheme (Mode) Is Set in MAX+plus II, Pins Unique to that Mode Will Be Revealed in Device Summary Section of the Report File
Configuration Appendix Contains Instructions for Setting the Configuration Scheme (Mode) in MAX+plus II
In-System Considerations
227
© 1998 Altera Corporation ®
FLEX In-System Considerations
Dedicated Bi-directional, Open-Drain Configuration Pins Should be Pulled to VCC with a 1K Resistor
nSTATUS CONF_DONE
Dedicated Configuration Pins that Are Bi-directional or Inputs Must be Driven at All Times in User Mode
– Pulled High or Low According to Configuration Instructions (See Configuration Appendix)
– Driven by Logic
MSEL nSTATUS nCONFIG DATA0
CONF_DONE DCLK nCE
Dedicated Configuration Output Pin nCEO Will Drive out Low During User Mode; Leave It Unconnected
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FLEX In-System Considerations
FLEX 10K Family Devices Have No Internal Pull-up Resistors on Device Pins Available in User Mode Except JTAG Pins
Pull-up Resistor on JTAG Pins Is a Weak Pull-up– Use External 1K Pull-up Resistor on JTAG Pins for
JTAG Boundary-Scan Testing with FLEX Devices
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Registers on which Preset Has Been Emulated with Not-Gate-Push-Back Will Be Cleared During Power-up– Registers with a Preset and No Clear
in Original Design
– Report File Shows Those Registers onwhich Not-Gate-Push-Back Has Been Implemented
FLEX In-System Considerations
Due to Inversion of the Register Output from Not-Gate-Push-Back, Outputs Driven by These Registers Will Be Logic Level High upon Power-up
Registers on Which the Preset Has Been Emulated with an Asynchronous Load Will Power-up Low
– These are registers on which both a clear and a preset signal are present in the original design.
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FLEX In-System Considerations
Not-Gate-Push-Back Can Be Prevented by Turning Off the Option Not Gate Push Back in MAX+plus II
– The Preset Will Be Emulated with an Asynchronous Load This Option Can Be Controlled through the Synthesis Styles,
Globally or Individually
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FLEX In-System Documentation
Invaluable for System Considerations – Application Note 75: High-Speed Board Designs– Operating Requirements for Altera Devices Data Sheet
Using MultiVolt™ Circuitry Feature of FLEX Devices– Refer to MultiVoltTM Appendix for Important System
Considerations
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Altera Technical Support
Reference MAX+plus II On-Line Help Consult Altera Applications (Factory Applications Engineers)
– Hotline: (800) 800-EPLD (6:00 a.m. - 6:00 p.m. PST)– E-mail: [email protected]
Field Applications Engineers: Contact Your Local Altera Sales Office
Receive Literature by Mail: (888) 3-ALTERA FTP: ftp.altera.com World-Wide Web: http://www.altera.com
– Use Atlas (Altera Technical Support) Solutions to Search for Answers to Technical Problems
– View Design Examples– View Customer Training Class Schedule & Register for a Class
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Achieving High Performance and Optimal Utilization in
Altera's FLEX 10K Family
Appendices
Appendices
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Appendices - Table of Contents
Global Nets, Peripheral Control Bus
Configuration
In-System Considerations
MultiVoltTM
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Appendix - Global Nets
AppendixGlobal Nets, Peripheral Control Bus
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Dedicated Inputs, Global Nets
If the Global Option Automatic Global
is selected, MAX+plus II will automatically place high fan-
out inputs on the Dedicated Inputs and Dedicated
Clocks. Driven signals will be on the global control and
clock nets.
This option is invoked by default.
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Dedicated Inputs, Global Nets
Assigning the
Individual Logic Option Global Signal
to an input pin places that input on a
Dedicated Input or Dedicated Clock.
Driven signals will be on the global
control or clock nets.
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Dedicated Inputs, Global Nets
Placing a “global” primitive after an input
pin places that input on a Dedicated
Input or Dedicated Clock. The driven
signal will be on a global control or clock
net.
An input can be assigned to a particular Dedicated Input or Dedicated Clock. For the driven signal to be placed on a global control or clock net, the input also needs to have the Individual Logic Option Global Signal assigned to it or automatically be determined a global signal by the Global Option Automatic Global.
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Internally-Driven Global Control Nets
The four global control nets can be driven by internal logic
The two global clock nets cannot be driven by internal logic
Placing a “global” primitive after logic
that drives a control or data signal
places the output of that logic on a
global control net.
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Internally-Driven Global Control Nets
Assigning the Individual Logic
Option Global Signal to logic places
the output of that logic on a global
control net.
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Internally-Driven Global Control Nets
Anything driven by the logic that drives GLOBAL signal will also be globally driven.
If this is undesired, consider duplicating logic.Now, in this example, tout is not driven by a global net.
In this example, both the output pin tout and the clock signal to the second register are driven by a global control net.
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Internally-Driven Global Control Nets
globalcontrol
net
globalcontrol
net
Dedicated Input Internal Logic
The four global control nets can be driven by
Dedicated Inputs or internal logic
globalclocknet
globalcontrol
net
globalcontrol
net
globalclocknet
Dedicated Clock
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Internally-Driven Global Control Nets
Global Net 0 A A A B A E B H L J
Global Net 1 A B B C C C D F J H
Global Net 2 B D D E G F H J N L
Global Net 3 C F F H J E L I M K
EP
F10K
10/A
EP
F10K
20
EP
F10K
30/A
/E
EP
F10K
40
EP
F10K
50/V
/A/E
EP
F01K
70
EP
F10K
100/
B/A
/E
EP
F10K
130/
V/A
/E
EP
F10K
250A
/E
EP
F10K
200E
MAX+plus II will, whenever possible, automatically locate driving logic in these optimum locations
Should signals be slower than expected, however, explore the locations of driving logic
Although LE1 of a LAB in any row can drive a global control net,
fastest results for a particular net will from originate from LE1 of LABs in the corresponding rows above
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Internally-Driven Global Control Nets
A Dedicated Input or Dedicated Clock must be
grounded if it is not used.
If a global control net is internally driven and its
Dedicated Input is thus unused, which Dedicated
Input is to be grounded?
The Device Summary section of the Report File
reveals all pins to be grounded.
In this example, pin 20 is an unused Dedicated
Input.
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Global Nets
Whether internally-driven or brought on-chip through a Dedicated Input/Clock,
verify in the report file that a signal is on a global control or clock net by looking for
… GLOBAL(signal_name) …
in the Equations of the Report File:
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Peripheral Control Bus
net 0 A A A B A E B H L J
net 1 A B B C C C D F J H
net 2 B D D E G F H J N L
net 3 C F F H J E L I M K
net 4 B C C D E B F D H F
net 5 C E E F I H J L P N
net 6 A A A A A A A C G E
net 7 A B B C B B C E I G
net 8 B C C D D D E G K I
net 9 B D D E F I G N R P
net 10 C E E F H G I K O M
net 11 C F F G J H K M Q O
EP
F10K
10/A
EP
F10K
20
EP
F10K
30/A
/E
EP
F10K
40
EP
F10K
50/V
/A/E
EP
F01K
70
EP
F10K
100/
B/A
/E
EP
F10K
130/
V/A
/E
EP
F10K
250A
/E
EP
F10K
200E
Although LE1 of a LAB in any row can drive any net of the Peripheral Control Bus,
fastest results for a particular net will from originate from LE1 of LABs in the corresponding rows above
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Appendix - Configuration
AppendixConfiguration
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Configuration Pins
nCONFIG– Input pin– Low to high transition starts configuration– Driving low at any time will reset FLEX device and prepare it for
reconfiguration– Pull-up to VCC with 1K resistor
MSEL0, MSEL1– Input pins– FLEX devices “poll” these pins to determine configuration mode
• Can be tied to VCC, GND• Values can be determined by board logic to allow FLEX device on
board to be configured in more than one mode
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Configuration Pins
DCLK– Used to clock configuration data into the FLEX device– Input or output pin:
• Passive modes - externally-generated clock source input to FLEX device
• Configuration EPROM mode - clock signal generated by EPC1, EPC1441 input to FLEX 10K Family Device
DATA[ ]– Input pins– Used to send data to the FLEX device– Serial (DATA0) or parallel (DATA[7..0])– Note DATA[7..1] are typically user I/O. They are converted to
configuration pins when a parallel-type Configuration Scheme (Configuration Mode)
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Configuration Pins
nSTATUS– Bi-directional, open-drain pin; pull-up to VCC with 1K resistor– FLEX device pulls this low after power up – Released and pulled high by resistor within 100 ms after power up– Drives low if an error is detected in configuration data– If driven low by outside source, FLEX device enters error state
CONF_DONE– Bi-directional, open-drain pin; pull-up to VCC with 1K resistor– As an output, low before and during configuration– Released when all configuration data is received; when released, becomes an
input– As an input
• a low will delay initialization(NA for FLEX 10K Family devices configured in “Configuration EPROM” mode in which CLK_USR can be used to delay initialization)
• a high directs the device to enter initialization
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Configuration Pins
INIT_DONE– A user I/O pin that can be converted to a configuration pin to monitor initialization
– As a configuration pin,
• output pin; pull-up to VCC with 1K resistor
• drives low during configuration and initialization; released at end of initialization
For more information and instructions on enabling INIT_DONE pin in MAX+plus II,refer to description of Device Option “Enable INIT_DONE Output” in
Configuration Device Options section of this appendix
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Configuration Device Options
After configuration, FLEX devices must be clocked 10 times for the initialization process in which the devices’ registers are cleared, user I/O are enabled, and the device begins operation. The source of these 10 clock pulses is typically either from an oscillator internal to the FLEX device or externally input on the DCLK pin.
Alternatively, for certain configuration modes, the 10 clock pulses can be input on the CLK_USR pin. This circuitry can be used to synchronize the initialization of several FLEX devices.
To control the initialization of the FLEX device from the CLK_USR pin, select the User-Supplied Start-Up Clock (CLK_USR) option in MAX+plus II.
For more information regarding to which devices and configuration modes this option applies, refer to the family-specific configuration application notes.
(all FLEX families)
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Configuration Device Options
If an error occurs during configuration, nSTATUS drives low and configuration stops. Typically, some user intervention is required to begin configuration again.
Alternatively, if the MAX+plus II option Auto-Restart Configuration on Frame Error is selected, the FLEX device will automatically begin configuration again with no user intervention required.
For more information regarding specific devices and modes, refer to the family-specific configuration application notes.
During configuration, the user I/O of a FLEX device are tri-stated and the registers are cleared.
Typically, during initialization, the user I/O are enabled before the registers.
Alternatively, if the MAX+plus II option Release Clears Before Tri-States is invoked, the registers will be enabled before the user I/O.
(all FLEX families)
(all FLEX families)
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Configuration Device Options
On FLEX 10K Family devices, a specific user I/O pin can be configured as a pin to monitor the status of initialization.
Typically, this pin is a user I/O pin, tri-stated during configuration and enabled with all other user I/O during initialization.
Alternatively, if the option Enable INIT_DONE Output is selected, this pin can be configured as the INIT_DONE output, in which case it should be pulled to VCC with a 1K resistor. Rather than being tri-stated during configuration and becoming enabled with all other user I/O, this pin will drive low during configuration and be released (pulled high) at the end of initialization, as the device enters user mode. The INIT_DONE pin is available as a user I/O during user mode.
(FLEX 10K Family Devices)
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Configuration Device Options
Selecting a Configuration Scheme (mode) in this window
– converts applicable dual-purpose pins to configuration pinsex: Data [7..1]
– configures the user-mode settings of the dual-purpose pins to be the recommended settings for a configuration mode
These settings are written into the POF and SOF files so that the pins will operate appropriately during configuration and user mode.
Selecting a Configuration Scheme (mode) in this window, however, does not determine the configuration mode of the FLEX device. The actual configuration mode is determined only by the voltages at the MSEL pins at the time that the nCONFIG pin transitions from low to high.
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Configuration Device Options
Certain pins of FLEX devices are dedicated to configuration; they are never available as user I/O. (ex: MSEL, nSTATUS, nCONFIG, etc.)
Other pins can serve as dual-purpose pins; they can be used as configuration pins during configuration and as user I/O in user mode.
A user can configure these dual-purpose pins so that during user mode they are:
– available as user I/O
– reserved - not available as user I/O, but not tri-stated; these pins will drive out in user mode and should be left unconnected on a board
– tri-stated - tri-stated and not available as user I/O
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Configuration Device Options
As the Configuration Scheme (mode) is selected within the Device Options, MAX+plus II will default to mode-specific recommended settings for the dual purpose pins.
These recommended settings for the dual-purpose pins are reflected in the Device View section of the Report File:
see the In-System Considerations Appendix for an explanation of the Report File pin legend
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Configuration - Related Topics
Refer to In-System Considerations Appendix
If utilizing MutliVoltTM feature of FLEX, additionally refer to MultiVoltTM Appendix
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Appendix - In-System
AppendixIn-System
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Chip-Wide Reset, Output Enable
Either Globally to an entire project/designor on an Individual device,two specific user I/O pins can be configured to dedicated use as
– Chip-Wide Reset– Chip-Wide Output Enable
These Chip-Wide controls will be– Active low– Non-invertable
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Chip-Wide Reset, Output Enable
– The Chip-Wide Reset will affect every register in the FLEX device.
– The Chip-Wide Output Enable will affect every output in the FLEX device.
TheChip-Wide ResetandChip-Wide Output Enable will not appear in the Equations of the Report File.
They will appear in the Device Options and Device Summary sections of the Report File.
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With Slow Slew Rate assigned, delays become (see data book)
– output buffer and pad delay - tOD3
– IOE output buffer enable - tZX3
Assigning Slow Slew Rate
Assigning the Individual Logic Option Slow Slew Rate to an output pin will slow the speed
at which an output transitions
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Assigning Slow Slew Rate
The Report File reveals which outputs have been implemented with slow slew rates
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Automatic Open-Drain Pins
The Global Option Automatic Open-Drain Pins allows MAX+plus II to automatically implement appropriate outputs as open-drain pins.
By default, this option is selected.
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Automatic Open Drain Pins
The Report File reveals which pins have been implemented as open drain
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Assigning PCI_I/O
Assigning the Individual Logic Option PCI_I/O to a pin will clamp the maximum voltage of
that pin to VCCIO
Pins to which PCI_I/O have been assigned cannot tolerate voltages above VCC IO
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Assigning PCI_I/O
The Report File reveals which outputs have been implemented with PCI_I/O
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Report File Legend for Pins
The Device Summary portion of a Report File contains
– the Configuration Scheme (mode) as set in MAX+plus II’s Device Options
– a list of other Device Option settings
– a device view that reveals how every pin on the device should be connected
– a “legend” for this device view
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Report File Legend for Pins
This pin has no logic driving it; leave unconnected on board
VCC pin for device core
VCC pin for device I/O
GND pin for device core
GND pin for device I/O
Unused I/O pin, which MUST be left unconnected on board because it will drive out
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Report File Legend for Pins
Dedicated configuration pin that is generally not available as user I/O in user mode (see last page of this appendix) -MSEL, nSTATUS, nCONFIG, CONF_DONE, DCLK, nCE, nCEO
Dual-Purpose configuration pins - see Configuration Appendix, Configuration Device Options
Chip-Wide Reset, Chip-Wide Output Enable if user enabled this functionality
See JTAG Appendix
Not applicable to FLEX
Dual-Purpose configuration pins - see Configuration Appendix, Configuration Device Options
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Vertical Migration
When vertically migrating to larger or smaller devices
– Designs must be recompiled
– Timing should be re-analyzed
• Review whether IOE or LE register provides shorter set-up time for device
– Pin-outs in device data sheets show which pins should remain no-connects so that designs can be re-compiled for smaller devices
When migrating among same density devices of different families,
EPF10K50 > EPF10K50V, EPF10K50V > EPF10K50A, EPF10K30 > EPF10K30A, for example
– Designs must be recompiled
– Timing should be re-analyzed
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Appendix - MultiVoltTM
AppendixMultiVoltTM
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MultiVoltTM Devices
Selecting the Individual or Global Device Option Low Voltage I/O enables MAX+plus II’s timing analysis to reflect the correct output timing when the MultiVoltTM feature of FLEX is utilized.
Note selecting this option only adjusts the timing model used in MAX+plus II. It has no bearing on the actual voltage of the devices on a circuit board. Connecting VCCIO and GNDIO to the appropriate voltages on the circuit board determine the I/O voltage of the FLEX device.See following page.
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The Device Summary section of the Report File reveals which device pins are
– VCCINT VCC for device core
– VCCIO VCC for device pins
– GNDINT GND for device core
– GNDIO GND for device pins
These pins should be tied to the appropriate voltage sources on a circuit board.
MultiVoltTM Devices
Timing changes when utilizing the MultiVoltTM feature of FLEX devices
(MAX+plus II timing analysis reflects these changes)
– output buffer and pad delay becomes tOD2 (see data book)
– IOE output buffer enable delay becomes tZX2 (see data book)
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MultiVoltTM Devices
In addition to In-system and Configuration considerations (see appendices),
System Considerations for MultiVoltTM
– Signals into the configuration input pins may be of level VCCINT or VCCIO as the FLEX inputs can be driven by signals of both VCCINT and VCCIO levels(see presentation slide entitled Altera’s MultiVoltTM Offering)
– Download cables can operate with their VCC equal to VCCINT or VCCIO of the FLEX device
– When configuring with an EPC1 or EPC 1441
• 10K/V/A/B Devices
– VCC for the EPC1, EPC1441 must be equal to VCCINT of the FLEX device as the inputs of an EPC1, EPC1441 are not tolerant to voltage levels higher than its VCC
• 10KB/E Devices
– VCC for the EPC1, EPC1441 may be 3.3 V or 5V as the 10KB/E devices do not actively drive high during configuration
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MultiVoltTM Devices
In addition to In-system and Configuration considerations (see appendices),
System Considerations for MultiVoltTM
– Pull-ups on open-drain pins may be tied to VCCINT or VCCIO; applicable to(as these pins will either be grounded or tri-stated)
• user I/O that have been implemented as open-drain pins• nSTATUS, CONF_DONE
– Pull-ups on other user I/O should be tied to VCCIO