ENGR. RASHID FARID CHISHTILECTURER,DEE, FET, IIUI

CHISHTI@IIU.EDU.PK

WEEK 9

BEHAVIORAL MODELINGMOORE MACHINE

FPGA Based System Design

Saturday, April 15, 2023

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www.iiu.edu.pk Saturday, April 15, 2023

Mealy Machine vs Moore Machine

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module Moore_mdl (x,AB,CLK,RST); // Moore state diagram input x,CLK,RST; output [1:0]AB; reg [1:0] PrState, NxtState; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge CLK or negedge RST) // to handle reset and clock if (~RST) PrState = S0; // Initialize to state S0 else PrState = NxtState; // Clock operations always @ (PrState or x) // to Determine next state case (PrState) S0: if (~x) NxtState = S1; else NxtState = S0; S1: if (~x) NxtState = S3; else NxtState = S2; S2: if (~x) NxtState = S3; else NxtState = S2; S3: if (~x) NxtState = S0; else NxtState = S3; endcase

assign AB = PrState; // to determine outputendmodule

www.iiu.edu.pk Saturday, April 15, 2023

Moore Model

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module test_Moore_Circuit; reg x, CLK, RST; // inputs for circuit wire [1:0] AB; // output from circuit Moore_mdl mm1 (x, AB, CLK, RST); initial begin CLK = 0;

repeat (14) #5 CLK = ~CLK; end initial begin x = 0;

repeat (7) #10 x = ~ x;end

initial begin RST = 1; #3RST = 0; #3RST = 1;

endendmodule

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Test Bench

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Examples

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Moore Machine

// Structural description of sequential circuitmodule Moore_mdl (x, y, AB, CLK, RST); input x, CLK, RST; output y; output [1:0] AB; wire Ta, Tb, A, B; assign Ta = x & AB[0], Tb = x; //Flip-flip input equations assign y = AB[1] & AB[0]; //Output equation T_FF BF (AB[0], Tb, CLK, RST); // Instantiate T flip-flops T_FF AF (AB[1], Ta, CLK, RST);endmodule

module T_FF (Q,T,CLK,RST); // T flip-flop output Q; input T,CLK,RST; reg Q; always @ (posedge CLK or negedge RST) if (~RST) Q = 1'b0; else Q = Q ^ T;endmodule

www.iiu.edu.pk Saturday, April 15, 2023

Structured Programming

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// Stimulus for testing sequential circuitmodule test_Moore_mdl; reg x, CLK, RST; // inputs for circuit wire y; wire [1:0] AB; // output from circuit Moore_mdl mm1 (x, y, AB, CLK, RST); initial begin RST = 1; #7 RST = 0; #3 RST = 1;

end initial begin CLK = 0;

repeat (20) #5 CLK = ~CLK;endinitial begin x = 1; repeat (10) #10 x = ~ x;

endendmodule

www.iiu.edu.pk Saturday, April 15, 2023

Test Bench

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module Moore_mdl (x,Y, AB, CLK,RST); // Moore state diagram input x,CLK,RST; output [1:0]AB; output Y; reg [1:0] PrState, NxtState; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge CLK or negedge RST) // to handle reset and clock if (~RST) PrState = S0; // Initialize to state S0 else PrState = NxtState; // Clock operations always @ (PrState or x) // to Determine next state case (PrState) S0: if (x) NxtState = S1; else NxtState = S0; S1: if (x) NxtState = S2; else NxtState = S1; S2: if (x) NxtState = S3; else NxtState = S2; S3: if (x) NxtState = S0; else NxtState = S3; endcase

assign AB = PrState; // to show state assign Y = AB[0] & AB[1]; // to show stateendmodule

www.iiu.edu.pk Saturday, April 15, 2023

Moore Machine: Behavioral Programming

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