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EFFICIENT REGISTER RENAMING AND RECOVERY FOR HIGH-PERFORMANCE PROCESSORS

in association with

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EFFICIENT REGISTER RENAMING AND RECOVERY

FOR HIGH-PERFORMANCE PROCESSORS

GUIDED BY, PRESENTED BY, Ms . JYOTHISREE K R JINTO GEORGE Asst. Professor ECE S7 A ECE Department , MLMCE. NO:45

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1.INTRODUCTION2.EXISTING SYSTEM3. PROPOSED SYSTEM4.ADVANTAGES5.DISADVANTAGES6.APPLICATIONS7.FUTURE SCOPE8.CONCLUSION9.REFERENCE

CONTENTS

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Modern superscalar microprocessors implement out-of-order and speculative execution.

Register renaming technique is used increase the performance of the processor.

Modern superscalar processors implement register renaming using either RAM or CAM.

1. INTRODUCTION

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Register renaming uses two kinds of registers-

Logical registers Physical registers

A new hybrid scheme is presented here.

It combines the best of both RAM-CAM register renaming approaches.

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Many mechanisms are there for enhancing the concurrent execution of instructions.

All these mechanisms require register renaming technique.

Register renaming techniques solve write after read and write after write data hazards.

RAM and CAM are two approaches used for register renaming at present.

2.EXISTING SYSTEM

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RAM Approach

RAMs provide faster access times.

RAM provides energy efficient access to register mappings.

It’s not appropriate to avoid recovery penalties.

RAM approaches use a free register queue(FRQ)

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CAM Approach

CAM structures have as many rows as the number of available physical registers.

Each row maintains the information for renaming and recovery.

It is more appropriate to avoid recovery penalties.

Source registers are renamed to physical registers.

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HYBRID RAM–CAM approach for Register Renaming

Hybrid RAM-CAM approach is a combination of both RAM and CAM register renaming.

The hybrid scheme uses two methods:

A CAM containing all register mappings up to date

A RAM acting as a cache of the CAM

3.PROPOSED SYSTEM

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The CAM is indexed by physical registers or logical registers.

The RAM is indexed by a logical registers.

Register renaming is performed by just accessing the RAM.

In hybrid RAM–CAM. (a) Instruction reach at the rename stage. (b) Destination registers are mapped to the new physical registers (c)The new mapping is recorded both in the RAM and the CAM.

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PIPELINED IMPLEMENTATION OF THE HYBRID SCHEME

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The block diagram can be divided in three sections:

A.Clearing Previous Destination Mappings

B. Destination Register Renaming

C. Source Register Renaming

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A. Clearing Previous Destination Mappings

CAM entries corresponding to previous destination mappings are cleared

For the valid entries, physical register identifiers are obtained

B. Destination Register Renaming

Free physical registers are mapped to the destination registers.

Setting and updating new mappings.

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C. Source Register Renaming

The RAM is accessed in the first stage.

Mappings are obtained.

On a miss, an associative CAM search is performed in the second stage.

A hazard arises during the second stage.

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Fast and energy-efficient access to register mappings.

Reduces the power consumption.

It reduces the access time.

Leakage energy is lower for hybrid schemes

4.ADVANTAGES

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Hardware is complex.

5.DISADVANTAGES

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This technique can be used in instruction level processors(ILP)

To remove false data dependencies in a straight code sequence

6.APPLICATIONS

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In processors where high speed and energy-efficient register renaming is required.

7.FUTURE SCOPE

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Presented a renaming mechanism consisting of a RAM and a CAM

A final hybrid design that took the best of both approaches

Hybrid designs also reduced the dynamic energy

Hybrid designs are to be more efficient than the RAM approaches both in terms area and energy

8.CONCLUSION

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[1] Efficient Register Renaming and Recovery for High-Performance Processors bySalvador Petit, Member, IEEE, Rafael Ubal, Julio Sahuquillo, Member, IEEE, and Pedro López, Member, IEEE

9.REFERENCE

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