AgO Analog Circuit Optimization

Analog & RF Circuit Optimization

10X Faster & Max Yield

Hillol Sarkar

[email protected]

What we will talk about

• Company Background

• Challenges in Analog and RF design

© Copyright AgO Inc 20112

• Overview of AnXplorer

• Competitive Differentiation

Company Background

• Founded in 2007

• Held senior positions at National

• Held senior position in GE and Toshiba

• Awarded 8 Patents and 15 papers -National


• AgO - Advanced Generation Optimization

• Global Sales & Marketing Presence Q4 2011

Challenges in Analog & RF Design

Achieving design specification

• Meeting or beating performance while minimising cost of implementation

• Managing greater complexity in operating and power saving modes

Maximising yield

• Validating greater numbers of process, voltage and temperature corners

• Efficiently centering design across all PVT corners using Monte Carlo


Respin avoidance

• Analog circuits are responsible for ~ 50% of IC design re-spins

• Re-spins can mean missing market windows and unbudgeted costs

• Managing greater complexity in operating and power saving modes

Design porting

• Moving existing circuit designs to similar technologies

• Re-centering design to meet constraints of new technology

Classic Analog Design Methodology

• Design methodology has changed little over the years

• Manual, iterative design with many SPICE runs

Define topology

&

resize devices

Design

specification &

constraints

Spice


Physical layout

& adjust

Extraction

Layout verification

Spice

Optimization StrategyOptimization Strategy

Feasibility Global Optimization Centering Database

Description• DC Operation• Increase Margin

Description• Single Corner• Meet performance

Description• All Corners• Rapid Size

Description• Conflict• Change Priority


• Increase Margin• Quick check• Best Design Space

• Meet performance• Monte Carlo• Ready for Center

• Rapid Size• Ready for P&R

• Change Priority• System Analysis

AgO Optimization Strategy

AnXplorer Goals

• Quickly size W/L a circuit in a given technology

• Explore suitability of different design options

• Robust design over PVT & Monte Carlo

• Support all types of devices


• Explore results using database

• Optimize production yield

AgO Design Methodology

AnXplorer automates device sizing

Define topology Design

specification &

constraints

Feasibility

Global


Physical layout

& adjust

Extraction

Layout verification

Centering

Porting of Existing Circuits

Vendor X

Common challenge

• Port existing design in technology X (say

180 nm) to technology Y (in 180 nm)

• Ensure that original design goals are met


Vendor Y

AnXplorer approach

• Start with original sized circuit

• Define variable ranges for target circuit

• “One click” command

• Optimises and centers with new PVT

corners

Same Node

Porting

Prioritized Design Objectives

• Most tools support a weight-based prioritisation

for multiple objectives

– Designer is often unsure of relative weights

• AnXplorer supports hierarchical design objectives

– User defines relative priority of different objectives


– User defines relative priority of different objectives

• AnXplorer achieves important objectives before

optimizing others

Implicit Objectives

• Imposes implicit objectives on

conditions of devices at DC

operating point

• Customizable objectives

• Detects common sub-circuits and

imposes constraints on their

Examples of sub-

circuits:

• transistors in

saturation

• transistors in linear

region


imposes constraints on their

operating conditions

• Ensures a robust DC operating

point

• Feature only available for MOS

devices

region

• current mirrors

• level shifters

• differential pairs

• voltage reference

• current mirror banks

• etc

Core Optimization Technology

Early Optimisation tools

• Frequently relied on traditional

convex/gradient methods

• These are known to have difficulty with

multiple local minima

AnXplorer


AnXplorer

• Based on Evolutionary algorithm

• Capable of finding global minimum in

presence of many local minima

• Successfully optimised tough tests e.g.

Rastrigin’s function

• Optional logarithmic partitioning of

design space

Supports both simulation-based

optimization & equation-based

optimization

Multiple Local Minimum


Trade-off Analysis

• Finds multiple design points satisfying design

objectives

• Creates exploration database for post-

optimization analysis

– Database stores all explored design points


– Database stores all explored design points

– Query language or GUI

• Useful for trade-off analysis with conflicting

objectives

• Useful for “what-if” analysis

Industry Standard Formats

Design objectives Un-sized circuit

Schematics

Definition of

Design variables

Compatible with existing design flows


AnXplorer

Sized and centered

net list

Exploration

database for

Trade off analysis

Design Environment

• Spice Simulators

– Cadence Spectre

– Synopsys HSpice

– Mentor Eldo

– Multi-threading support


– Multi-threading support

• Operating system

– Red Hat Enterprise Linux RHEL 5

Competitive Differentiation

• One product, four optimization steps

• Robust centering to maximise yield –Monte Carlo

• Implicit objectives for stable DC operation (CMOS)

• Hierarchical design objectives

• User can perform trade-off analysis


• User can perform trade-off analysis

• Industry standard formats and simulators

• Core based on Evolutionary Algorithm

Analog and RF Optimization New generation Analog & RF Circuit Optimization

Hillol Sarkar

[email protected]@ago-inc.com

Devices & Hardware

AgO Analog Circuit Optimization