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1) What is inter delay and intra delay?
always @(posedge clk)
A <= #5b;
#5A<=b;
Explain with wave form.
2) What is sensitivity list? Is it mandatory to mention all inputs of pure combinational
circuit in sensitivity list? Answer with reason.
3) What is difference between case, case-x and case-z?
4) What will be the output of following code?
always@(clk) begin
a= 0;
a<=1;
$display(a);
end
5) Difference between === and ==?
6) Find error(if any) in following code
always@(clk)
begin
if (2’b01 & 2’b11)
$display( “xyz”);
else
$display(“ zyx”);
end
7) Explain race condition with example and how can you avoid that in Verilog?
8) What is the difference between always block and initial block in Verilog code?
9) What is the meaning of time scale 10ns/1ns? Why we need to use it?
10) Write Verilog initial block for following diagram
11) What is difference between blocking and non-blocking statement? Explain with example
how they execute.
12) Difference between $strobe , $display and $monitor?
13) What is the value of rag_c[5] at simulation time 14?
reg x, y, z; reg [15:0] reg_a, reg_b; integer count; initial begin x = 0; y = 1; z = 1; count = 0; reg_c = 16'b0; reg_b = reg_a; reg_c[5] <= #14 1'b1; reg_b[15:13] <= #10 {x, y, z}; count <= count + 1; end
14) What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
15) What is FSM? Types of FSM? Explain with diagram.
