AgO Product Overview

Analog & RF Circuit Optimization

© Copyright AgO Inc 20112

What we will talk about

• Company Background

• Challenges in Analog and RF design

• Overview of AnXplorer

• Competitive Differentiation


Company Background

• Founded in 2007• Held senior positions at National• Held senior position in GE and Toshiba• Awarded 8 Patents and 15 papers -National• AgO - Advanced Generation Optimization• Global Sales & Marketing Presence Q4 2011


Challenges in Analog & RF Design

Respin avoidance• Analog circuits are responsible for ~ 50% of IC design re-spins• Re-spins can mean missing market windows and unbudgeted costs

Achieving design specification• Meeting or beating performance while minimising cost of implementation• Managing greater complexity in operating and power saving modes

Maximising yield• Validating greater numbers of process, voltage and temperature corners• Efficiently centering design across all PVT corners using Monte Carlo

Design porting• Moving existing circuit designs to similar technologies• Re-centering design to meet constraints of new technology


Classic Analog Design Methodology• Design methodology has changed little over the years• Manual, iterative design with many SPICE runs

Define topology &

resize devices

Physical layout& adjust

ExtractionLayout verification

Designspecification &

constraints

Spice

Spice


Optimization Strategy Optimization Strategy

Feasibility Global Optimization Centering Database

Description• DC Operation• Increase Margin• Quick check• Best Design Space

Description• Single Corner• Meet performance• Monte Carlo• Ready for Center

Description• All Corners• Rapid Size• Ready for P&R

Description• Conflict• Change Priority• System Analysis

AgO Optimization Strategy


AnXplorer Goals

• Quickly size W/L a circuit in a given technology• Explore suitability of different design options • Robust design PVT variations using Monte Carlo• Support all types of devices• Explore results using database


AgO Design Methodology

AnXplorer automates device resizing using SPICE runs

Define topology

Physical layout& adjust

ExtractionLayout verification

Designspecification &

constraints

AnXplorer

Feasibility

Global

Centering


Porting of Existing Circuits

AnXplorer

Technology X

Technology Y

Common challenge• Port existing design in technology X (say 180 nm) to technology Y (in 180 nm)• Ensure that original design goals are met

AnXplorer approach

• Start with original sized circuit• Define variable ranges for target circuit• “One click” command• Optimises and centers with new PVT

corners

Porting


Prioritized Design Objectives

• Most tools support a weight-based prioritisation for multiple objectives– Designer is often unsure of relative weights

• AnXplorer supports hierarchical design objectives– User defines relative priority of different objectives

• AnXplorer achieves important objectives before optimizing others


Implicit Objectives

• Imposes implicit objectives on conditions of devices at DC operating point

• Customizable objectives• Detects common sub-circuits and

imposes constraints on their operating conditions

• Ensures a robust DC operating point

• Feature only available for MOS devices

Examples of sub-

circuits:

• transistors in

saturation• transistors in linear

region• current mirrors• level shifters• differential pairs• voltage reference• current mirror banks• etc


Core Optimization Technology

Early Optimisation tools• Frequently relied on traditional convex/gradient methods• These are known to have difficulty with multiple local minima

AnXplorer• Based on Evolutionary algorithm• Capable of finding global minimum in presence of many local minima• Successfully optimised tough tests e.g. Rastrigin’s function• Optional logarithmic partitioning of design space

Supports both simulation-based optimization & equation-based optimization


Multiple Local Minimum


Trade-off Analysis

• Finds multiple design points satisfying design objectives

• Creates exploration database for post-optimization analysis– Database stores all explored design points– Query language or GUI

• Useful for trade-off analysis with conflicting objectives

• Useful for “what-if” analysis


Industry Standard Formats

AnXplorer

Design objectives Un-sized circuit

Schematics

Sized and centerednet list

Exploration database for

Trade off analysis

Definition of Design variables

Compatible with existing design flows


Design Environment

• Spice Simulators– Cadence Spectre – Synopsys Finesim & HSpice– Mentor Eldo – Multi-threading support

• Operating system– Red Hat Enterprise Linux RHEL 5 & 4


Competitive Differentiation

• One product, four optimization steps

• Robust centering to maximise yield –Monte Carlo

• Implicit objectives for stable DC operation (CMOS)

• Hierarchical design objectives

• User can perform trade-off analysis

• Industry standard formats and simulators

• Core based on Evolutionary Algorithm


Promotion

• EE Times Global Coverage

• Document Download 300 per month

• No of customers engagement 50 in 2012

• Trade Show: DATE 2012 Dresden Germany


Market Segment - Power


HD TV


Wireless

560 LTE Devices83 SuppliersMIMO Technology

http://www.gsacom.com/news/statistics.php4


Medical Devices

• Low Power• Reliability• Performance• Long Life• Implant Devices $15B

Analog and RF Optimization New generation Analog & RF Circuit Optimization

Hillol [email protected]