May 2, 2012 1

Minimizing Customer Returns by Using User-Defined Fault Models

Design for Test and Manufacturing Test

Evgeny Polyakov

Euro Application Engineer

Mentor Graphics

May 2, 2012 2

Introduction

• Analysis has shown that many customer returns are due to undetected cell-internal faults

• State-of-the-art fault models do not target cell-internal defects sufficiently

• A new method and new defect-oriented fault model is needed

2

How can we do it?

Z D2 S1 D0 S0 D1

vdd

gnd

May 2, 2012 3

State-of-the-art Fault Models

• The N-Detect model targets every fault multiple times. Big disadvantage is the large amount of additional test patterns and as such high test costs

• The Embedded-Multi-Detect (EMD) model is an N-Detect model without increasing the pattern count or test costs

• The Gate-Exhaustive model tests every gate/cell exhaustively. This results into a very large amount of test patterns and as such into very high test costs

3

• The Stuck-At model is known and used very widely. ATPG tools can generate compact test patterns. The test is easy to implement

• The Transition model assumes gross delays at library cell level. The ATPG needs to generate at least a two cycle normal mode test sequence

• The timing-aware and Path-Delay model assumes smaller delays along critical paths. The ATPG needs to generate a pattern that will activate the path and will propagate an edge through it

May 2, 2012 4

User-Defined Fault Models

• Defines stimulus criteria for fault detection

• Stimulus criteria “manually” determined based on experience or test failures

• Leverages existing Fault Models (Stuck-at, transition)

4

2Truth Table for MUX

Cell “MUX2” Fault “Z1” test StaticFault “Z”=1;Condition “D0”=0,“D1”=0,“S”=0; test StaticFault “Z”=1;Condition “D0”=0,“D1”=1,“S”=0; test StaticFault “Z”=1;Condition “D0”=0,“D1”=0,“S”=1;

UDFM that offers test alternatives for fault detection

May 2, 2012 5

Gate Exhaustive UDFM

• A way to specify that all possible stimulus combinations be used to detect faults

• Creates a larger test set

5

Cell “MUX2” Fault “SA_s0_00_Z” test StaticFault “Z”=1;Condition “D0”=0,“D1”=0,“S”=0; Fault “SA_s0_01_Z” test StaticFault “Z”=1;Condition “D0”=0,“D1”=1,“S”=0; … Fault “SA_s1_11_Z” test StaticFault “Z”=0;Condition “D0”=1,“D1”=1,“S”=1; // Transition Fault “TR_s0_00_Z” test DelayFault “Z”=1;Condition “D0”=10,“D1”=00,“S”=00; Fault “TR_s0_01_Z” test DelayFault “Z”=1;Condition “D0”=10,“D1”=11,“S”=00; … Fault “TR_s1_11_Z” test DelayFault “Z”=0;Condition “D0”=01,“D1”=11,“S”=11;

2Truth Table for MUX

May 2, 2012 6

Cell-Aware UDFM

• Map the layout related cell-internal defects to the transistor-level netlist

• Modify/sweep parameters to determine effects of opens and bridges

• Generate stimulus that will detect the defects

• Generate the UDFM

6

Z D2 S1 D0 S0 D1

vdd

gnd

D0

S0

S0N

D2

S1

P23

P63

N23

N24

P24

N33

N32

P38

P34

D1

N28

P54

N57

N41

P48

N63

P31

Z

S1N

Layout

Transistor netlist

May 2, 2012 7

Cell-Aware Methodology

7

Defect Matrix

SPICE parasitics

netlist

Layout Extraction

Analog Fault Simulation

Cell-Aware Fault Model Generation

Library Characterization Flow

defects

CAM

Reports

Cell-Aware UDFM Model

May 2, 2012 8

UDFM Development

• Starting with GDS2 for each cell, extract a SPICE netlist including parasitics

• Perform SPICE simulations and sweep the parasitic capacitor to values from 1KΩ to 20KΩ to model bridges

• Replace each parasitic resistor with 1GΩ to model opens

• Compare fault-free simulation results with fault injected simulation results

8

May 2, 2012 9

UDFM At-Speed

• Transient analysis of SPICE simulation is done at two time frames exhaustively

• The lowest detectable cells are complex cells (MUXs, AOs) and cells with high drive strength

• Gross delay and small delay fault models target different kinds of bridge types

9

May 2, 2012 10

Cell-Aware: Identifying Potential Defects

10

• A bridge between select S0 and data input D1 would typically not be detected using traditional test generation

• Standard test generation would not assign a value to D1 when S0 is active

Mentor/AMD: “Cell-aware library characterization for advanced technology nodes and production test results from a 32nm processor F. Hapke, et al., 2012 DATE

May 2, 2012 11

Production Test Design

Fault models • Stuck-At (Slow-Speed) • Transition (At-speed ND5) • Cell-Aware (Slow-speed) • Cell-Aware(At-speed)

GPU

Core Core

Core Core

• AMD Notebook processor • ~200mm2, 1.5B transistors • 4 Cores: 35M transistors/core • Process: 32nm • 1MB L2 cache • DDR3 Memory • DirectX GPU / 822M transistors

Mentor/AMD: “Cell-aware library characterization for advanced technology nodes and production” test results from a 32nm processor (Presentation) F. Hapke, et al., 2012 DATE

May 2, 2012 12

Production Test Flow

12

Mentor/AMD: “Cell-aware library characterization for advanced technology nodes and production test results from a 32nm processor F. Hapke, et al., 2012 DATE

May 2, 2012 13

Production Test Results

• 800K IC tested

• Slow-speed cell-aware patterns detected 231 defects that the standard test patterns did not detect

• Slow-speed cell-aware patterns reduced DPM by 292

• At-speed cell-aware patterns detected 609 defects that the standard test patterns did not detect

• At-speed cell-aware patterns reduced DPM by 771

• Combining both cell-aware tests shows a DPM reduction of 885

13

Mentor/AMD: “Cell-aware library characterization for advanced technology nodes and production test results from a 32nm processor F. Hapke, et al., 2012 DATE

Total 699 fails = 885 PPM

468fails

90fails

Slow-speed At-speed

141fails

total

231 fails292 ppm

total

609 fails771 ppm

May 2, 2012 14 14

• Cell-Aware UDFM provides targeted test coverage for defects internal to cells

• Generating Cell-Aware UDFM is a straight-forward exercise, and only has to be done once for each library

• Significant results have already been seen in production test and those results have been published

Summary