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IEEE P1581 Simplifying Connectivity Tests for Complex Memories and other Non-Boundary Scan Devices Heiko Ehrenberg, GOEPEL Electronics Chair of IEEE P1581 working group [email protected]

IEEE Std 1581 VTS 2011 slides

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Page 1: IEEE Std 1581   VTS 2011 slides

IEEE P1581Simplifying Connectivity Tests for Complex Memories

and other Non-Boundary Scan Devices

Heiko Ehrenberg, GOEPEL ElectronicsChair of IEEE P1581 working group

[email protected]

Page 2: IEEE Std 1581   VTS 2011 slides

IEEE P1581 - Introduction

• Scope:Low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1) is not feasible;

• Purpose:Improve interconnect test for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs;

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Page 3: IEEE Std 1581   VTS 2011 slides

Basic concept

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IEEE 1581 device

IEEE 1149.1

device(s)

Memory Controller

Test Control

TTM(optional)

Memory Cells

CombinationalTest Logic

xInputBus

y

Output Bus

Optional Test Pin(if no TTM)

PCB

Page 4: IEEE Std 1581   VTS 2011 slides

Key features

• Simple test logic implementation for memory devices (and possibly other complex, slave-type components)

• No extra pins required

• Not relying on complex memory access cycles

• Fast test execution, small test vector set

• Usable with any access methodology (Boundary scan, functional, ICT)

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Page 5: IEEE Std 1581   VTS 2011 slides

Test mode control• Dedicated test pin (TPN), or

• One of seven transparent test mode (TTM) control methods:

• Non-functional stimulus (NFS)

• Designated command codes (DCC)

• Simultaneous input/output (SIO)

• Clock frequency (CKF)

• Analog level (ANL)

• Conditional power-up initiation (CPI)

• Default power-up initiation (DPI)

These methods require additional board-level and/or controlling device DFT to be implemented

Test entry or exit is triggered by a condition on the pins that would otherwise never exist under normal functional conditions

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Page 6: IEEE Std 1581   VTS 2011 slides

Test mode control - NFS

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WE

CS

WE

CS

IEEE 1581Device

ToTDO

FromTDI

ControlDevice

Page 7: IEEE Std 1581   VTS 2011 slides

Test mode control - DCC

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CD2

STB

IEEE 1581Device

CD1

CD2

STB

ToTDO

FromTDI

ControlDevice

CD1

Page 8: IEEE Std 1581   VTS 2011 slides

Test mode control - CPI

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WE

CS

WE

CS

Non-VolatileIEEE 1581

Device

ToTDO

FromTDI

ControlDevice

OR

OR

PCB DFTControl

Test mode is entered if a predetermined set of logical input states exist at a predetermined period after device power-up.

Page 9: IEEE Std 1581   VTS 2011 slides

Test logic

• One of three defined test logic architectures:

• XOR (3-input XOR or XNOR gates)

• IAX (XOR, Inverters, and AND gates)

• XOR-2 (2-input XOR or XNOR gates)

• Or a custom test logic that satisfies rules in IEEE P1581

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Page 10: IEEE Std 1581   VTS 2011 slides

Test logic example - XOR

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IEEE 1581 Memory Device

Inputs 1-6

XOR

XOR

XOR

XOR

O1

O2

O3

O4

Page 11: IEEE Std 1581   VTS 2011 slides

Optional test functions

• Optional test functions accessible via test pattern partitioning

• Examples include:

• Reading a device identification (ID)

• Control line continuity test

• Built-in self test (BIST) access

• Other public or private commands

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Page 12: IEEE Std 1581   VTS 2011 slides

Status of IEEE P1581

• Balloting completed

• Ballot group voted to accept IEEE P1581

• IEEE needs to review and finalize acceptance

• Official adoption as IEEE Std 1581 expected for mid 2010

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