View
1.000
Download
1
Category
Preview:
DESCRIPTION
Citation preview
On-Chip Stress Analysis in a Package Interaction Test Chip
Dr. Javad Zarbakhsh, KAI GmbH
Carlos O. Trejo-Caballero (Master Student, KAI)
Bala Karunamurthy, KAI
Thomas Detzel (Infineon Villach)
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 2 of 15
Overview
� Introduction and motivation
� Finite Element Model
� Stress sensor test chip
� Accurate geometry build for microscopic model
� Simulation vs. Measurements
� Conclusion
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 3 of 15
Length scales in automotive electronics
1 nm 1 µm 1 mm 1 m
Quantum mechanicsAb-initio calculations
Discrete mechanicsMolecular dynamics simulation
Continuum mechanicsFinite element simulation
Atoms
Molecules
Interfaces/voids/cracks
Bond wires
Chips
Packages
Boards
DMOS
Thin films
Thin film grains
Cars
Mobiles
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 4 of 15
Process Overview: From Wafer to Package
Wafer Saw Die Attach Wire Bond Mold / Cure
Deflash & Plate Trim & Form
Silicon wafer
CMOS Process flow
- Lithography - Etching- Deposition
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 5 of 15
MC
LF
WBNon-planar layers
DA
Failures in chip package system
Chip crack during fabrication Chip crack after temperature cycling
Mold compounddegradation
Imide, dielectrics and passivation cracks
Chip cracks
Si-lattice deformation
Die pad delamination
Die top delamination
Bond-interfaceDegradation
Solder / Glue dela-mination of die attach
Corrosion ofmetallization
Package – Board issues
Matching behavior of bipolar and MOS devices
Plastic deformation of metallization layers
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 6 of 15
Approach for design improvement
Chip corners
Chip center (Symmetry study)
Below Cu patternCu edges
Below bond pads (Bond study)
Near poly heater(Thermal cycling / Fatigue)
Stress cells carefully positioned to address chip-package failures
� On-chip stress cells
� Finite Element analysis
� Nested submodeling
� Understanding of microscopic stress
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 7 of 15
Finite Element Model – Chip and Package
� The first approach is to consider a simple model with simplified geometry
� Material models need to be accurate
MC
CuSi Lead Frame (LF)Die Attach
Si
LF
DA
CuCu
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 8 of 15
Elastoplastic model development for Cu films
Numerical fit onto the experimental data
Fit parameters: � saturation stress � activation free enthalpy (activation energy)
References: � Lederer, Zarbakhsh, Huang, et. al. “Thermomechanical Stresses in Copper Films at Elevated
Temperature”, Journal of Microelectronics and Electronic Packaging, 7, pp. 1-6 (2010)� Zarbakhsh et al. “Modeling of multi-temperaturecycle wafer curvature experiment”, Proceeding of
ITherm2010
General material model in the framework of von Mises plasticity
Uni-axial stress-strain curves
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 9 of 15
Chip – Package model
1. Cu Deposition
2. Heat up to die attach temperature
3. Soldering die attach and Lead frame
4. Cool down to room temperature
5. Heat up to molding temperature
6. Molding process
7. MC curing for 4 hours
8. Cool down to room temperature
9. MC storage for 24 hours
Die deformation scaled by factor 100
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 10 of 15
On-chip stress sensors
� Stress sensors allow real-time monitoring of on-chip stress
� Each stress cell consists of two MOSFET devices arranged as a current mirror.
� Two different types of stress cells were used to measure shear and normal stress in the chip plane.
� Calibrations were done to determine the piezo-resistivity coefficients.
� The stress cells are located at various desired points of interest. Stress sensors Bond pad Focus of sub-model
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 11 of 15
Accurate FEM geometry using FIB cut
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 12 of 15
Finite Element – Sub-modeling
Nested sub-modeling approach:
� Solve a coarse model
� Apply the resulting displacements as boundary conditions to subsequent sub-models
� Continue with the next submodel
Region of interest
� Itermetallic dielectrics: sub micron
� Package (centimeter)
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 13 of 15
Stress comparison – Planar vs. nonplanar
� The magnitude of stress is similar
� Evolution and concentration of stress are highly geometry dependent
� local stress concentration sites vary
� sharp corners in non-planar geometries show high compressive stress
� Finally, we can detect the stress singularities sites and redesign
first principle stress
High stress
Reference: Javad Zarbakhsh, Bala Karunamurthy, Carlos O. Trejo-Caballero, Endre Barti, and Thomas Detzel, Microscopic stress simulation of non-planar chip Technologies, Microelectronics Reliability, 50, pp. 16661671 (2010)
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 14 of 15
Conclusion
� FE nested submodeling is an efficient method when the model includes various length scales, e.g. chip package simulations
� On-chip stress sensors and test chips are important vehicles for verifications of FE models
� Accurate geometry build is necessary when stress singularities cause chip failure
� Design improvement approach:
� Develop your own material models
� Use simplified FE model for whole system
� Use accurate geometry for submodels micromodels
� Use calibration methods to verify simulations,
e.g. use on-chip stress sensors
� Calculate singularities using FEM � Find sites with high stress
� Redesign singularities (Layout modification)
April 7th 2011 ANSYS Conf 2011, Vienna, Austria Dr. Javad Zarbakhsh, javzar@gmail.com 15 of 15
Acknowledgement
� Federal Ministry of Economics and Labor, Austria � GZ: 98.362/0112-C1/10/2005
� Carinthian Economic Promotion Fund (KWF)� KWF-18911|13628|19100.
Thanks for your attention
Kontaktieren Sie uns – wir helfen Ihnen gerne!
CADFEM (Austria) GmbH Wagenseilgasse 14
1120 Wien
Tel. +43 (0)1 587 70 73 – 0
E-Mail. info@cadfem.at
Web. http://www.cadfem.at
Immer aktuell informiert – CADFEM Blog, Xing und Youtube-Channel
CADFEM Blog - Umfassend informiert
• News zur FEM-Simulation - What‘s hot? What‘s new?
• Video-Tutorials - ANSYS, LS DYNA & mehr
• Hinter den Kulissen: CADFEM intern
CADFEM Youtube Channel - Tips & Trick
• Video Tutorials - ANSYS Software und CADFEM Applications
CADFEM auf Xing - News kompakt
• Vorschau auf Events & Seminare
• Neue CADFEM Produkte
• CADFEM Jobbörse
Fragen? Interesse?
Recommended