On chip photonic-nima afraz

On-Chip Photonic

Nima AfrazKazem farjami nejhad

For the Advanced VLSI Course Term Paper Presentation

February 20121

Why? To improve performance and energy in a future

many-core processor, it is vital that the interconnect technology is optimized.

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Optical networks silicon photonics is a promising new interconnect

technology with lower power, higher bandwidth density, and shorter latencies.

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Contents Introduction Architecture Overview Analysis and Comparison Conclusion

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IntroductionLow-latency high-bandwidth: How? Packet-switched networks

Made of carefully engineered links Represent a shared medium that is highly scalable Provide enough bandwidth

But... Communication infrastructure is the major power

consumer Power dissipation budget limit will be achieved

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IntroductionPhotonic Technology Photonic interconnection networks

Low power dissipation independent of capacity Ultra-high throughput Minimal access latencies

Why less power? Once a photonic path is established, the data is

transmitted end to end without the need for repeating, regeneration and buffering

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IntroductionPhotonic Technology Is photonic technology cheap enough?

Since 2006, high-speed optical communications directly between silicon die are possible at a price-performance point competitive with traditional electrical interconnects

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Contents Introduction Architecture Overview Analysis and Comparison Conclusion

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Architecture Overview Phonotonic NoC Hybrid Approach

Photonic interconnection network Transmits high-bandwidth messages

Electronic control network Controls the photonic network with small control messages

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Architecture OverviewPhonotonic NoC Before transmitting a photonic message, an

electronic control packet (path-setup packet) is routed in the electronic network acquires and sets up a photonic path for the

message Photonic message is transmitted without

buffering once the path is acquired

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Architecture OverviewPhotonic NoC Main advantage of photonic paths is bit-rate

transparency Photonic switches switch on or off once per

message Energy dissipation does not depend on the bit-rate

whereas Traditional CMOS routers switch with every bit of

transmitted data

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Architecture OverviewPhotonic NoC Another advantage is low loss in optical

waveguides Power dissipated on a photonic link is completely

independent of the transmission distance No matter if 2 cores are 2mm or 2cm apart

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Architecture OverviewPhotonic NoC 2X2 photonic switching elements

Capable of switching messages in a sub nanosecond switching time

Switches are arranged as a 2D matrix and organized in groups of four Each group is controlled by an electronic router to

construct a 4X4 switch Convenient for planar 2D topologies such as mesh

and torus

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Architecture OverviewPhotonic NoC Each node includes a network gateway to serve as

a photonic network interface Electronic/Optical (E/O) and Optical/Electronic (O/E)

conversions Clock synchronization and recovery Serialization/deserialization

Wavelength division multiplexing is used at network gateways to provide larger data capacity Optical equivalent of using parallel wires

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Architecture OverviewLife of a Packet on Photonic NoC Write operation from a processor in Node A to a memory in

Node B1. A path-setup packet is sent on the electronic control

network Includes information on the destination address of Node B

and additional control information such as priority and flow id

2. Path-setup packet is routed in the electronic control network Reserves the photonic switches along the path At every router in the path, the next hop is decided

according to the routing algorithm used3. Path-setup packet reaches the destination

Photonic path is reserved A fast light pulse is sent on the photonic path from Node B

to Node A to indicate that the path is reserved

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Architecture OverviewLife of a Packet on Photonic NoC

4. The photonic message starts from Node A follows path from switch to switch until it reaches Node B

5. Message transmission completed6. Path-teardown packet is sent from Node B to

Node A on the electronic control network to release the path

7. Photonic message is checked for errors and a small acknowledgement packet is sent from Node B to Node A on the electronic control network

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Contents Introduction Architecture Overview Analysis and Comparison Conclusion

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Analysis and ComparisonPower Dissipation Case Study Setup

16-node CMP where each processor requires BWpeak = 1024 Gb/s BWavg = 800 Gb/s

Traffic driven by the processors is assumed to be uniform

Both networks use a mesh topology and XY dimension order routing

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Analysis and ComparisonPower Dissipation Reference Electronic Network

4X4 mesh, where each router is integrated in one processor tile

PW=765W Photonic Network

8X8 photonic mesh 256 photonic switching elements organized as 64

4X4 switches PW=30W (96% less power dissipation)

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Contents Introduction Architecture Overview Analysis and Comparison Conclusion

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Conclusion The advantages of photonic medium

High transmission bandwidth Low power consumption

Recent (i.e. since 2006) advances make photonic technology practical for NoCs Fabrication of silicon photonic devices Integration of photonic devices in CMOS electronic

circuits Next generation of NoCs will possibly use

photonic technology

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References On the Design of a Photonic Network-on-Chip

Assaf Shacham, Keren Bergman, Luca P. Carloni First International Symposium on Networks-on-Chip (NOCS'07), pp. 53-64,

2007 Photonic Networks-on-Chip: Opportunities and Challenges

Michele Petracca, Keren Bergman, Luca P. Carloni IEEE International Symposium on Circuits and Systems 2008 (ISCAS 2008),

pp. 2789-2792, May 2008 The Case for Low-Power Photonic Networks on Chip

Assaf Shacham, Keren Bergman, Luca P. Carloni Proceedings of the 44th Annual Conference on Design Automation, pp. 132-

135, 2007 Maximizing GFLOPS-per-Watt: High-Bandwidth, Low Power Photonic

On-Chip Networks Shacham, K Bergman, LP Carloni IBM P=ac2 Conference, October 2006

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