OPTIMIZED REVERSIBLE VEDIC MULTIPLIERS

OPTIMISED REVERSIBLE VEDIC MULTIPLIERS FOR HIGH SPEED LOW

POWER OPERATIONS

PPDV Engg College. Project Associates

AB.Samjida

A.Vamsi Krishna

CH.U.L.Prakash

G.Sivaparvathi

Objective

Reversible logic gates

Vedic multiplication

Comparison of multipliers

2x2 Vedic multiplication

RCA(Ripple carry adder)

4x4 Vedic multiplier

Output comparison

8x8 Vedic multiplier and comparison

Applications

Advantages

Presentation Topics:

Objective of The project

• Designing a 8x8 bit reversible Vedic multiplier

circuits based on Urdhava Triyakbhyam Sutras

(Vertical and Crosswise Algorithm).

• To optimize the area, Quantum cost and garbage

output of the Vedic multiplier circuits.

For the logic Synthesis- Xilinx 9.2ISE simulation.

Verilog HDL programing language.

Utilized tools:

Reversible logic gates

A Reversible logic gate is an n-input and n-output device with one-to-one mapping.

These gates are helps to determine the outputs from the inputs and also the inputs can be uniquely recovered from the outputs.

By using these gates lowering the power dissipation. Different reversible gates are Feymann gate, Peres gate, HNG gate etc.

One or more operation can implement in a single unit called Reversible Gate

BASIC REVERSIBLE LOGIC CIRCUITSFeynman Gate: It is a 2x2 gate and its logic circuit is as shown in the

figure. It is also known as Controlled Not (CNOT) Gate. It has quantum cost one and is generally used for Fan Out purposes. The input vector is I (A, B) and the output vector is O (P, Q).

(a) Feynman gate

(b): combinational circuit diagram of 1x1 feynman gate

2. Peres Gate: 3. Fred kin Gate:

4. HNG Gate:

VEDIC MULTIPLICATION: URDHVA TIRYAKBHAYAM SUTRA:

The “Urdhva Tiryagbhyam” Sutra is a general multiplication formula applicable to all cases of multiplication such as binary, hex, decimal and octal. The Sanskrit word “Urdhva” means “Vertically” and “Tiryagbhyam‟ means “crosswise”. Fig 4 shows an example of Urdhva Tiryagbhyam(UT).

R is the Result and PC is thePrevious Carry

Urdhva Tlryakbhyam algorithm for binary multiplication

Comparison between Vedic and normal multiplication:

Vedic multiplication normal multiplication

2x2 REVERSIBLE VEDIC MULTIPLICATION BY USING URDHVA TIRYAKBHYAM(UT):

Logic Implementation

RIPPLE CARRY ADDER BY USING REVERSIBLE LOGIC GATES:

4-bit ripple carry adder

5-bit ripple carry adder

BLOCK DIAGRAM OF 4x4 UT MULTIPLIER:

Logic Reversible Vedic multiplication

Vedic multiplication

TIME DELAY 11.018nsec 12.708nsec

AREA 24% 54%

Number of LUT’s 31 33

Comparison of two4-bit multipliers

BLOCK DIAGRAM OF 8x8 UT MULTIPLIER

Comparison of two 8-bit multipliers

logic Reversible Vedic multiplication

Vedic multiplication

TIME DELAY 20.726nsec 20.980nsec

AREA 48% 48%

Number of LUT’s 32 32

OUTPUT OF 8X8 MULTIPLIER

This multiplier may find applications in Fast Fourier Transforms

(FFTs).

To provide universal multiplication with low power high speed.

Applications in system on chip design as technology scales.

In public key cryptography like AES encryption and decryption.

Laptop/Handheld/Wearable Computers

Implanted Medical Devices

Wallet “smart cards”

APPLICATIONS:

Increase the Speed of the system To acquire good efficiency of the system Reduce the time delay as well as path

delay in the multiplier.

ADVANTAGES:

In this project presents the Urdhva Tiryakbhayam Vedic

Multiplier realized using reversible logic gates. Firstly a basic 2x2 UT

multiplier is designed. After this, the 2x2 UT multiplier block is cascaded

to obtain 4x4 multiplier. The ripple carry adders which were required for

adding the partial products were constructed using HNG gates.similarly

design the 8x8 multiplier.

Vedic multipliers for speedy operations not only for mental

calculations but also for hardware implementations.

Conclusion:

THANK YOU