View
205
Download
0
Category
Tags:
Preview:
Citation preview
04/13/2023 Department Of Computer Science and Engg.
1
Acceleration of XMLParsing through Prefetching
IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 8, AUGUST 2013Authors: Jie Tang, Student Member, IEEE, Shaoshan Liu, Chen Liu, Member, IEEE, Zhimin Gu, and Jean-Luc Gaudiot, Fellow, IEEE
Presented By :Rohit Deshpande
Mtech CSE 2nd sem130913016
04/13/2023 Department Of Computer Science and Engg.
2
Contents• Introduction• Motivation• The XML Parsing Process• Prefetching Techniques• Methodology• Performance Analysis of XML Parsing• Memory-Side Acceleration• Implementation Feasibility• A Exemplary Hardware Implementation• Conclusion• Future Work
04/13/2023 Department Of Computer Science and Engg.
3
Introduction
• Extensible Markup Language (XML) has become a widely adopted standard for data representation and exchange.
• Neutrality, Application independency and Flexibility. • Morgan Stanley’s Financial Services system, spends
40% execution time on processing XML documents.• This paper proposes to accelerate XML parsing from
the memory side.
04/13/2023 Department Of Computer Science and Engg.
4
Motivation
• XML is widely adopted standard for data representation and exchange.
• Parsing of XML data introduce significant overhead.
04/13/2023 Department Of Computer Science and Engg.
5
The XML Parsing Process
04/13/2023 Department Of Computer Science and Engg.
6
• XML data parsing consists of three steps: • Character conversion • Lexical analysis• Syntactic analysis.
04/13/2023 Department Of Computer Science and Engg.
7
XML Parsing Modeling
04/13/2023 Department Of Computer Science and Engg.
8
• Event Driven Parser
• Tree-Based Parser
04/13/2023 Department Of Computer Science and Engg.
9
Prefetching Techniques
• Data prefetching has been proposed as a speculative technique to bridge the speed gap between CPU and memory subsystem.
• Classic Prefetching Techniques:-• Sequential Prefetching• Stride Prefetching• Strem Prefetching• Correlating Prefetching
04/13/2023 Department Of Computer Science and Engg.
10
Overview of Hardware Prefetching• System Integration of Hardware Prefetcher
04/13/2023 Department Of Computer Science and Engg.
11
Architecture of Hardware Prefetcher
04/13/2023 Department Of Computer Science and Engg.
12
Methodology
• XML Parsers and Benchmarks
04/13/2023 Department Of Computer Science and Engg.
13
• Performance and memory Modeling
04/13/2023 Department Of Computer Science and Engg.
14
Native versus Managed Execution
04/13/2023 Department Of Computer Science and Engg.
15
Performance Analysis Of XML Parsing
• Data Flow of XML Parsing
04/13/2023 Department Of Computer Science and Engg.
16
• Disk Data Loading
04/13/2023 Department Of Computer Science and Engg.
17
Data Loading from Memory Side
• Data flow starting from main memory, going through each cache layer and finally fetched in to CPU.
• The CPI of speed test is 0.80. • Using the SAX parser, the CPI of standard is
1.27, which introduces 58.75 % of overhead.• Using the DOM parser, the CPI of standard
becomes 1.42, which introduces 77.5% of overhead.
04/13/2023 Department Of Computer Science and Engg.
18
Memory-Side Acceleration
• Prefetchers
04/13/2023 Department Of Computer Science and Engg.
19
• Performance Analysis
04/13/2023 Department Of Computer Science and Engg.
20
• Performance Improvement for SAX Parsing
04/13/2023 Department Of Computer Science and Engg.
21
• Performance Improvement for DOM Parsing
04/13/2023 Department Of Computer Science and Engg.
22
Implementation Feasibility
• Bandwidth Utilization
04/13/2023 Department Of Computer Science and Engg.
23
• Hardware Cost and Energy Consumption
04/13/2023 Department Of Computer Science and Engg.
24
04/13/2023 Department Of Computer Science and Engg.
25
• Energy Consumption of SAX Parsing
04/13/2023 Department Of Computer Science and Engg.
26
• Energy Consumption of DOM Parsing
04/13/2023 Department Of Computer Science and Engg.
27
A Exemplary Hardware Implementation
• Power consumption of the prefetcher on FPGA
04/13/2023 Department Of Computer Science and Engg.
28
• Hardware Cost and Power Consumption Comparison between eMIPS and Prefetcher
04/13/2023 Department Of Computer Science and Engg.
29
Performance comparison of L2-only versus two-level prefetcher
04/13/2023 Department Of Computer Science and Engg.
30
consumption comparison of L2-only versus two-level prefetcher
04/13/2023 Department Of Computer Science and Engg.
31
Conclusion
• Authors Proposed to make acceleration for XML parsing from memory side by improving its data loading performance.
• Reduce cache misses by up to 80 percent, which translates into up to 20 percent of performance improvement.
• 12.77 percent of energy saving.
04/13/2023 Department Of Computer Science and Engg.
32
Future Work
• The ultimate goal is to built a many core chip in which one core perform conventional general computing workloads and the other cores do XML parsing and Garbage Collection.
04/13/2023 Department Of Computer Science and Engg.
33
References• K. Chiu, M. Govindaraju, and R. Bramley, “Investigating the Limits of Soap Performance for Scientific
Computing,” Proc. IEEE 11th Int’l Symp. High Performance Distributed Computing (HPDC-11), 2002. • M.R. Head, M. Govindaraju, R. van Engelen, and W. Zhang, “Grid Scheduling and Protocols-Benchmarking
xml Processors for Applications in Grid Web Services,” Proc. ACM/IEEE Conf. Supercomputing (SC ’06), p. 121, 2006.
• P. Apparao et al., “Architectural Characterization of an XML-Centric Commercial Server Workload,” Proc.
33rd Int’l Conf. Parallel Processing, 2004. • P. Apparao and M. Bhat, “A Detailed Look at the Characteristics of xml Parsing,” Proc. First Workshop
Building Block Engine Architectures for Computers and Networks (BEACON ’04), 2004. • M. Nicola and J. John, “XML Parsing: A Threat to Database Performance,” Proc. 12th Int’l Conf.
Information and Knowledge Management, 2003. • Int’l HapMap Project: http://hapmap.ncbi.nlm.nih.gov/, 2013. SAX Parsing Model: http://sax.sourceforge.net, 2013.
04/13/2023 Department Of Computer Science and Engg.
34
• W3C, “Document Object Model (DOM) Level 2 Core Specifica-tion,” http://www.w3.org/TR/DOM-Level-2-Core, 2013.
• K. Chiu, T. Devadithya, W. Lu, and A. Slominski, “A Binary XML for Scientific Applications,” Proc. First Int’l Conf. e-
Science and Grid Computing, 2005. • XimpleWare, “VTD-XML: The Future of XML Processing,” http://vtdxml. sourceforge.net, Accessed 10, Mar. 2007. W. Lu, K. Chiu, and Y. Pan, “A Parallel Approach to XML Parsing,” Proc. IEEE/ACM Seventh Int’l Conf. Grid Computing,
Sept. 2006. • M.R. Head and M. Govindaraju, “Approaching a Parallelized XML Parser Optimized for Multi-Core Processor,” Proc.
Workshop Service-Oriented Computing Performance: Aspects, Issues, and Ap-proaches (SOCP ’07), June 2007. • R.D. Cameron, K.S. Herdy, and D. Lin, “High Performance XML Parsing Using Parallel Bit Stream Technology,” Proc.
Conf. Center for Advanced Studies on Collaborative Research, Oct. 2008. • L. Zhao and L. Bhuyan, “Performance Evaluation and Accelera-tion for XML Data Parsing,” Proc. Ninth Workshop
Computer Architecture Evaluation Using Commercial Workloads, 2006. • J. Moscola and J.W. Lockwood, “Reconfigurable Content-Based Router Using Hardware-Accelerated Language
Parser,” ACM Trans. Design Automation of Electronic Systems, vol. 13, article 28, 2008.
04/13/2023 Department Of Computer Science and Engg.
35
THANK YOU
Recommended