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7/31/2019 VLSI lect 5
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The Ideal Wire
The Lumped Model
The Lumped RC model
The Distributed rc Line
The Transmission Line
Electrical wire models
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Throughout most of the history of ICs, on-chip interconnect
wires were considered to be second class citizens that need
be considered only in special cases or when performing high-
precision analysis.
With the introduction of deep-submicron semiconductor
technologies, this picture is undergoing rapid changes.
The parasitic effects introduced by the wires display a
scaling behavior that differs from the active devices and
tend to gain in importance as device dimensions are reduced
and circuit speed is increased. 2
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In fact, they start to dominate some of the relevant
metrics of digital ICs such as speed, energy consumption,
and reliability.
This situation is aggravated by the fact that
improvements in technology make the production of ever
larger die sizes economically feasible, which results in an
increase in the average length of an interconnect wireand in the associated parasitic effects.
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Wiring of today’s ICs forms a complex geometry that
introduces capacitive, resistive, and inductive parasitics.
All three have multiple effects on the circuit behavior.
a) Increase in propagation delay
b) Impact on the energy dissipation and the power
distribution
c) Introduction of extra noise sources, which affects the
reliability of the circuit.
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A designer can decide to play it safe and include all these
parasitic effects in the analysis and design optimization
process. This conservative approach is non-constructive
and even non-feasible.
First of all, a ―complete‖ model is dauntingly complex
and is applicable only to very small topologies.
It is hence totally useless for today’s ICs with their
millions of circuit nodes.
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The circuit behavior at a given circuit node is determined
only by a few dominant parameters.
Bringing all possible effects to bear only obscures the
picture and turns the optimization and design process a
―trial-and-error‖ operation rather than an enlightened
and focused search.
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1) Inductive effects can be ignored if the resistance of the
wire is substantial — this is the case for long Al wires
with a small cross-section — or if the rise (fall) time of
the applied signals is large.
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Fortunately, substantial simplifications often can be made.
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3) When the separation between neighboring wires is
large, or when the wires run together only for a short
distance, inter-wire capacitance can be ignored, and all
the parasitic capacitance can be modeled as capacitance
to ground.
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2) When the wires are short, or the cross-section of the
wire is large, or the interconnect material used has a low
resistivity, a capacitance-only model can be used.
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The circuit parasitics of a wire are distributed along its
length and are not lumped at a single position.
Yet, when only a single parasitic component is dominant,
or when the interaction between the components is small,
it is often useful (possible) to lump the different fractions
into a single circuit element.
The lumped model
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The advantage of this approach is that the effects of the
parasitic, then, can be described by an ordinary
differential equation.
Description of distributed elements requires PDEs.
As long as the resistive component of the wire is small and
the switching frequencies are in the low to medium range,
it is necessary to consider only the capacitive component
of the wire and to lump the distributed capacitance into a
single capacitor 10
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In this model, the wire still represents an equipotential
region, and the wire itself does not introduce any delay.
The only impact on performance is by the loading effect
of the capacitor on the driving gate.
This capacitive lumped model is simple, yet effective, and
is the model of choice for the analysis of most
interconnect wires in digital ICs.
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C lumped = L cwire, with L the length of the wire and cwire
the capacitance per unit length. The driver is modeled as
a voltage source of source resistance R driver . 12
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While the lumped capacitor model is the most popular,
sometimes it is also useful to present lumped models of a
wire with respect to either resistance and inductance.
This is often the case when studying the supply
distribution network.
Both the resistance and inductance of the supply wires can
be interpreted as parasitic noise sources that introduce
voltage drops and bounces on the supply rails.
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The lumped RC model
On-chip metal wires of over a few mm length have a
significant resistance.
The equipotential assumption is no longer valid and aresistive-capacitive model has to be adopted
A first approach lumps the total wire resistance of eachwire segment into one single R and similarly combines the
capacitance into a single capacitor C - lumped RC model
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Consider the resistor-capacitor network below.
This network is called an RC tree
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This network has the following properties:
• the network has a single input node (labeled s)
• all the capacitors are between a node and the ground
• the network does not contain any resistive loops
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An interesting result of this topology is that there exists a
unique resistive path between the source node s and any
node i of the network. The total resistance along this path
is called the path resistance Rii. For example, the path
resistance between the source node s and node 4 is
R44 = R1 + R3 + R4
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The definition of the path resistance can be extended to
address the shared path resistance Rik, which represents
the resistance shared among the paths from the root
node s to nodes k and i:
For example, Ri4 = R1 + R3
and Ri2 = R1
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Assume now that each of the N nodes of the network is
initially discharged to GND, and that a step input is
applied at node s at time t = 0.
The Elmore delay at node i is then given by:
For the above circuit, the Elmore delay is:
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The designer should be aware that this time-constant
represents a simple approximation of the actual delay
between source node and node i.
Yet, in most cases this approximation has proven to be
quite reasonable and acceptable.
It offers the designer a powerful mechanism for
providing a quick estimate of the delay of a complex
network.
The Elmore delay is equivalent to the first-order time
constant of the network
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As a special case of the RC tree network, consider the
simple, non-branched RC chain (ladder) shown below.
This network is worth analyzing because it is a structurethat is often encountered in digital circuits, and also
because it represents an approximate model of a
resistive-capacitive wire.
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The Elmore delay of this chain network is:
This model can be used as an approximation of a
resistive-capacitive wire.
The wire with a total length of L is partitioned into N
identical segments, each with a length of L/N .
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The delay of a wire is a quadratic function of its length -
doubling the length of the wire quadruples its delay.
The delay of the distributed rc-line is one half of the delay
that would have been predicted by the lumped RC model.
The lumped RC model is pessimistic and inaccurate for
long interconnect wires, which are better represented by
the distributed rc model
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Voltage range Lumped RC
network
Distributed rc
network
0 to 50 % (tp) 0.69 RC 0.38 RC
0 to 63 % ( ) RC 0.5 RC
10 to 90% (tr) 2.2 RC 0.9 RC
0 to 90 % 2.3 RC RC
Step response of lumped and distributed RC
networks — points of interest
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Step response of a distributed rc line26
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a) Distributed rc delays need be considered only when
tpRC is comparable or larger than the tpgate of the driving
gate.
This defines a critical length Lcrit =
b) rc delays need be considered only when the rise (fall)
time at the line input is smaller than RC – R and C are
the total resistance and capacitance of the wire
Otherwise, lumped C model suffices27
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Propagation delay of
the network can be
approximated as:
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The transmission line
When the switching speeds become sufficiently fast, and the
quality of the interconnect material become high enough so
that the resistance of the wire is kept within bounds, the
inductance of the wire starts to dominate the delay behavior,
and transmission line effects must be considered.
The lossless transmission line is appropriate for wires at the
PCB level
For interconnections in ICs, the lossy transmission line
model should be considered.
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X = 0X = L
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Step response for Rs = 5 Zo, ZL =
X = L
X = 0
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Step response for Rs = Zo, ZL =32
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Step response for Rs = Zo /5 , ZL =33
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To avoid potentially disastrous transmission line
effects such as ringing or large propagation
delays, the line should be terminated, either at the
source (series termination), or at the destination
(parallel termination), with a resistance equal to
the characteristic impedance of the line.
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The response of a lossy RLC line to a step combines wave
propagation with a diffusive component.
The step input still propagates as a wave through the
line. However, the amplitude of this traveling wave is
attenuated along the line
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Farther from the source, the more the response
resembles the behavior of a distributed rc line.
The resistive effect becomes dominant, and the line
behaves as a distributed rc line when R >> Z0.
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1) Transmission line effects should be considered when
the rise (fall) time of the input signal t r (t f ) is smaller than
the time-of-flight of the transmission line ( t flight).
For on-chip wires with a length of 1 cm, one need worry
about transmission line effects only when t r < 150 ps.
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2) Transmission line effects should be considered only
when the total resistance of the wire is limited to R < 5 Zo
If this is not the case, the distributed rc model is more
appropriate.
Both the above constraints can be summarized in the
following set of bounds on the wire length:
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As transistor dimensions are reduced, the interconnect
dimensions must also be reduced to take full advantage of
the scaling process.
A straightforward approach is to scale all dimensions of
the wire by the same factor S as the transistors.
This might not be possible for at least one dimension of
the wire - the length.
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Scaling of wires
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Length of local interconnections, that connect closely
grouped transistors, scales in the same way as transistors.
Global interconnections, that provide the connectivity
between large modules, display a different scaling
behavior. (clock signals and data and instruction buses)
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The average length of these long wires is proportional
to the die size of the circuit.
When scaling the wire length, we have to differentiate
between local and global wires.
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Assume that all other wire dimensions (W , H , t) scale with
the technology factor S.
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We consider three models: local wires (S L = S > 1), constant
length wires (S L = 1), and global wires (S L = SC < 1).
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Parameter Relation Local
wire
Constant
wire
Global
wire
W, H, t 1/S 1/S 1/S
L 1/S 1 1/Sc
C LW/t 1/S 1 1/Sc
R L/WH S S² S²/Sc
RC L²/Ht 1 S² (S /Sc)²
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This leads to the scaling behavior as
S
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Scaling of the technology does not reduce wire delay.
A constant delay is predicted for local wires, while the delay
of the global wires goes up - in contrast with the gate delay
which reduces from year to year
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In the local wires, density and low-capacitance are crucial,
while keeping the resistance under control is crucial in the
global wires.
To address these conflicting demands, modern interconnect
topologies combine a dense and thin wiring grid at the lower
metal layers with fat, widely spaced wires at the higher levels.
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