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1www.stringtechnologies.net
www.unistring.com
VL
SI
foru
mVLSI Design m
ethodologies
By
K. Vasu
Senior Application engineer
vasu@unistring.com, vasu.vlsi@
gmail.com
UnistringTech Solutions Pvt. Ltd
# D10, 5th Floor, Eureka court, Beside Image hospitals, Ameerpet,
Hyderabad, ph:040- 23732798, 09440318188
www.unistring.com
String Technologies
#309, Vedericomplex, oppDilshukNagarbus Depot, Dilsukhnagar, H
yderabad,
ph: 040 –24151900
www.stringtechnologies.net
UTS VLSI forum
2www.stringtechnologies.net
www.unistring.com
VL
SI
foru
m
Electron � ���
System
The Big picture
3www.stringtechnologies.net
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VL
SI
foru
m
VLSI design M
ethodologies
•Full-C
ustom
VLSI D
esig
n
•Sem
i-Custom
VLSI D
esig
n
Sta
ndar
d c
ell bas
ed IC tec
hnolo
gy
Struct
ure
d A
SIC
IC tec
hnolo
gy
Pro
gra
mm
able
Logic
Dev
ice
(PLD
) IC
tec
hnolo
gy
4www.stringtechnologies.net
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VL
SI
foru
m
Full Custom design
Des
igner
han
d d
raw
s geo
met
ries
whic
h spec
ify
tran
sistors
and o
ther
dev
ices
for an
inte
gra
ted c
ircu
it.
Des
igner
must
be
an e
xper
t in
VLSI (V
ery L
arge
Sca
le Inte
gra
tion) des
ign.
Can
ach
ieve
ver
y h
igh tra
nsi
stor den
sity
(tran
sistors
per
squar
e m
icro
n); u
nfo
rtunat
ely, des
ign tim
e ca
n b
e
ver
y long (m
ultip
le m
onth
s).
Involv
es the
crea
tion o
f a
com
ple
tely
new
chip
, w
hic
h
consi
sts of ab
out a
doze
n m
asks (for th
e
photo
lito
gra
phic
man
ufa
cturing p
roce
ss).
5www.stringtechnologies.net
www.unistring.com
VL
SI
foru
m
Issues in Full Custom design (continued ..)
•O
ffer
s th
e ch
ance
for optimum perform
ance
.
–Per
form
ance
is bas
ed o
n a
vai
lable
pro
cess
tec
hnolo
gy, des
igner
skill, a
nd C
AD
tool as
sistan
ce.
•Fab
rica
tion c
osts ar
e hig
h -
all cu
stom
mas
ks m
ust b
e m
ade
so n
on-rec
urrin
g
engin
eering c
osts (N
RE) is h
igh (in
the
thousa
nds of dollar
s).
–If req
uired
num
ber
of ch
ips is h
igh then
can
spre
ad thes
e N
RE c
osts ac
ross
the
chip
s.
•The
firs
t cu
stom
chip
costs you a
bout $200,0
00
firs
t cu
stom
chip
costs you a
bout $200,0
00, but ea
ch a
dditio
nal
one
is m
uch
chea
per
.
6www.stringtechnologies.net
www.unistring.com
VL
SI
foru
m
•Fab
rica
tion tim
e from
geo
met
ry subm
ission to ret
urn
ed c
hip
s is a
t le
ast 6-8
w
eeks.
•Full c
ustom
is cu
rren
tly the
only
option for m
ixed
Anal
og/D
igital
chip
s.
•A
n e
xam
ple
VLSI la
yout is show
n b
elow
.
Issues in Full Custom design (continued ..)
7www.stringtechnologies.net
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VL
SI
foru
m
Sem
i-Custom standard cell based IC Technology
•Sta
ndar
d C
ell
–A
lib
rary
of pre
-des
igned
cel
l
–Pla
ce a
nd route
–In
tegra
te to y
ield
fin
al lay
out
ASIC
8www.stringtechnologies.net
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VL
SI
foru
m
•Gat
e A
rray
s
–A
rray
of pre
fabrica
ted g
ates
–“p
lace
” an
d route
–H
igher
den
sity
, fa
ster
tim
e-to
-mar
ket
–D
oes
not in
tegra
te a
s w
ell w
ith full-c
ust
om
Sem
i-Custom G
ate Arrays Technology
Structured
ASIC
9www.stringtechnologies.net
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VL
SI
foru
m
Sem
i-custom Programmable Logic Device
(PLD) IC
Technology
•PA
L
•CPLD
•FPG
A
10
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VL
SI
foru
m
11
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VL
SI
foru
m
Complex programmable logic device (C
PLD)
Programmable Logic Array
Typic
ally
a C
PLD
consi
sts of fe
w
tens to
few
hundre
ds of PA
Ls
12
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VL
SI
foru
m
I /O
cel
l
Logic
cel
l
Inte
rconnec
tion
Field programmable gate array (FPGA)
13
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VL
SI
foru
m
AlteraFLEX 10K logic cell
14
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VL
SI
foru
m
Full-custom Vs Sem
i-custom
15
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VL
SI
foru
m
Sem
i custom VLSI Design entry
(part of front end design)
�Sch
emat
ic E
ntry
�H
ardw
are
Des
crip
tion L
anguag
es
VH
DL
Ver
ilog
AH
DL
�Sta
te m
achin
e m
odel
s
�H
igh lev
el p
rogra
mm
ing lan
guag
es (la
test tre
nd)
system
C(C
++ c
lass
lib
rary
with V
erilog
synta
x)
�Few
Oth
er tec
hniq
ues
In sem
i cu
stom
VLSI des
ign sty
le the
required
logic
can
be
des
crib
ed
by a
ny o
ne,
or co
mbin
atio
n o
f th
e fo
llow
ing tec
hniq
ues
16
www.stringtechnologies.net
www.unistring.com
VL
SI
foru
m�FPG
As
�CPLD
s
�usi
ng A
SIC
cel
l libra
ries
�G
ate
Arr
ays
Sem
i custom VLSI Synthesis (or)
(part of Back end Design)
In sem
i cu
stom
VLSI des
ign sty
le the
required
logic
(w
hic
h is in
suitab
le form
) ca
n b
e sy
nth
esiz
ed for an
y o
ne
of th
e fo
llow
ing
dev
ices
.
PLD
synth
esis
ASIC
synth
esis
Struct
ure
d A
SIC
synth
esis
17
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VL
SI
foru
m
RTL sim
ulation (front end)Tools
Model
sim
M
ento
r G
raphic
s
VCS
Synopsy
s
NCSim
Cad
ence
Max
+Plu
s II sim
ula
tor
Alter
a
Xilin
x S
imula
tor
Xilin
x
synthesis (back end)tools
DC (des
ign c
om
piler
) Synopsy
s(A
SIC
)
PK
S (physica
lly k
now
ledgab
lesy
nth
esis)
Cad
ence
(A
SIC
)
Synplify
Pro
Synplici
ty(F
PG
A)
Xilin
x S
ynth
esis tec
hnolo
gy (X
ST)
Xilin
x(F
PG
A)
Alter
asy
nth
esis tool
Alter
a(F
PG
A)
Leo
nar
doSpec
trum
Men
tor G
raphic
s (C
PLD
, FPG
A, or A
SIC
)
18
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VL
SI
foru
m
Than
k y
ou
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