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Dr. Bassam Jamil
Adopted from slides of the
textbook
Transistor Theory
and
DC Characteristics
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 2
Outline
Transistor Theory
– Channel Formation and operation Regions
– I-V Characteristics
– C-V Characteristics
• Gate and Diffusion Capacitance
Nonideal characteristics
DC Response
– DC Response
– Logic Levels and Noise Margins
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 3
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 4
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
MOS Device Channel Formation
Gate and body form MOS
capacitor
Operating modes
– Accumulation
– Depletion
– Inversion
(b)
+-
0 < Vg < Vt
depletion region
(c)
+-
Vg > Vt
depletion region
inversion region
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 5
Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 6
nMOS Cutoff
No channel
Ids ≈ 0
+-
Vgs
= 0
n+ n+
+-
Vgd
p-type body
b
g
s d
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 7
nMOS Linear
Channel forms
Current flows from d to s
– e- from s to d
Ids increases with Vds
Similar to linear resistor
+-
Vgs
> Vt
n+ n+
+-
Vgd
= Vgs
+-
Vgs
> Vt
n+ n+
+-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 8
nMOS Saturation
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 9
I-V Characteristics
In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 10
Long Channel I-V
MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, eox
= 3.9)
polysilicon
gate
Cox = eox / tox
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Long Channel I-V
3: CMOS Transistor Theory 11
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 12
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 13
nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
Shockley 1st order transistor models
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 14
Example
The following is a 0.6 mm process:
– tox = 100 Å
– m = 350 cm2/V*s
– Vt = 0.7 V
Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 l
14
2
8
3.9 8.85 10350 120 μA/V
100 10ox
W W WC
L L L m
0 1 2 3 4 50
0.5
1
1.5
2
2.5
Vds
I ds (m
A)
Vgs
= 5
Vgs
= 4
Vgs
= 3
Vgs
= 2
Vgs
= 1
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Another Example
3: CMOS Transistor Theory 15
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 16
pMOS I-V
All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V•s in AMI 0.6 mm process
Thus pMOS must be wider to
provide same current
– In this class, assume
mn / mp = 2
-5 -4 -3 -2 -1 0-0.8
-0.6
-0.4
-0.2
0
I ds(m
A)
Vgs
= -5
Vgs
= -4
Vgs
= -3
Vgs
= -2
Vgs
= -1
Vds
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 17
Reverse
Voltages
Terminals
Change > to <
Positives to negatives
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 18
Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
– Creates channel charge necessary for operation
Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
CMOS VLSI Design CMOS VLSI Design 4th Ed.
MOS Device Capacitances
3: CMOS Transistor Theory 19
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 20
Gate Capacitance
Approximate channel as connected to source
Cgs = eoxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/mm
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, eox
= 3.9e0)
polysilicon
gate
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Gate Overlap Capacitance
3: CMOS Transistor Theory 21
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Approximation of Intrinsic Gate Capacitance
3: CMOS Transistor Theory 22
CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 23
Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Diffusion Cap Calculations
Total source diff capacitance
Source area (AS) = W D
Source Perimeter (PS) = W + 2D
3: CMOS Transistor Theory 24
* The side wall capacitance
abutting the channel is:
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Diffusion Cap Example
3: CMOS Transistor Theory 25
l = 25 nm
W = 4 l = 0.1mm
D = 5 l = 0.125mm
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Nonideal
Transistor
Theory
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 27
Outline
Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
Process and Environmental Variations
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 28
Ideal vs. Simulated nMOS I-V Plot
65 nm IBM process, VDD = 1.0 V
This is due to:
– Velocity Saturation
– Mobility depredation
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
1200
Vds
Ids (mA)
Vgs = 1.0
Vgs = 1.0
Vgs = 0.8
Vgs = 0.6
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Channel length modulation:
Saturation current increases
with Vds
Ion = 747 mA @
Vgs = Vds = VDD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 29
ON and OFF Current
Ion = Ids @ Vgs = Vds = VDD
– Saturation
Ioff = Ids @ Vgs = 0, Vds = VDD
– Cutoff
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
Vds
Ids (mA)
Vgs = 1.0
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Ion = 747 mA @
Vgs = Vds = VDD
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Nonideal Transistor Behavior:
High Field Effects
The saturation current increases less than quadratically with
increasing Vgs because of:
– velocity saturation
– mobility degradation.
At high lateral field strengths (Vds /L), carrier velocity ceases to
increase linearly with field strength. This is called velocity
saturation and results in lower Ids than expected at high Vds .
At high vertical field strengths (Vgs /tox ), the carriers scatter off
the oxide interface more often, slowing their progress. This
mobility degradation effect also leads to less current than
expected at high Vgs
3: CMOS Transistor Theory 30
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Nonideal Transistor Behavior: Other
Effects
The saturation current of the nonideal transistor increases
somewhat with Vds . This is caused by channel length
modulation, in which higher Vds increases the size of the
depletion region around the drain and thus effectively shortens
the channel.
There are other fields in the transistor have some effect on the
channel, effectively modifying the threshold voltage.
– Increasing the potential between the source and body
raises the threshold through the body effect.
– Increasing the drain voltage lowers the threshold through
drain-induced barrier lowering.
– Increasing the channel length raises the threshold through
the short channel effect.
3: CMOS Transistor Theory 31
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Nonideal Transistor Behavior: Leakage &
Temperature
Sources of leakage result in current flow in nominally OFF transistors:
– Subthreshold conduction: when Vgs < Vt , the current drops off exponentially
rather than abruptly becoming zero.
– Gate leakage: The current into the gate Ig is ideally 0. However, as the
thickness of gate oxides reduces to only a small number of atomic layers,
electrons tunnel through the gate, causing some gate leakage current.
– Diffusion leakage: The source and drain diffusions are typically reverse-biased
diodes and also experience junction leakage into the substrate or well.
Both mobility and threshold voltage decrease with rising temperature. The
mobility effect tends to dominate for strongly ON transistors, resulting in
lower Ids at high temperature. The threshold effect is most important for
OFF transistors, resulting in higher leakage current at high temperature. In
summary, MOS characteristics degrade with temperature.
3: CMOS Transistor Theory 32
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 33
Temperature Sensitivity
Increasing temperature
– Reduces mobility
– Reduces Vt
Vgs
dsI
increasing
temperature
The mobility effect tends to dominate for strongly ON transistors, resulting in lower
Ids at high temperature. The threshold effect is most important for OFF transistors,
resulting in higher leakage current at high temperature.
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 34
Electric Fields Effects
Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel Evert
Lateral electric field: Elat = Vds / L
– Accelerates carriers from drain to source
– Long channel: v = mElat
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 35
Mobility Degradation
High Evert effectively reduces mobility
– Collisions with oxide interface
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 36
Velocity Saturation
At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Better model
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 37
Vel Sat I-V Effects
Ideal transistor ON current increases with VDD2
Velocity-saturated ON current increases with VDD
Real transistors are partially velocity saturated
– Approximate with a-power law model
– Ids VDDa
– 1 < a < 2 determined empirically (≈ 1.3 for 65 nm)
2
2
ox2 2
gs t
ds gs t
V VWI C V V
L
m
ox maxds gs tI C W V V v
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 38
a-Power Model
0 cutoff
linear
saturation
gs t
dsds dsat ds dsat
dsat
dsat ds dsat
V V
VI I V V
V
I V V
/ 2
2dsat c gs t
dsat v gs t
I P V V
V P V V
a
a
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 39
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
l = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
n
+
p
GateSource Drain
bulk Si
n
+
VDDGND VDD
GND
L
Leff
Depletion Region
Width: Ld
2
12
ds gs t dsI V V V
l
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 40
Threshold Voltage Effects
Vt is Vgs for which the channel starts to invert
Ideal models assumed Vt is constant
Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 41
Body Effect
Body is a fourth transistor terminal
Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
fs = surface potential at threshold
– Depends on doping level NA
– And intrinsic carrier concentration ni
g = body effect coefficient
0t t s sb sV V Vg f f
2 ln As T
i
Nv
nf
sioxsi
ox ox
2q2q A
A
NtN
C
eg e
e
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 42
Body Effect Cont.
For small source-to-body voltage, treat as linear
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Body Effect Example
3: CMOS Transistor Theory 43
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 44
DIBL
Electric field from drain affects channel
More pronounced in small transistors where the drain is closer
to the channel
Drain-Induced Barrier Lowering
– Drain voltage also affect Vt
High drain voltage causes current to increase.
ttdsVVV
t t dsV V V
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 45
Short Channel Effect
In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes Vt a function of channel length
Short channel effect: Vt increases with L
– Some processes exhibit a reverse short channel
effect in which Vt decreases with L
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 46
Leakage
What about current in cutoff?
Simulated results
What differs?
– Current doesn’t
go to 0 in cutoff
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 47
Leakage Sources
Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
Gate leakage
– Tunneling through ultrathin gate dielectric
Junction leakage
– Reverse-biased PN junction diode current
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 48
Subthreshold Leakage
Subthreshold leakage exponential with Vgs
n is process dependent
– typically 1.3-1.7
Rewrite relative to Ioff on log scale
S ≈ 100 mV/decade @ room temperature
0
0e 1 e
gs t ds sb ds
T T
V V V k V V
nv v
ds dsI I
g
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 49
Gate Leakage
Carriers tunnel thorough very thin gate oxides
Exponentially sensitive to tox and VDD
– A and B are tech constants
– Greater for electrons
• So nMOS gates leak more
Negligible for older processes (tox > 20 Å)
Critically important at 65 nm and below (tox ≈ 10.5 Å)
From
[Song01]
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Junction Leakage
Reverse-biased p-n junctions have some leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)
n well
n+n+ n+p+p+p+
p substrate
CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 51
Diode Leakage
Reverse-biased p-n junctions have some leakage
At any significant negative diode voltage, ID = -Is
Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/mm2 (negligible)
e 1D
T
V
v
D SI I
CMOS VLSI Design CMOS VLSI Design 4th Ed.
DC
Characteristics
Dr. Bassam Jamil
Adopted from slides of the
textbook
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 53
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 54
Pass Transistors
We have assumed source is grounded
What if source > 0?
– e.g. pass transistor passing VDD
Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
Transmission gates are needed to pass both 0 and 1
VDD
VDD
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 55
Pass Transistor Ckts
VDD
VDDVs = VDD-Vtn
VSS
Vs = |Vtp|
VDD
VDD-Vtn VDD-Vtn
VDD-Vtn
VDD
VDD VDD VDD
VDD
VDD-Vtn
VDD-2Vtn
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 56
DC Response
DC Response: Vout vs. Vin for a gate
Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
– In between, Vout depends on
transistor size and current
– By KCL, must settle such that
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
Idsn
Idsp
Vout
VDD
Vin
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 57
pMOS Operation
Idsn
IdspVout
VDD
Vin
For PMOS: Vtp < 0
Vgsp = Vin – VDD , Vdsp = Vout – VDD
For NMOS: Vgsp = Vin , Vdsp =Vout – VDD
CMOS VLSI Design CMOS VLSI Design 4th Ed.
DC Characteristic
3: CMOS Transistor Theory 58
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 59
Operating Regions
Revisit transistor operating regions
Define input threshold (Vinv) as when
Vinv=Vin=Vout
CV
out
0
Vin
VDD
VDD
A B
DE
Vtn
VDD
/2 VDD
+Vtp
Vout
VDD
Vin
CMOS VLSI Design CMOS VLSI Design 4th Ed.
Calculate Vinv
4: Nonideal Transistor Theory 60
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 61
Beta Ratio
If p / n 1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter
Vout
0
Vin
VDD
VDD
0.5
12
10p
n
0.1p
n
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 62
Noise Margins
How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
CMOS VLSI Design CMOS VLSI Design 4th Ed. 5: DC and Transient Response 63
VDD
Vin
Vout
VOH
VDD
VOL
VIL
VIH
Vtn
Unity Gain Points
Slope = -1
VDD
-
|Vtp|
p/
n > 1
Vin
Vout
0
Logic Levels
To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Recommended