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Victor Moroz
September 9, 2016
Semicon Taiwan 2016
Transistor and Logic Design
for 5nm Technology Node
© 2016 Synopsys, Inc. 2
Outline
© 2016 Synopsys, Inc. 3
Outline
© 2016 Synopsys, Inc. 4
Why Scaling?
When What scales? When does it end?
1965 Moore’s Law (Fairchild):
Double transistor density every couple of years
• By 2043, there will be 1 atom per transistor
• But you can go up (3D IC)
• Great for planning and aligning the industry
1999
Claasen’s Law (Philips CEO):
Usefulness = log(Technology), or:
Technology = exp(Usefulness)
Forever?
2010
Koomey’s Law (Stanford Professor):
"at a fixed computing load, the amount of battery you need will fall by a factor of two every year and a half.“
• By the second law of thermodynamics and Landauer's principle, irreversible computing cannot continue to be made more energy efficient forever. As of 2011, computers have a computing efficiency of about 0.00001%. The Landauer bound will be reached in 2048. Thus, after 2048, the law could no longer hold.
• With reversible computing, however, Landauer's principle is not applicable. With reversible computing, though, computational efficiency is still bounded by the Margolus–Levitin theorem. By the theorem, Koomey's law has the potential to be valid for about 125 years.
© 2016 Synopsys, Inc. 5
Transistor Scaling Trend
Node, nm CPP, nm MP, nm
14 90 64
10 64 45
7 54 38
5 44 32
3.5 32 24
Industry scaling roadmap
Source: Scotten Jones, Semicon West 2016
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15
Min
imu
m p
itch
, n
m
Technology node, nm
Moore’s law
Industry
CPP
MP
CPP is Contacted Poly Pitch, a.k.a. Gate Pitch
MP is Metal Pitch
Scaling from 14nm to
10nm is on track
Scaling beyond10nm
is slower than 0.7x
Is that a
problem?
© 2016 Synopsys, Inc. 6
Logic Area Scaling Factors Besides Transistors
9
7.5
6
5 5
0
2
4
6
8
10
14 10 7 5 3.5
Cell
heig
ht
in m
eta
l tr
acks
Technology node, nm
0
1
2
14 10 7 5 3.5
Isola
tion w
idth
in C
PP
pitches
Technology node, nm
Fin depopulation
enables cell height
reduction
SDB DDB IG
SDB is Single Diffusion Break
DDB is Double Diffusion Break
IG is Isolating Gates
© 2016 Synopsys, Inc. 7
Logic Area Scaling Trend
0
20
40
60
80
100
0 5 10 15
Min
imum
pitch,
nm
Technology node, nm
9 7.5
6 5 5
0
2
4
6
8
10
14 10 7 5 3.5
Cell
heig
ht
Technology node, nm
0
1
2
14 10 7 5 3.5
Isola
tion w
idth
Technology node, …
0.01
0.1
1
0 5 10 15
Logic
cell
are
a w
.r.t.
14nm
Technology node, nm
Technology Scaling Roadmap
Logic area scaling
CPP*MP scaling
Moore's law
Pretty much on
track!
Pitch scaling Cell height Isolation width
© 2016 Synopsys, Inc. 8
Outline
© 2016 Synopsys, Inc. 9
9 Track Tall, 2 Fins 9 Track Tall, 1 Fin 6 Track Tall, Rotated Fins
3nm 2-NAND Cell: Design Choices
GP = 32nm MP = 24nm FP = 18nm
GP = 2 * MP FP = 2 * MP MP = 24nm
GP = 32nm MP = 24nm
fins
gates
contacts
90o rotated fins Relaxed gate pitch More stress
Rotate the fins
© 2016 Synopsys, Inc. 10
Proposed DTCO: Pre-Si PowerPerformanceArea Evaluation
GDS: Maxwell
or Laker
Process T Time Etch
Process1 480 C 25 min 12 nm
Process2 475 C 23 min 13 nm
DR DR
1
DR
2
Fin
pitch
24
nm
22
nm
MG
ext.
15
nm
15
nm
Spac
er
7
nm
6
nm
Litho:
Sentaurus
3D structure:
Process
Explorer
Switching
behavior:
TCAD
Design rule
bad
bad
good
Design rule P
rocess c
onditio
n
Design rule
Pro
cess c
onditio
n
© 2016 Synopsys, Inc. 11
3D Library Cell in Process Explorer
M2
M1
M0
Transistors
© 2016 Synopsys, Inc. 12
Power-Performance-Area Evaluation in TCAD
• Transient analysis of the switching behavior in Sentaurus-Device
• Time delay is the averaged pull-up and pull-down delays
• Rigorous current flow analysis in the 3D structure
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 2E-11 4E-11 6E-11 8E-11 1E-10
Po
ten
tia
l, V
Time, s
Input
Low_ROutput
3D current crowding
© 2016 Synopsys, Inc. 13
0
0.5
1
1.5
2
0 5 10 15 20 25
En
erg
y p
er
sw
itch
, f
J
Switching delay, ps
2 Fins
1 Fin
Rotated Fin
3nm Technology Evaluation: PowerPerformanceArea @TCAD
Load: Fan-out of 2 plus 70 pitches long BEOL wire
3D current flow in TCAD
2-NAND logic cell
2 Fins: Pin capacitance = 0.796 fF
© 2016 Synopsys, Inc. 14
0
0.5
1
1.5
2
0 5 10 15 20 25
En
erg
y p
er
sw
itch
, f
J
Switching delay, ps
2 Fins
1 Fin
Rotated Fin
3nm Technology Evaluation: PowerPerformanceArea @TCAD
Load: Fan-out of 2 plus 70 pitches long BEOL wire
3D current flow in TCAD
2-NAND logic cell
30%
2 Fins: Pin capacitance = 0.796 fF
1 Fin: Pin capacitance = 0.495 fF Ion: -50% Cpin: -40%
© 2016 Synopsys, Inc. 15
0
0.5
1
1.5
2
0 5 10 15 20 25
En
erg
y p
er
sw
itch
, f
J
Switching delay, ps
2 Fins
1 Fin
Rotated Fin
3nm Technology Evaluation: PowerPerformanceArea @TCAD
Load: Fan-out of 2 plus 70 pitches long BEOL wire
3D current flow in TCAD
2-NAND logic cell
30%
38%
2 Fins: Pin capacitance = 0.796 fF
1 Fin: Pin capacitance = 0.495 fF Ion: -50% Cpin: -40%
Rotated Fin: Pin capacitance = 0.432 fF Ion: -40% Cpin: -45%
© 2016 Synopsys, Inc. 16
Outline
© 2016 Synopsys, Inc. 17
5nm Nanowire Design Same layout
(5nm 1x inverter)
© 2016 Synopsys, Inc. 18
5nm Nanowire Design Same layout
(5nm 1x inverter)
Si
Si
Si
Si
SiGe
SiGe
SiGe
Si
Si
Si
Si
SiGe
SiGe
SiGe
© 2016 Synopsys, Inc. 19
5nm Nanowire Design Same layout
(5nm 1x inverter)
No
n-G
AA
Na
no
-sh
eet
GA
A N
an
o-s
heet
© 2016 Synopsys, Inc. 20
5nm Nanowire Design Same layout
(5nm 1x inverter)
No
n-G
AA
Na
no
-sh
eet
GA
A N
an
o-s
heet P
ote
ntial Gate
Gate
Gate
Gate
D S
Gate HK
On
-Curr
ent
density
© 2016 Synopsys, Inc. 21
5nm Nanowire Design Same layout
(5nm 1x inverter)
No
n-G
AA
Na
no
-sh
eet
GA
A N
an
o-s
heet P
ote
ntial Gate
Gate
Gate
Gate
D S
Current
density
Gate HK
HK
Gate
On
-Curr
ent
density
© 2016 Synopsys, Inc. 22
5nm Nanowire Design Same layout
(5nm 1x inverter)
No
n-G
AA
Na
no
-sh
eet
GA
A N
an
o-s
heet
On
-Curr
ent
density
Pote
ntial Gate
Gate
Gate
Gate
D S
Current
density
30% lower Ion
But 10%
lower CMOL
Gate HK
HK
Gate
© 2016 Synopsys, Inc. 23
Outline
© 2016 Synopsys, Inc. 24
Why Variability is Important
#
Ion
• Technology A
Design spec:
Nominal – 3s
Nominal
Performance A • What matters is
nominal – 3s
• Therefore variability affects chip area
© 2016 Synopsys, Inc. 25
Why Variability is Important
#
Ion
• Technology A
• Technology B
Nominal Design spec:
Nominal – 3s
Nominal
Performance B
Performance A • What matters is
nominal – 3s
• Therefore variability affects chip area
• There is no “good enough” variability – the target is zero!
© 2016 Synopsys, Inc. 26
Fin Depopulation Adds Pressure to Variability Scaling
14nm
10nm
7nm
5nm
sVt ~ 1 / sqrt(# of fins)
© 2016 Synopsys, Inc. 27
Fin Depopulation Adds Pressure to Variability Scaling
14nm
10nm
7nm
5nm
sVt ~ 1 / sqrt(# of fins)
• Other considerations:
• Electromigration
• Power density
• Fin pitch
© 2016 Synopsys, Inc. 28
Planar to FinFET Transition
• FinFETs improve variability
• Planar MOSFETs suffered from RDF
• FinFETs are insensitive to channel doping RDF
0
10
20
30
40
50
60
110100
Sig
ma V
t, m
V
Technology node, nm
Variability Evolution Total
Planar FinFET NW
130
22
14 7
10 65
Measured data for low Vt process from S. Natarajan et al., IEDM 2014
© 2016 Synopsys, Inc. 29
HKMG Grains Introduce Gate Workfunction Variation
• At 10nm and 7nm nodes, HKMG becomes the dominant variability mechanism
• Introduction of amorphous MG at 7nm would solve this issue
0
10
20
30
40
50
60
110100
Sig
ma V
t, m
V
Technology node, nm
Variability Evolution Total
HKMG
7
10
© 2016 Synopsys, Inc. 30
Geometry
• Planar MOSFETs are insensitive to geometry
• FinFETs and NW are more sensitive to geometry
• NW are less sensitive to L than FinFET, but more sensitive to W
• This data is based on 1 geometry sigma staying at 5% of CD 0
10
20
30
40
50
60
110100
Sig
ma V
t, m
V
Technology node, nm
Variability Evolution Total
HKMG
Geometry
5 3
2
© 2016 Synopsys, Inc. 31
RDF (Random Dopant Fluctuations)
• Planar MOSFETs suffered from RDF
• FinFETs are insensitive to channel doping RDF
0
10
20
30
40
50
60
110100
Sig
ma V
t, m
V
Technology node, nm
Variability Evolution Total
HKMG
RDF
Geometry
© 2016 Synopsys, Inc. 32
FinFET to Nanowire Transition: Counting Particles
• NW variability depends on how many S/D dopants get into the channel
0
10
20
30
40
50
60
110100
Sig
ma V
t, m
V
Technology node, nm
Variability Evolution Total
HKMG
RDF
Geometry
KMC
0 dopants
1 dopant
2
3
S D
© 2016 Synopsys, Inc. 33
Outline
© 2016 Synopsys, Inc. 34
Observation in a Recent Nanowire Research Paper
Nanowire Joule self-heating due
to high current density when
operating at higher than normal
Vdd
C.-H. Jeon et al., IEEE Trans. Electron Dev., v. 63, n. 6, pp. 2288 – 2292, (2016)
Driving strength increases after
Joule self-heating, but eventually
nanowire breaks down
With longer Joule heating, on-state
current increases, and subthreshold
slope degrades, which is a signature
of channel length getting shorter
© 2016 Synopsys, Inc. 35
Repairing Slow Transistors/Gates Removes Design Margin
#
Ion
• As-manufactured
• Repaired
Nominal
Design spec:
Nominal – 3s
Conventional spec
• Selectively repair transistors that are in critical paths
• What matters is nominal – 3s
• For 14nm FinFETs, 3s = ~30%
• For 5nm Nanowires, 3s = ~50%
Spec for repaired chip
© 2016 Synopsys, Inc. 36
As-Manufactured Distribution of Transistor Properties O
ff-s
tate
curr
ent
On-state current
• As-manufactured
• This is a typical sample of transistors
• Individual Ion/Ioff points are stretched along the Ion/Ioff trade-off trend for a particular technology
Fast Slow
© 2016 Synopsys, Inc. 37
Repairing Slow Part of Transistor Population O
ff-s
tate
curr
ent
On-state current
• As-manufactured
• Slow -> Repaired • Repair can be applied selectively,
for example, only to critical paths
• Over time, some of the transistors will drift towards lower left corner due to NBTI and HCI degradation mechanisms that increase Vt
• Then, self-heating repair can be applied again to speed up such transistors
Fast
Average
Slow
© 2016 Synopsys, Inc. 38
Summary
• Combination of CPP and MP pitch scaling and library cell design evolution provides on-track logic area scaling at least down to 3nm design rules
• 5nm and 3nm technologies have multiple trade-offs in transistor architecture and MOL RC that require holistic DTCO engineering
• Ideal variability is zero, and fin depopulation adds even more pressure
• Nanowire transistors can be selectively repaired to eliminate local variability
9 7.5 6
5 5
02468
10
14 10 7 5 3.5
Cell
he
igh
t
Technology node, nm
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