The PFIT Project WW07'14

INTEL CONFIDENTIAL1

Intel CorporationPlatform Engineering GroupNick KleinJan 30, 2014

The PFIT Project WW07'14

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

The PFIT Project

Agenda• Objective• Strategy• Timeline

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

The PFIT Project key objectives

• Apply LEAN principles to Advanced FI• Define equipment required to optimize automated Advanced

FI test throughput time (TPT)• Development of industry standard automated Advanced FI

equipment to significantly reduce FI throughput time and expense.

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

Reasons for the PFIT project

• Advanced FI methodologies currently rely on equipment intended for functional FI.

• Functional and Advanced FI equipment needs differ significantly, in that testing is often performed on completely non-functional parts, and require much higher test currents and dual-polarity voltages.

• This project extends the capability of Advanced FI across all product lines to significantly decrease TPT.

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

The PFIT Project

Agenda• Objective• Strategy• Timeline

6

Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

The PFIT Project strategy• Identify strategies to enhance existing functional FI• Determine essential minimum equipment• Curve tracing• Latch up• High-current Bin8

• Develop TIU• Universal carrier interface• Daughter board per product

• Develop automated LabView test procedures• Mostly universal across product lines

• Document entire system for copy-exact to other sites

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

The PFIT Project

Agenda• Objective• Strategy• Timeline

8

Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

The PFIT Project timeline

Q1’14 Q2’14 Q3’14WW 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Spec writing Board design

and Software Design

Harness Design Boards in house

Pre-Power On testing.

Validation

Phase 2Phase 1 Completion

Demos and implementation

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

Back up

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

Backplane block diagram

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

Family board block diagram

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Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries.  Other names and brands may be claimed as the property of others.  All products, dates, and figures

are preliminary and are subject to change without any notice.  Copyright © 2012, Intel Corporation.Reference Number: XXXXXX Intel Confidential Revision: 1.0

Project File