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The HIR - Packaging, Heterogeneous Integration, and High Performance
Computing
W. Dale Becker, IBM Corporation
Abstract - The Heterogeneous Integration Roadmap (HIR) was initially released in 2019
with 22 working groups covering the broad areas of packaging and packaging development. A
comprehensive view of the heterogeneous integration of separately manufactured components
into a higher-level assembly is provided in this roadmap and is actively updated with a 2020
edition available and a 2021 edition nearing completion. This talk will give an overview of the HIR
and how that supports how high-performance computing systems and data centers use
heterogeneous integration and the roadmap of key elements that this working group has
identified. EPEPS has and will continue to cover the detail of electrical design, modeling, and
simulation of the components as well as the electrical challenges for assembly into full systems
and is a key resource for developing the roadmap.
Biography:
Dr. Dale Becker is the Chief Engineer of Electronic Packaging
Integration in IBM Systems, responsible for system packaging
architecture including the design of high-speed channels to enable
the computer system performance and the power distribution
networks. He currently chairs the IEEE EPS Technical Committee on
Electrical Modeling, Design, and Simulation and is a Senior Area
Editor for the Transactions on EPS. Dale co-chairs the HIR High-
Performance Computing & Data Center Technical Working Group. He
has been elected an IEEE Fellow.
Interposer Analysis: Challenges and Solutions for Efficient 3D EM Extraction
Amir A. Asif, Cadence
Abstract - Semiconductor packaging has been evolving over past decades, and recently
we are seeing how the industry is transitioning toward chiplet based architecture where the chips
are in a closer proximity on an interposer. Basically, with the introduction and maturity of
through-Silicon via techniques, the foundries are now taking part in the role that was traditionally
performed by traditional packaging. This allows convenience for die-to-die communication
utilizing a much efficient route, compared to the traditional arrangement of ‘die-package-PCB-
package-die’. Now, it is possible to the place a CPU and memories on top of the same interposer.
The task of simulating Interposer comes with its own unique set of challenges. The absence of
solid planes, aspect ratio of routings, thousands of intricate metal layouts, etc. present a special
scenario for it extraction. The high operating speed (such as PAM4) and proximity of routings
demand extraction with an accurate analysis method based on finite element method (FEM).
Being very dense and intricate, interposers can push 3D EM solvers in terms of capacity,
computing resources and performance. In this tutorial, some challenges would be discussed for
such scenarios and corresponding solutions with Clarity 3D EM solver will be presented with
example designs.
Topical Coverage of tutorial:
• Overview of packaging evolution and interposer architecture
• Challenges of 3D EM simulation: capacity, resources and performance.
• Simulation for signal integrity (SI) and power aware SI extraction.
• Running 3D EM simulation with example design with Clarity 3D solver: layout translation to
project, setup, computing resource allocation, parallelization and result inspection with help
of Clarity 3D EM Solver
• Brief overview of further analysis with EM results.
Biography:
Amir Asif is working as Principal Product Engineer in Multi-domain
System Analysis group of Cadence Design Systems, Inc. He focuses
on electromagnetic model extraction with various Cadence tools
using Finite Element Method (FEM), Method of Moment (MoM) and
Hybrid Solvers: Clarity, PowerSI, EMX, etc. Currently, he is involved
with simulating PCB, packages and interposers and extracting their
accurate models.
Dr. Asif received his PhD in Electrical Engineering from Clemson
University, SC, USA, and Bachelor in Electrical & Electronic
Engineering from Bangladesh University of Engineering and
Technology (BUET), Bangladesh.
Addressing EM Simulation Challenges for IC-Package-Board Problems
Feng Ling, Xpeedic Technology Inc.
Jonatan Aronsson, CEMWorks Inc.
Abstract - Electromagnetic (EM) simulation becomes indispensable in designing today’s
electronic systems. High-frequency links and high-speed interfaces are ubiquitous from IC,
package, to board, which all require accurate EM simulation to achieve signal integrity, power
integrity, and EMC. Increasing demand for accurate, fast, and scalable EM simulations drives the
development of EM simulation technologies. Advanced process and advanced packaging
technologies pose new challenges to EM solver development. In this talk, we will give an overview
of EM solver technologies adopted in today’s IC, package, and board designs including the
Method of Moments (MoM) and the Finite Element Method (FEM). Various acceleration
techniques for the MoM solver will be discussed. Their performance will be compared with the
real-world IC, package, and board problems.
Biographies:
Feng Ling is the Founder and CEO of Xpeedic Technology, a
leading EDA solution provider for IC-package-system designs. His
twenty years’ industrial career spans from Motorola to EDA
startups Neolinear (acquired by Cadence) and Physware
(acquired by Mentor Graphics). In 2009, he founded Xpeedic
Technology, continuing the efforts to bring novel EDA solutions
to the semiconductor industry. Dr. Ling received his Ph.D. degree
in electrical engineering from the University of Illinois at Urbana-
Champaign (UIUC) in 2000.
Jonatan Aronsson is the Founder and President CEMWorks Inc.,
an innovator in specialized EM simulation software for
applications such as IC packaging, embedded antennas,
metasurfaces, and modeling of 5G deployments. Before
founding CEMWorks, Dr. Aronsson worked as an HPC scientific
developer and technical lead at the University of Waterloo and
Compute Canada supercomputing centers. Dr. Aronsson is an
EM expert with a Ph.D. degree in Electrical Engineering
(University of Manitoba) and an M.Sc. in Engineering Physics
(Lund Institute of Technology).
Tutorial on Electrical Characterization and Measurement for Electronic
Packaging
Heidi Barnes, Keysight Technologies
Michael Hill, Intel Corporation
Wui-Weng Wong, AMD
Abstract - This tutorial will explore industry methods used for characterizing and
measuring electronic packages for the purpose of improving the state-of-the art in simulation
and modeling. The IEEE EPS Society’s Technical Committee on Electrical Design, Modeling and
Simulation (EDMS) has initiated a publicly available Suite of Packaging Benchmarks for the
verification, validation, and performance of electronic packages. This effort has highlighted the
challenges in providing accurate DC to 50GHz material characterization and measured
performance data to enable simulation to measurement correlation. Specific topics will include
impact of fixturing on signal integrity probing measurements, challenges with low impedance
power integrity probing measurements, and understanding the accuracy of material
characterization methods for electronic packages.
Biographies:
Heidi Barnes is a Senior Application Engineer for High-Speed Digital
applications in the EEsof EDA Group of Keysight Technologies. Her recent
activities include the application of electromagnetic, transient, and channel
simulators to solve signal and power integrity challenges. Author of over 20
papers on SI and PI and recipient of the DesignCon 2017 Engineer of the Year.
Experience includes 6 years designing ATE test fixtures for Verigy, 6 years in
RF/Microwave microcircuit packaging for Agilent Technologies, and 10 years
with NASA in the aerospace industry. Heidi graduated from the California Institute of Technology
in 1986 with a bachelor’s degree in electrical engineering. She has been with Keysight EEsof since
2012.
Michael J. Hill is a Principal Engineer at Intel Corporation in Chandler,
Arizona. He has been with the Electrical Core Competency group since
2002. His work in this area includes the development of new tools and
techniques to allow precise characterization of substrate electrical
performance metrics spanning power delivery, highspeed I/O and RF
applications. Much of his recent work has focused on metrologies for
characterizing high speed integrated voltage regulators. In addition to his
work in Power Delivery, Michael is also responsible for developing characterization methods for
package material sets spanning DC to 110GHz. Prior to joining Intel, Michael was involved in
development of high density active microwave phased arrays for medical applications, and later
in the development of wireless networking hardware and characterization systems utilizing
spherical near-field scanning techniques. Michael is a senior member of the IEEE, has authored
more than 30 peer reviewed publications, holds 9 patents and is a member of Tau Beta Pi and
Etta Kappa Nu. He holds B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University
of Arizona. Michael can be reached by email at: Michael.j.hill@intel.com.
Wui-Weng Wong is a Senior Manager in AMD Packaging Group. He leads a
SI/PI team in Singapore. His recent works included simulation and
characterization on flip chip packages and printed circuit boards for high-
speed digital applications. Mr. Wong has been actively participating in IEEE
Electronics Packaging Technology Conference since 2015. He holds M.S.E.
degree in Electrical Engineering from Arizona State University.
Analysis and optimization of SerDes interfaces running at 100Gbps per lane
Cristian Filip & Daniel De Araujo, Siemens EDA
Abstract - The industry demand for increased bandwidth has led to the development of
protocol specifications defining the requirements of interfaces running at 100Gbps per lane. The
IEEE802.3ck and OIF CEI-112G specifications are addressing the challenges and intricacies of such
interfaces. A special case is that of Chip-to-Module (C2M) operating modes with a complex
methodology for compliance testing. While their 50Gps predecessors were using an eye diagram-
based method, the new interfaces include Channel Operating Margin (COM) as informative
Figure of Merit (FOM). This presentation will highlight the most important aspects of the
compliance testing methodology and practical considerations for system level optimization.
Biographies:
Cristian Filip joined Siemens EDA in 2014 as a product architect. His
interest includes high-speed serial link design, modeling and simulations of
DDR memory interfaces as well as power integrity. Prior to joining
Siemens, Cristian was a Senior Hardware Engineer specializing in signal
and power integrity at General Dynamics Canada in Ottawa. Cristian holds
a M. Eng. In Electronics and Telecommunications from the Polytechnic
University, Timisoara, Romania and is a member of Professional Engineers
Ontario. He has co-authored several papers, among them ”BER- and COM-
Way of Channel-Compliance Evaluation: What are the Sources of
Differences?” and “Efficient Sensitivity-Aware Assessment of High-Speed
Links Using PCE and Implications for COM” that won the DesignCon Best
Paper Award in 2016 and 2018 respectively.
Daniel de Araujo has 24 years of experience in board, package, and chip
design, simulation, and validation. He has a B.S.E.E from Michigan State
University and obtained a Masters in Computer Engineering from North
Carolina State University in 2000. Daniel has worked at IBM PC Company,
IBM Server Division, joined Ansoft Corporation as an application engineer
in 2006 and Physware in 2010 as Director of Applications. Mentor Graphics
acquired Nimbic in 2014 and Siemens acquired Mentor in 2016. Daniel has
14 patents issued, 11 filed, nine patent disclosure publications and 77 peer-
reviewed publications in international IEEE conference proceedings,
transactions, journals, and books.
Package Design Considerations for Enabling High Volume Manufacturing Tests
Michael E. Ryan, Intel Corporation
Abstract - In the rush to bring innovative products to market, design for testability is often
overlooked. The market success of groundbreaking semiconductor products can be easily
derailed if the product’s design choices result in diminished validation and/or test coverage;
allowing defects to escape to customers. Test escapes can delay product launches, lead to missed
opportunities to maximize customer adoption, and cause significant damage to the company’s
brand. Take for example, the Intel Pentium FDIV bug in 1994 that ultimately led to a product
recall and cost the company hundreds of millions of dollars. Although this bug was not related
to package design, it’s important to note that a gap in test coverage allowed this bug to escape.
The test escape led to the implementation of new test methods, new hardware capabilities and
a renewed commitment to always prioritize full feature test coverage. However, as product
operating speeds continue to increase, chipmakers can no longer rely solely on test hardware
performance improvements to stay ahead of product operating specifications. Package
optimization for test has become a critical test enabler.
This presentation describes why test enabling has historically been ignored in package
design and the relationship to traditional test hardware performance limitations. It will also
demonstrate that incorporating test enabling may be achieved without increasing package cost,
complexity, or schedule risk. Examples of package design choices will be described, and their
overall impact on test enabling will be demonstrated.
Biography:
Michael E Ryan is a Sr. Test R&D Technologist in the Sort/Test
Technology Development organization within Intel’s Technology and
Manufacturing Group. He is responsible for defining high speed I/O
test solutions for high volume manufacturing.
Mike joined Intel in 1996 as a Burn-in process development engineer
where he was responsible for transferring a new Test During Burn-in
(TDBI) process and hardware to Intel’s Asia test sites. In 1997 he was
recruited to join a newly created test development team responsible for
bring up Intel’s first System Level Test capability. In this role he led
the development and deployment of System Test for Intel’s Xeon server
product line. Mike went on to hold positions as a Signal Integrity
Engineer for Intel’s Embedded products division, and as an Electrical
Validation Engineer for Intel’s Internet of Things (IoT) products
division in the early 2000’s. However, realizing that his true calling was test development, he returned to STTD
in 2012, where he leverages his test, signal integrity and validation experience to drive Intel’s System Test high
speed I/O test enabling strategies and solutions.
Mike holds a bachelor’s degree in electronics engineering technology from Arizona State University. He resides
in Arizona with his wife and two children.
Analysis of Direct-to-Chip-Package 224G Channels
Michael Rowlands, Amphenol
Abstract - Achieving 224Gbps over copper interconnects presents multiple challenges.
Target metrics, including loss, reflections, loss deviation, and crosstalk, need to be met. This
presentation investigates key bump-to-bump passive copper channels for 224G transmission.
Key features that enable 224G include direct-to-package interconnects, which remove BGA and
PCB geometry, and OverPass structures, including twinax and IO panel connectors. Channels are
analyzed with metrics such as insertion loss, loss deviation, integrated crosstalk, and channel
operating margin. Both chip-to-chip and chip-to-module configurations are analyzed.
Biography:
Michael Rowlands is an SI Engineering Manager at Amphenol
designing 224G connectors. He specializes in signal integrity at
multi-gigahertz frequencies. He received a Bachelor's and
Master's degree in Electrical Engineering from MIT in 1998. In his
career, he’s worked on a variety of system components, inluding
cable assemblies, circuit boards, optical chips, chip packaging,
twin-axial cable, and connectors.
Packaging challenges for mobile and beyond, an industry perspective
Gerardo Romo Luevano & Joonsuk Park, Qualcomm Technologies Inc.
Abstract - Since smartphone was getting popularity 14 years ago, smartphone has been
the driving force in the technology migration. Due to the small form factor and sensitivity to the
power, migration to sub 5nm was accelerated. Now 5G made the demand for intelligent devices
(IoT) very high and autonomous vehicle within a reach. This presentation will discuss the unique
signal and power integrity challenges associated with different market segments. The
performance, package requirements, technical challenges, cost, etc. can vary significantly
depending on the targeted area of the package. For example, mobile devices require to have a
small foot-print to reserve more space for bigger battery and the slim designs put strong
constraints on their height; this naturally leads to tighter ball pitch constraints for the packages.
On the other hand, IoT packages need to be extremely cheap and those for automotive
applications require a longer life cycle and therefore a more rigid build. This presentation
discusses the general aspects of package development with emphasis on the signal and power
integrity tradeoffs and challenges primarily in the area of mobile, but briefly addresses compute,
IoT, Automotive and beyond.
Biographies:
Gerardo Romo L. obtained the Ph.D. degree in electrical engineering from
Carleton University, Ottawa, ON, in 2005. He has held positions as a SI/PI
Egineer at Intel Corporation and as an Application Engineer at CST of America.
He currently works as an SI/PI engineer at Qualcomm Technologies Inc. His
main interests are Signal/Power Integrity and computational
electromagnetics applied to high frequency problems.
Joonsuk Park received the B.S. degree from University of Michigan, Ann
Arbor, MI, in 1988 and M.S. degree from Columbia University, NYC, NY, in
1992. He worked at IBM EDA since 1989 to develop Package SI sign-off
vehicles such as simultaneous switching noise calculator (DELI), Geometric
Xtalk extractor (Gxtalk), Statistical Xtalk estimators (Sxtalk) to support
various server development projects. Later, he worked with IBM research
to develop High Speed SerDes simulation tool (HSSCDR).
In 2014, he joined QualComm Packaging team and worked with SerDes SI/PI
issues in various products and currently Principal Engineer/Manager in
charge of Package Electrical team and responsible for digital and RF package
extraction, simulation and sign-offs.
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