Team DC-HSBA

Robert BensonDavid Hover

Jonathan TatePaul Niewoonder

ROBERT BENSON

Primary GoalEmbedded Software Graphics Accelerator

Shader Unit Media-Centric Co-Processor High Floating-Point Computation Performance Graphical Computation

Complete Software Graphics Pipeline

HardwareCustom Multi-FPGA Development Board

Cyclone III FPGAsOutputs

VGA Port LEDs

Inputs 8-Directional Joysticks JTAG Programming Port

Hardware Block Diagram

Hardware DetailsAbdomen

Cyclone III (EP3C16Q240C8)DAC (ADV7123)Serial Programming Device (EPCS)JTAG Configuration Port

LegCyclone III (EP3C25E144C7)DDR SDRAM (512 MBit)Ports for GPIO

Hardware DetailsI/O Widgets

8 Directional JoystickRGB LEDs

Communication MethodsMemory – DDR SSTL_2Inter FPGA - LVDS

Hardware Power

Cost EstimateExpenses

Unit Cost Quantity ExtendedLobster

Leg FPGA $ 60 2 $ 120 Abdomen FPGA $ 30 1 $ 30 Memory $ 6 2 $ 12 Discrete $ 50 1 $ 50 Power $ 77 1 $ 77 I/O $ 40 1 $ 40 Board $ 70 1 $ 70

Total $ 399 Both Revisions $ 798

CrabLeg FPGA $ 60 4 $ 240 Abdomen FPGA $ 30 1 $ 30 Memory $ 6 4 $ 24 Discrete $ 70 1 $ 70 Power $ 109 1 $ 109 I/O $ 50 1 $ 50 Board $ 200 1 $ 200

Total 723 $ 723

Total Costs $1,521

Schematics?

Layout?

DAVID HOVER

SoftwareUser Application Software

Main User InterfaceBenchmarksDemosTetrisphere Clone

Graphics Pipeline SoftwareAssembler

Main MenuSee attached

Benchmarks & DemosBenchmarks

Matrix MultiplicationsMatrix-Vector MultiplicationsTranscendental Function Calculation

DemosRacecarBouncing BlobBuffaloBeach

Software Implementation“Game Loop”

Poll User InputUpdate “Game” StateRedraw Environment

OpenDC APISimilar To OpenGLSmaller Subset

Example OpenDC FunctionsState Manipulation

dcEnable()dcClear()dcFinish()

Matrix ManipulationdcMatrixMode()dcLoadIdentity()

Parameter ManipulationdcBindShader()dcBindTexture()dcUniform1f()

General Software Layout

Graphics Pipeline SoftwareHardware to

Software Abstraction

The Assembler - Flex Matches expressions Literal or regular expressions Can perform any action after a match The main task is to turn matches into

tokens for the upcoming parser

Flex (Cont.)Our Lexer has the following properties Matches all valid assembly commands Allows for comments, i.e, anything after a

semicolon is ignored Ignores all white space Is able to distinguish between arguments and

labels.

The Assembler – BisonInvoked after the lexerSends tokens through an annotated context-free

grammar.A context-free grammar, for example, has the

form of:stmts : stmt stmts | stmt ;

This is one of many definitions.This stores data as it parses

Bison (Cont.)The parser is general, all commands are

treated equallyValidity is checked per completed commandAfter completion, the parser passes the

finished data to be converted into a bitstream

JONATHAN TATE

System Logic DesignPrebuilt

SOPC BuilderMemory ControllersNIOS II Processor

CustomCachesLVDS to Avalon Interconnect BridgeShader Unit

Shader ALU

Shader Unit

Leg Shader Block

Shader Thread Scheduling

Cycle0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Thread 1 x Thread 2 x

Thread 3 x Thread 4 x

Thread 1 y Thread 2 y

Thread 3 y Thread 4 y

Thread 1 z Thread 2 z

Thread 3 z Thread 4 z

Thread 1 x

Shader Thread SchedulingCycle

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30Thread 1 x

Thread 2 x Thread 3 x

Thread 4 x Thread 1 y

Thread 2 y Thread 3 y

Thread 4 y Thread 1 z

Thread 2 z Thread 3 z

Thread 4 z Thread 1 w

Thread 2 w Thread 3 w

Thread 4 w Thread 1 x

PAUL NIEWOONDER

Arithmetic – Multiply-AddMultiply Unit

Arithmetic – Multiply-AddAdd Unit

Arithmetic – Inverse Square Rootfloat InvSqrt(float x){float xhalf = 0.5f * x;int i = *(int*)&x; i = 0x5f3759d5 - (i >> 1);x = *(float*)&i;x = x*(1.5f - xhalf*x*x); return x;

}

Arithmetic – DividerChained subtract and bit shiftRequires many LUTs

Full divide support would take up most of the available board space

Limited divide support (1 divide per sixteen cycles)

Case DesignPlexiglas substrateVentilation holesFan mount

Joystick control mountVGA output port

ScheduleID Task Name Duration Start Finish

1 Capstone Proj ect 104 days Mon 1/11/10 Sat 4/24/102 Board Design 104 days Mon 1/11/10 Sat 4/24/103 Lobster 82 days Mon 1/11/10 Fri 4/2/104 Leg Design 19 days Mon 1/11/10 Fri 1/29/108 Central Design 6 days Sun 1/31/10 Fri 2/5/10

12 Power Design 7 days Sat 2/6/10 Fri 2/12/10

13 Board Layout 20 days Sat 2/13/10 Thu 3/4/10

14 Revi sion 1 At Advanced Circuits 8 days Fri 3/5/10 Fri 3/12/10

15 Revi sion 1 Test ing and Revision 6 days Sat 3/13/10 Thu 3/18/10

16 Revi sion 2 At Advanced Circuits 8 days Fri 3/19/10 Fri 3/26/10

17 Revi sion 2 Test ing 7 days Sat 3/27/10 Fri 4/2/10

18 Crab 22 days Sat 4/3/10 Sat 4/24/1019 Design Expansi on 7 days Sat 4/3/10 Fri 4/9/10

20 Revi sion 1 At Advanced Circuits 8 days Sat 4/10/10 Sat 4/17/10

21 Revi sion 1 Test ing 7 days Sun 4/18/10 Sat 4/24/10

22 Softw are 98 days Mon 1/11/10 Sun 4/18/1023 Assembler 20 days Mon 1/11/10 Sat 1/30/10

24 Software Requi rements Specifi cati on 49 days Mon 1/11/10 Sun 2/28/10

25 Iteration 1 14 days Mon 3/1/10 Sun 3/14/1031 Iteration 2 21 days Mon 3/15/10 Sun 4/4/1034 Iteration 3 14 days Mon 4/5/10 Sun 4/18/1037 Logic Design 83 days Sun 1/17/10 Fri 4/9/1038 Micro Cache Design 7 days Sun 1/17/10 Sat 1/23/10

39 Shader Pipel ine 7 days Sun 2/14/10 Sat 2/20/10

40 Shader Control Unit 21 days Sun 2/21/10 Sat 3/13/10

41 Mult iply Add Uni t 20 days Sun 1/17/10 Fri 2/5/10

42 Excess Floating Point Uni ts 14 days Sun 2/7/10 Sat 2/20/10

43 Testi ng 1 7 days Sat 3/13/10 Fri 3/19/10

44 Revi sion 1 7 days Sat 3/20/10 Fri 3/26/10

45 Testi ng 2 7 days Sat 3/27/10 Fri 4/2/10

46 Revi sion 2 7 days Sat 4/3/10 Fri 4/9/10

47 PDR 1 day Tue 1/26/10 Tue 1/26/10

48 CDR 1 day Thu 2/25/10 Thu 2/25/10

49 Mil estone 1 1 day Tue 3/16/10 Tue 3/16/10

50 Mil estone 2 1 day Thu 4/15/10 Thu 4/15/10

51 Expo 1 day Thu 4/29/10 Thu 4/29/10

1/262/25

3/164/15

4/29

30 2 5 8 11 14 17 20 23 26 29 1 4 7 10 13 16 19 22 25 28 3 6 9 12 15 18 21 24 27 30 2 5 8 11 14 17 20 23 26 29 2 5 8December 2009 January 2010 February 2010 March 2010 April 2010 May 2010

Milestone DeliverablesMilestone 1

Revision 1 of Lobster FPGA BoardIteration 1 of the Software

Milestone 2Lobster FPGA BoardIteration 3 of the SoftwareAll Logic

Capstone ExpoCrab FPGA Board

Division of LaborJonathan Tate

System Logic Design

Shader ProgramsGraphics Pipeline

Control SoftwareDavid Hover

AssemblerUser Application

Software

Robert BensonBoard DesignUser Application

SoftwareGraphics Pipeline

Control SoftwarePaul Niewoonder

Arithmetic Logic Design

Case

QUESTIONS?