Stick diagrams

1

STICK DIAGRAMS

2

STICK DIAGRAM:

green,, yellow n-diffusion, p-difffusion

Red Polysilicon

Blue Metal

Yellow Implant

Black Contact areas

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NMOS ENHANCEMENT TRANSISTOR:

When polysilicon crosses n-diffusion a transistor forms

n-diffusion

polysilicon

4

NMOS DEPLETION TRANSISTOR:

diffusion

polysilicon

implant

5

PMOS ENHANCEMENT TRANSISTOR:

When polysilicon crosses p-diffusion a transistor forms

P-diffusion

polysilicon

5

6

STICK DIAGRAM FOR NMOS INVERTER:

vin

gnd

7

STEP1:

Draw metal(blue) VDD and GND rails in parallel with enough separation

VDD

GND

8

vin

gnd

STEP2:

Forming transistorsVDD

GND

9

STEP2-1:

vin

gnd Vin

10

STEP3:

interconnections

vin

gnd

Vout

11

STEP4:

Contact points

vin

gnd

VDD

GND

Vout

Vin

12

A nand B

Vdd

Vss

A

B

13

Vdd

Vss

A

Ploy(G)

Ploy(G)

s

s

D

D

B

Ploy(G)

Vout(A nand B)

Nmos NAND GATE

14

A nor B

A B

Vdd

Vss

Nmos NOR GATE

1515

Vdd

Vss

A

Ploy(G)

Ploy(G)

s s

DD

B

Vout(A nor B)

Nmos NOR GATE

16

CMOS STICK ENCODINGS

layer color stick notation color code

n-diffusion Green

p-diffusion yellow

polysilicon red

metal-1 blue

metal-2 dark blue or purple

contact cut black

via black

demarcationline -------------------------------------------------------' brown

Vdd orVss contact black

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CMOS INVERTER:

18

STEP1:

Draw VDD & GND rails

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STEP2:

Forming transistors

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STEP3: How to identify whether the transistor

is nmos or pmos???????????????? Using demarcation line(----------------)

pmos

nmos

Demorcation line

Vdd

Vss

21

STEP4: Inter connections

pmos

nmos

Demorcaion line

input output

STEP5: Contact points

pmos

nmos

Demorcaion line

inputoutput

VDD

GND 22

23

A A nand BB

Vdd

Vss

Cmos NAND GATE

24

Demarcation Line

Vdd contact

Vss contact

Vdd

Vss

Vout(A nor B)

A

Ploy(G)

Ploy(G)

Ploy(G)

Ploy(G)

B

s s

s

s

D

D D

D

Cmos NAND GATE

25

A nor BA

B

Vdd

Vss

Cmos Nor GATE

26

Vdd contact

Vss contact

Vdd

Vss

Demarcation Line

Vout(A nand B)

A

Ploy(G)

Ploy(G)

Ploy(G)

Ploy(G)

s

s

s s

D

D

D

D

B

Cmos Nor GATE

27

Vdd

Vss

Vin

Vout

BiCmos inverter

Vss contact

Vdd

Vss

Demarcation Line

Vout

Vdd contact

BiCmos inverter

29

Vdd

Vss

Vin

Vout

BiCmos inverter

30Vss contact

Vdd

Vss

Demarcation Line Vou

t

Vdd contact

BiCmos inverter