Step by Step Design Tutorial of a fixed-frequency adapter ... · Step by Step Design Tutorial of a...

Step by Step Design Tutorial of a fixed-frequency adapter < 75 W

with very low power consumptionPresented by: Petr Papica

Agenda• Application and requirements

• Flyback converter basics

• Flyback converter parasitic

• Design step 1: Power stage

• Design step 2: Efficiency optimization

• Design step 3: Control mode and protections

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• Design step 4: No Load Input Power

• Design step 5: Magnetics

• Design step 6: EMI

• Demoboard example

The flyback, a popular structure� The flyback converter is widely used in consumer products� Ease of design, low-cost, well-known struture� Poor EMI signature, bulky transformer, practical up to 150 W

flyback≈ 10 – 35 WDVD player

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flyback≈ 40 – 180 Wnotebook

flyback≈ 3 – 5 Wcharger

EPA 2.0 (External Power Supplies)

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(was > 0.84 in previous version 1.1)

(< 0.5 W in 1.1)

(< 0.75 W in 1.1)

EPS 5.0 (ENERGY STAR® Program Requirements for Computers)

• Defines ETEC for different types of products as a Typical Energy Consumption• For the desktop and notebook product categories TEC will be determined by the following formula:

ETEC = (8760/1000) * (Poff * Toff + Psleep * Tsleep + Pidle * Tidle )

• where all Px are power values in watts, all Tx are Time values in % of year, and the TEC ETEC is in units of kWh and represents annual energy consumption based on mode weightings

• The light load efficiency and no load consumption i s more important

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Desktops and Integrated Computers (kWh) Notebook Co mputers (kWh)

TEC (kWh)Category A : ≤ 148.0 Category B : ≤ 175.0Category C : ≤ 209.0Category D : ≤ 234.0

Category A : ≤ 40.0 Category B : ≤ 53.0 Category C : ≤ 88.5

ETEC requirement desktops and notebooks

• Effective from July 1, 2009 (except: game consoles from July 1, 2010)

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drvVout

VoutVout

gnd gnd

An isolated buck-boost

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buck-boostground referenced

buck-boostinput referenced

flybackisolated ground referenced

� The flyback converter is an isolated version of the buck-boost cell� By rotating the switch, we obtain a ground-referenced isolated converter� Keep this in mind for the small-signal analysis!

V(SW / D) = Vin

V(SW / D) = Vout

On-time and freewheel

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inpeak valley on

VI I t

L= + out

valley peak off

VI I t

L= −

SW is closed, D is blocked SW is open, D is closed

Circulates in thesame direction

� When the switch closes, current ramps-up in L� At the switch opening, the stored energy is dumped into C

Cout Rload

The flyback circuit

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� Similar buck-boost equations hold when scaled by the turn ratio N� The switch is now ground referenced for an easier drive� We have galvanic isolation between the primary and the secondary

-Vin.N

VLpLp(Np)

Ls(Ns)

ILs = 0

inpeak valley on

VI I t

L= + CCM

inpeak on

L= DCM

The turn-on event

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N = Ns / Np

� The controller instructs the power switch to turn on� The current increases in the inductor in relationship to Vin and Lp

�The output capacitor supplies the load on its own

in outPIV V N V= + Reverse voltage on the diode

Simplified, no leakage

.VLp=Vout/NLp(Np)

Ls(Ns)

Vin+VLp

ILs = ILp / N

VLp(t)

Vout/N

Applying volt-second balance, CCM

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Vin+VLp

N = Ns / Np

ILp=0S

DS off in in r

VV V V V

N= + = +

Simplified, no leakage

Reflectedvoltage

( ) ( )1 1out on sw

in off sw

V Nt NDT ND

V t D T D= = =

− −

ton = DTsw toff = (1-D)Tsw

dc transfer function in CCM

VLp(t)

Vout /N

.VLp=0Lp(Np)

Ls(Ns)

ILs = 0

Applying volt-second balance, DCM

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ton = DTsw toff = (1-D)Tsw

2out load

in p sw

V L F=

dc transfer function in DCMN no longer plays a roleRload, Lp and Fsw do

N = Ns / Np

,DS off inV V=

24 X1PSW1RON = 10m

3 Cout470uIC = 10

Rload2

Vin100

Vout6 1

X2XFMRRATIO = -0.1

VdsIIn

.Lp2.2m

Flyback, typical waveforms

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RON = 10mROFF = 1Meg

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

� A simple flyback circuit without parasitic elements� It runs open-loop for the sake of simplicity� Vout = 8 V

iin in

I in(t)

ILp(t)LI∆

VinoutV Nout inV N V+

Diode blocks

iin in

I in(t)

ILp(t)LI∆

VinoutV Nout inV N V+

Diode blocks

Input current

Ivalley

Evalley

Flyback, typical waveforms, CCM

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3.002m 3.006m 3.010m 3.014m 3.018mtime in seconds

VDS(t)

Vout(t)

Output cap.refueling

Output capacitorsupplies the load

Id(t)Ipeak/ N

VDS(t)

Vout(t)

Id(t)Ipeak/ N

400miin

I in(t)

ILp(t)

VDS(t)

VoutV Nout inV N V+

DCM (core reset)

Diode blocks

400miin

I in(t)

ILp(t)

VDS(t)

VoutV Nout inV N V+

DCM (core reset)

Diode blocks

Input current

Evalley = 0

Flyback, typical waveforms, DCM

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12.632

12.636

12.640

12.644

12.648

Vout(t)

Vinout

Id(t)Ipeak/ N

12.632

12.636

12.640

12.644

12.648

Vout(t)

Vinout

Id(t)Ipeak/ N

VDS is backto Vin whenall SW areblocked.

2pL valley p valleyE L I=

2pL peak p peakE L I=

Initially stored energy

Stored energy at ton

( )2 2 2 2,

2 2 2pL accu p peak p valley p peak valleyE L I L I L I I= − = − Accumulated energy at Tsw

Energy transfer in CCM and DCM

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Power (watts) is energy (joules) averaged over time (a switching cycle, seconds)

( )2 21

2out peak valley p swP I I L F η= − 21

2out peak p swP I L F η=

CCM DCM, Ivalley = 0

Eta, the efficiency

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The leakage inductance

� The coupling in a transformer is not perfect� Some induction lines couple in the air: leakage flux

Closed pathin the air Leakage flux

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in the air

Closed pathin the airLeakage flux

Leakage flux

An equivalent transformer model

� For a two-winding transformer, the model is simple:� Two leakage inductors� One magnetizing inductor

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Lleak1 Lleak2

primary secondary

VLpLp(Np)

(Vout+Vf) / N

LleakIpeak

LpIpeakVLp

The leakage role

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ClumpILp

SClump VDS

The switch closes:Current flows in Lleak and Lp

The switch opens:The current charges the lump capacitor

Lprim3m

Cout12.2mF

Resr160m

Lleak15u

X4XFMR-AUXRATIO_POW = -0.05RATIO_AUX = -0.06

Vdrain

Rprim0.5

D51N5822

R64.7k C6

Rload9

Vin350 V

Vout16 V

olts VDS(t)

VDS,max750 V

Valley switching

Lprim3m

Cout12.2mF

Resr160m

Lleak15u

X4XFMR-AUXRATIO_POW = -0.05RATIO_AUX = -0.06

Vdrain

Rprim0.5

D51N5822

R64.7k C6

Rload9

Vin350 V

Vout16 V

olts VDS(t)

VDS,max750 V

Valley switching

Drain-source excursion

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Rsense0.5

Creso1.5n

X3MTP4N85m

ILp(t)

ILleak(t)

Ipeak= 695 mA

Rsense0.5

Creso1.5n

X3MTP4N85m

ILp(t)

ILleak(t)

Ipeak= 695 mA

Reflected Vout

( )out f leakDS,max in peak

V V LV V I

+= + +

Characteristicimpedance

Need to limit the excursion!

Cout470uIC = 10

Rload1k

Vin100

X2XFMRRATIO = -0.1

.Lp{Lp}

Lleak{Leak}

parametersLp=2.2mk=0.02

C2100p

D11n5819

Resr150m

Rs250m

∆VLp

∆VLeak

D3MUR160

Vclamp150

Vclamp

CclpRclp

The need of a clamp

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V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

V2k=0.02Leak=Lp*k

� The clamp is made by a low impedance voltage source� When the drain reaches Vin + Vclamp, the clamp diode conducts

-60.0m

ilp in

-60.0m

ILp(t)

I leak(t)

Ipeak= 236 mA I’ peak= 210 mA

∆t = 480 ns-60.0m

ilp in

-60.0m

ILp(t)

I leak(t)

Ipeak= 236 mA I’ peak= 210 mA

∆t = 480 ns

Leakage inductorreset sequence

A reduced secondary-side current

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VDS(t)

Id,peak=2.1 A

VDS(t)

Id,peak=2.1 A

Vr + Vin

Vin + Vclamp

Vr + Vin

Vin + Vclamp

Vr + Vin

Vin + Vclamp

Ringing and turn-on in the valleys?

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valleystv

VDS(t)

valleystv

VDS(t)( )

2v p leak lumpt L L Cf

π= = +

� Wait until the drain voltage is minimum and reduce turn-on losses: valley switching!

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Power stage: Schematic of flyback converter

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NN sec=

Power stage design: Bulk capacitor

outoutout IVP ⋅=

• Output power Pout

• Estimation of input power PinEstimate the η based on the EPA standard

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inavgin V

PI =• Average input current Iin,avg

• Design the bulk capacitor for the maximum output power and the minimum input line voltage.

Power stage design: Bulk capacitor

• 1st current approach

∆Vbulk

Vbulk,min

∆−⋅−∆

⋅⋅

linebulk V

fC 1cos

Simple current approach:

avginbulk V

∆⋅

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• 2nd power approach

bulkbulk V

linefT

inbulk −

⋅⋅=

Use t2=7.5 to 8.5ms for fline= 50Hz

Low volume bulk: large ripple, better PF, lower input RMS current

High volume bulk: low ripple, bad PF, high input RMS current

Consideration:

Power stage design: Drain voltage

Vclamp

Vds(t)

Vds_max

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toff ton

Vds_pk

Power stage design: Transformer ratio

( )max,max,

2085.0 bulkDS

diodefoutC

−−⋅+⋅

Transformer ratio – consideration of the VDSS of used Q1

Reflected voltage Vr at primary from secondary

clampC V

The 20V means margin for clamping diode turning-on overshoot.

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VVV diodefout

min,max

Maximum duty cycle DCmax

In CCM operation: In DCM operation doesn’t depend on N:

min,min,max

swprim

⋅⋅⋅=

NN sec=

Power stage design: Current ripple

The average shared transformer current reflected to primary winding IL,avg

II avgin

avgL =

I valley

I peak

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Choose the relative ripple δIr: it affects the operation in the CCM or DCM

avgLr I

∆=δ avgLr III ,⋅=∆ δ

valleypeak III −=∆

+⋅=2

avgLpeak

−⋅=2

avgLvalley

• For universal AC input design use the δIr in range 0.5 to 1.0• For European AC input use the δIr in range 0.8 to 1.6

Power stage design: Primary inductance

bulkprim ∆⋅

⋅= maxmin,

∆+∆⋅−⋅=3

IIIIDCI peakpeakprimRMS

Transformer primary winding inductance Lprim

Maximum RMS value of the current flowing through primary winding Iprim,RMS

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3max peakpeakprimRMS

II peak

peak =sec,N

∆=∆ sec

∆+∆⋅−⋅−=

secsec,2

sec,maxsec

IIIIDCI peakpeakRMS

Maximum RMS value of the current flowing through secondary winding Isec,RMS

Power stage design: Q1 selection

Then the right device is chosen by parameters VDSmax, Ipeak, ton, toff

Conduction loss at Q1 should be approx. 1% of the Pout

2,100 RMSprim

outDSon

⋅≤

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Current sensing resistor Rsense selection

ILIMsense I

1.1senseprimRMSsense RIP ⋅= 2

The 1.1 factor means 10% margin for Lprim and other parameters spread, to be able to deliver maximum power.

Power stage design: Secondary rectification

outbulk VNVPIV +⋅= max,

The next important parameters for D1 selection are I , I and

D1 selection: Cout selection:

Reverse voltage across D1Minimum Cout value

swrippleout

outout FV

⋅⋅

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D1 selection are Isec,peak, Iout and the fast and soft recovery

rippleout

22sec,, outrmsrmsCout III −=

The maximum allowed ESR of Cout

It is recommended to use more parallel Cout for lowering the output voltage ripple.

Dominant part

Power stage design: Clamping network

TVS – losses in the suppressor:

RCD clamp – 1st iteration:

rclamp

clampswpeakleakswclampclamp VV

VFILFEP

−⋅⋅⋅⋅=⋅= 2

better EMI response

better at no load conditions

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swpeakleak

clampleakclamp

⋅⋅

⋅⋅=

clampclamp R

swclampripple

clampclamp FRV

⋅⋅>

These values need to be optimized for the no load consumption and losses in slow clamping diode D2

TVS vs RCD clamp comparison

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Drain voltage ringing with TVS as clamp Drain voltage ringing with RCD as clamp

Ch1 – Drain, Ch3 – Clamp node

Different Rdamp used in clamp

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Application schematic

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The losses distribution

2.442.53

Power loss [W]

Losses distribution measured without EMI filters an d surge protecting NTC

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Input line Input power Output power Total loss power Efficiency110 V / 60 Hz 72.5 W 63.62 W 8.88W 87.75%

tifier

Primar

y switc

Optimization of efficiency

• There was not found excessive contributor of losses in the power stage of the flyback converter

• Losses in all components should be decreased• Optimization approach:

1) decreasing the losses in power stage by selection of primary switch Q1 and secondary rectifier D1

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primary switch Q1 and secondary rectifier D1

2) decreasing the losses in power stage by decreasing losses in transformer

3) try to improve the bridge rectifier (not much space)

4) decreasing the conductive losses in EMI filters

5) Do we need surge protecting NTC in case of “low value” bulk capacitor ?

Influence of EMI filters• Input EMI filter contributes to the conductive losses mainly at full load

and low line condition• The high inductance 22mH or more is needed to reject the “low”

frequency emissions ( below 1 MHz )• There is needed to use two chamber CM choke or 2 CM mode chokes

to reject the high frequency emissions above 10MHz• Output EMI filter (CM choke) reject the high frequency emissions from

the DC cord, only low inductance is needed → low Rdc → low

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the DC cord, only low inductance is needed → low Rdc → low conduction losses

• The most important are losses in the high inductance input common choke from the efficiency optimization point of view

Note from experiments:

There was found an influence of HF ripple at input current to the precision of measurement of input power using wattmeter YOKOGAWA WT210. There were measured lower input power with the connected 100uH common choke in comparison without any EMC filter. (at the same conditions) It is better always to use some EMI filter, with small Rdc to reject the error given by the noisy HF currents.

Transformer optimization result

Transformer ratio Ns/Np optimization

88.00%

88.50%

89.00%

89.50%

Q1 breakdown area

Optimum ratio

The optimum ratio is given by the Q1

maximum break down voltage with 15%

derating factor

Decreasing the Ns/Np decreases the

secondary winding

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85.50%

86.00%

86.50%

87.00%

87.50%

0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Transformer ratio Ns/Np [-]

] secondary winding losses and primary

RMS current

Decreasing the Ns/Np increases the Q1

switching losses and secondary RMS

current

Improving Efficiency

• Sources of loss:

– Switching losses:

– Losses caused by leakage inductance:

SWoffturnDRAINDRAINswitchingloss FVCP ⋅⋅⋅= −2

)()( 2

FILP ⋅⋅⋅= 21

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• Ways to improve efficiency:

– Lower the switching frequency FSW � frequency foldback at light loads

– Lower the Drain voltage at turn-off � valley switching

SWpeakleakloss(leak) FILP ⋅⋅⋅= 2

Synchronous rectification

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• New SR controller NCP4303 coming in 2010

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Application schematic

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PWMmodulator

Verror

PWMmodulator

Verror

The voltage-mode PWM generation

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10.0u 30.0u 50.0u 70.0u 90.0utime in seconds

� In voltage-mode, one compares the error voltage to a fix ramp� This is « Pulse Width Modulation » also called « PWM »

Vin Vout

Rupper

ErrorAmplifier PWM

comparator

This levelsets the duty-cycle

The voltage-mode PWM generation

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VrefRlower RsenseI > Imax ?

--> reset

� The inductor current is sensed for safety only

3.003.50

Error voltage

MOSFET

3.003.50

Error voltage

MOSFET

The current-mode PWM generation

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2.00id

Inductor peak current2.50m 2.57m 2.65m 2.72m 2.80m

time in seconds

2.00id

Inductor peak current

� In current-mode, the error voltage fixes the peak current

Vin Vout

Rupper

ErrorAmplifier

Current sense

This levelsets the peak current

The current-mode PWM generation

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VrefRlower

Current sensecomparator

Rsense

� The sense resistor provides a pulse-by-pulse current limit

Same modulation between VM and CM� Both modulators use trailing edge modulation

TrailingTrailing edge modulation

feedback

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LeadingLeading edge modulation

feedback

NCP1237/38/87/88 flyback controller

The NCP1237/38/87/88 series represents the next generation of fixed frequency PWM controllers. It targets applications where cost-effectiveness, reliability, design flexibility and low standby power are compulsory.

� High-voltage current source with built-in Brown-out and mains OVP

� Freq. reduction in light load conditions and skip mode

� Adjustable Over Power Protection

� Fewer components and rugged design

� Extremely low no-load standby power

� Simple option to alter the max. peak current set point at high line

Unique Features Benefits

Value Proposition

Application Data

DSSDual OCP

LatchAuto

RecoveryNCP1237A Yes Yes YesNCP1237B Yes Yes Yes

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� AC-DC adapters for notebooks, LCD monitor, game console, printers

� CE applications (DVD, STB)

� NCP1237/38xDR2G - NCP1287/88xDR2G� SOIC-7 2500p per reel

Others Features

Ordering & Package InformationMarket & Applications

� Latch-off input for severe fault conditions, allowing direct connection of NTC

� Timer-based protection: auto-recovery or latched� Dual OCP option available� Built-in ramp compensation� Frequency jittering for a softened EMI signature� Vcc operation up to 30 V

Pb O, DW

Various options available depending upon end applications needs

NCP1237B Yes Yes YesNCP1238A Yes No YesNCP1238B Yes No YesNCP1287A HV only Yes YesNCP1287B HV only Yes YesNCP1288A HV only No YesNCP1288B HV only No Yes

NCP1237/38/87/88 – Built-in Startup FET

High startup current to

A flyback auxiliary winding supplies biasing voltage in normal condition to save power

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No startup resistor!

Low initial startup current to prevent damage if Vcc pin is shorted to ground.

High startup current to reduce charging time

Saves PCB area& saves power

How it works...

NCP1237/38/87/88 – Dynamic Self Supply (optional)

3ON/OFF

11.3V avgVccon

Vccoff

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C10.5V/12V

10.00M 30.00M 50.00M 70.00M 90.00M

Currentsource

Power ON � Current Source turns ON � Vcc is rising; no output pulses

Vcc reaches Vcc(on) � Current Source turns OFF � Vcc is falling; output is pulsing

Vcc falls to Vcc(off) � Current Source turns ON � Vcc is rising; output is pulsing

No need of auxiliary winding!Dynamic Self-Supply

NCP1237/38/87/88 – Dual startup current level

Startup current is low initially to

Startup current is

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low initially to prevent damage when VCC pin is grounded.

Startup current is activated when VCCdrops to VCC(off). Hence, the voltage never drops below VCC(off) after startup.

off when VCCreaches VCC(on)

NCP1237/38/87/88 – Brown-out and Mains OVP

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Can be connected to thehalf-wave rectified ac line

Detection independent ofRipple on HV pin

NCP1237/38/87/88 – Brown-out and Mains OVP

One Shot

VHV(start)

Starts only at VCC(on)

VHV(stop)

HV timerstarts

HV timer

restarts

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Passes full line cycle drop-outTimer-based detection

One Shot

40ms min.

Brown-out

∆Ipeak

Detectionoccurs here

Turn off isdelayed …

Ipeak,maxcontroller

Ipeak,maxreal

∆Ipeak

Detectionoccurs here

Turn off isdelayed …

Ipeak,maxcontroller

Ipeak,maxreal

Current overshoot: do not underestimate it…

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�Watch-out for clamp voltage variations, at start-up or in short-circuit� The main problem comes from the propagation delay!

sense,max in,maxpeak ,max prop

sense p

V VI t

R L= +

NCP1237/38/87/88 – Over Power Protection

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The compensation currentcreates an offset on theCurrent Sense signal

Over Power Protection Maximum output power clamped

Need to compensate for theeffect of the propagation delay

NCP1237/38/87/88 – Dual OCP threshold

VOUTFault timer

starts VOUTFault timer

starts

Over load

Over loadTransient

peak power

Output still in regulation

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Accommodates large output power transients

Suitable for printers

Skip Output load

Max output power

Skip Output load

Max peak

Max DC

0.7V at CS pin

0.5V at CS pin

These protections use the Up/Down counters, like classical analog integration.

NCP1237/38/87/88 – 4 ms Soft Start

with soft-start

voltage / current without soft-start

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VCCMax. current setpoint envelope

4 ms “digital” soft-start operation

Stressless start-up phase4 ms Soft Start

NCP1237/38/87/88 – Frequency Foldback

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Increased efficiencySwitching frequencylowered at light load

No audible noiseSwitching frequencyclamped at 25 kHz

NCP1237/38/87/88 – Recover from Standby

Soft-Skip mode is left as

soon as the voltage on the feedback pin

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Improved Load Transient response time

Transient Load Detect Function (TLD)

feedback pin reaches the

TLD threshold

NCP1237/38/87/88 – Latch-off Protection

VLATCH

Latch!

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Latch!

Less external components needed

An NTC thermistor can be directly connected to the IC

CCM operation, current instabilities

Perturbation has gone…

∆IL(0)

Perturbation has gone…

∆IL(0)

Duty-cycle < 50%

Asymptotically stable

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Duty clamp

∆IL(0)

Duty clamp

∆IL(0)

Duty clamp

∆IL(0)

Duty-cycle > 50%

Asymptotically unstable

CCM operation, curing current instabilitiesIL

I (T )

∆IL(0)

IL(Tsw)

I (T )

∆IL(0)

IL(Tsw)

( ) (0) (0)'

L sw L La

SI nT I I a

− ∆ = ∆ − = ∆ − +

Must staybelow 1

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tdTsw d’Tsw

IL(Tsw)∆t

tdTsw d’Tsw

IL(Tsw)∆t2

250%aS S>Inject ramp compensation

d = 100%

• There is a built in slope compensation with no external setting• The internal slope compensation is activated if the duty cycle is higher

than 40%• The amount of slope compensation is 5mV/% observed at CS pin

NCP1237/38/87/88 – Slope compensation

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Block schematic

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Reducing No-load Input Power

• Static losses in the start-up circuit:– Start-up resistor permanently drawing current from the bulk capacitor

• Ways to lower the start-up circuit losses– With external start-up resistor � Extremely low start-up current– Integrated start-up current source � Extremely low leakage when off– Connect the start-up circuit to the half-wave rectified ac input

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– Connect the start-up circuit to the half-wave rectified ac input

HV rail

NCP1351 Start-up resistors

RstartupHW

startupstartupHW

Selected frombulk connection

Reducing No-load Input Power

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10.0M 30.0M 50.0M 70.0M 90.0Mtime in secs

RstartupHW

CVccauxiliarywinding

Mainsinput

10.0M 30.0M 50.0M 70.0M 90.0Mtime in secs

RstartupHW

CVccauxiliarywinding

Mainsinput

4startup

startupHW

π= Brings a 21% reduction in power

No load input power reducing approach

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• Decrease the transformer leakage inductance• Use the controller IC with the frequency foldback and skip mode features• Do not allow the DSS operation (Vcc cap increase)• In case of low Vcc and high aux winding leakage increase the aux number of turns

to disable the DSS• Decrease the value of the Vcc damping resistor (may affect the EMI)

No load input power reducing approach

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• Lower the M1 switching losses• Optimize the clamping circuitry• Reduce the losses in the secondary rectifier and its snubber• Decrease the TL431 biasing• Decrease the cross current through the feedback resistor divider• Set a stable operation for all loading currents• Do not use the output voltage indication LED

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Area product A P

• There is defined the area product AP [m4]• Product of effective window area Wa [m2] and iron cross

section area Ac [m2]

caP AWA ⋅=

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• Allows fast, effective and optimal magnetic design• Should be published in core datasheet

Window utilization factor KuKu is a measure of the amount of copper that appears in the window area of transformer. This window utilization factor is affected by:

1) Wire insulation2) Wire lay (fill factor)3) Bobbin area

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3) Bobbin area4) Insulation required for multilayer windings or between windings

Typical values lay in range 0.35 to 0.48

The load coefficient K load

• Flux density in magnetic should be designed at Ipeak with some margin (5%) to avoid saturation

• Do you really need 100% Iout for 100% time??

If not, decrease core size!!,RMSoutI

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RMSout

RMSoutload I

Example: • Maximum DC output current is 3.5A, but it’s only needed for

transients• The long term RMS value is only 1.75A (at least 10 min.)• Loading coefficient is only 0.5 (not 1) → core size is smaller

→ losses in core and in copper are smaller

Flyback transformer core sizing

The core size can be calculated by the AP factor in case of these inputs:

1. Converter parameters: Lprim, Ipeak, Kload, δIr, DCmax

2. Core maximum flux density Bmax considered with the hysteresis and eddy current losses at switching frequency Fsw

3. Winding parameters (utilization factors for primary and secondary windings Kuprim, Kusec), (current densities in primary and secondary windings Jprim, Jsec

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windings Jprim, Jsec

Now the appropriate core can be selected from the vendor products list by the AP factor .

secsec

maxmax

⋅−

⋅⋅⋅

primprimload

peakprimP

Windings design

• Number of turns of primary winding

peakprimprim AB

⋅⋅

NTNNT ⋅=

• Number of turns of secondary winding

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primNTNNT ⋅=sec

, NTVV

diodefout

VccfCCaux ⋅

• Number of turns of auxiliary winding

Air gap length l g

−⋅⋅

MPL – core magnetic path length

µ0 - permeability of vacuum

MPLl g <<in case of

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µ0 - permeability of vacuum

µr - permeability of core

In case an EE, RM or pot core is used, divide the calculated lg by factor 2, because your core has 2 air gaps in magnetic path

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How to improve EMI of my design?

AC line filter

Diode snubber

DC output filter

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DRV dampingPower switch loop

Clamping loop

• All switching loops with RF currents should have small area

• Divide input AC filter at two chokes to decrease the parasitic capacitance coupling

• CY – closes the current loop for the RF currents injected via transformer

Diode snubber design

• Snubber resistance value should be close to the characteristic impedance of ringing circuitry

SECleaksnubber C

Lleak,SEC –the transformer leakage inductance observed from secondary side

Cd – reverse direction diode capacitance

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• RC time constant of the snubber should be small compared to the switching period but long compared to the voltage rise time

dsnubber CC ⋅÷≈ 43

capacitance

PCB Layout tips

Clamping loopDRV loop

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Output loop Capacitor pads arrangement for better filtering RF currents

Power switch loop

Diode snubber

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Preliminary demonstration board

A typical 65 W notebook adapter (19 V output)

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(optimized for EPS 2.0)

Schematic of preliminary demonstration board

A typical 65 W notebook adapter (19 V output)

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(optimized for EPS 2.0)

Demonstration board Efficiency (measured with DC co rd)

% of POUTnom

115 Vac/60Hz 230 Vac/60Hz

100 %(65 W)

87.10 % 87.37 %

75 %87.52 % 87.63 %

The DC cord length is 1.05m and copper cross sec. is 0.75mm2

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75 %(49 W)

87.52 % 87.63 %

50 %(32 W)

87.54 % 87.88 %

25 %(16 W)

87.79 % 85.96 %

Average at 115Vac is 87.32% and at 230 Vac is 87.21 %

Demonstration board Standby PowerLight load and no load input power with the NCP1237

115 Vac/60Hz 230 Vac/50Hz

10 %(6.5 W)

86.55 % 83.74 %

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5 %(3.3 W)

85.40 % 78.72 %

1 %(0.65 W)

77.49 % 73.77 %

No load 51.1 mW 73.5 mW

Demonstration board Efficiency

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0 10 20 30 40 50 60 70

Pout [W]

– 115 Vac - NCP1237

– 230 Vac - NCP1237

Demonstration board conducted EMI

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80% of full load (2.72A) at 230V/50Hz NCP1237B65kHz

NCP1237B100kHz frequency jittering

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Ref1 – DRV frequency

NCP1237B100kHz frequency foldback

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Ch1 – DRV, Ch2 – FB, Ref1 – DRV frequency

Load transient response from 20% to 100%

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Ch1 – Drain, Ch2 – FB, Ch3 – Vout (AC coupling), Ch4 - Iout

Load transient response from 100% to 20%

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Ch1 – Drain, Ch2 – FB, Ch3 – Vout (AC coupling), Ch4 - Iout

Conclusion

• Meeting the most recent requirements from ENERGY STAR®

or IEC is possible with the classical Flyback converter

• The new controller NCP1237/37/87/88 with frequency foldback and skip-mode at light load makes it possible

• Average efficiencies above 87% are possible

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• No-load input power below 300 mW is possible• No-load input power below 100 mW is achievable, although

the controller alone cannot ensure this. The whole power supply must be designed to reduce power waste.

References

Tutorial and Application notes:

http://www.onsemi.com/pub_link/Collateral/TND376-D.PDF

http://www.onsemi.com/pub_link/Collateral/AND8461-D.PDF

http://www.onsemi.com/pub_link/Collateral/DN06074.PDF

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http://www.onsemi.com/pub_link/Collateral/DN06074.PDF

Feedback loop design spreadsheet:

http://www.onsemi.com/pub/Collateral/FLYBACK DWS.XLS.ZIP

Thank You! Any Questions?

Backup

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Over power compensation

OPPOPPoff

OPPOPP

PROPbulk

CSPEAK R

VI ⋅⋅+

⋅−⋅+= int

Rt ⋅

The overpower compensation affects the primary peak current, by the following formula:

Then the overpower compensation resistor can be calculated:

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sensePROPOPP gL

⋅⋅

The over power compensating resistor affects only the Ipeak value, but in CCM the output power is given by the following formula, where Ivalley plays a role:

1valleypeakswprimout IIFLP −⋅⋅⋅⋅= η

2nd level over current protection

( )sense

OPPOPPoffbulk

CStranTRAN R

VI ⋅⋅−−=

The overpower compensation affects the 2nd level over current protection by the addition of bulk voltage feed forward.

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The 2nd level over current protection can be used for reducing the transformer size to ½ and keeping the peak power capability.

Spread sheet design of OPC

Inputs: Output voltage Vout [V] 19Primary turns N1 [-] 100Secondary turns N2 [-] 25Ramp Comp at CS RaCo [mV/%] 5Maximum int set point Vilimit [V] 0.7Sensing resistor Rsense [Ohm] 0.235

OPC design spread sheet was created and the user can choose the right ROPP and it’s effect to Ipeak, Itran, Pout and Ptran:

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Sensing resistor Rsense [Ohm] 0.235Propagation delay tprop [ns] 100Primary inductance Lp [uH] 560Vin to Iopp ratio gopp [uS] 0.5Over power comp resistor Ropp [Ohm] 680Switching frequency Fsw [kHz] 652nd level overcurrent prot Vcstran [V] 0.5

Spread sheet design of OPCPmax & Ptran vs line input voltage

Ipeak & Itran vs line input voltage

], Itr

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0 50 100 150 200 250 300 350 400

Vbulk [V]

Ptran Pmax

0 50 100 150 200 250 300 350 400

Vin [V]

Ipeak Itran

Keeping constant Ipeak in CCM mode tends to Ivalley decreasing with increasing the Vin. That’s why the maximum output deliverable power Pout increases with increasing Vin. Choose the right compensation.

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