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Webs• Production approaching the
end• Few problems with cut lines
on flexible part• Discovered with noise_scan
program when mounted on the detector
• Special test bench for this problem was discussed at the beginning but deemed not needed – Probably not justified for few
cases• Current test bench proved to
be very efficient to discover majority of the problems
COVER• Full production
arrived delayed and damaged– FedEx subcontracted
the delivery to CERN – Test all boards ASAP
to know the yield and possible problems
– 20 left to test– 1 damaged
mechanically– 10 did not pass the
test
COVER• Keep covers in place when
installed on the detector– 2 modules completely
installed– Tested with final LV patch
panels– Few bad straw wires and
web connections discovered during tests
• Remote programming– Firmware version 10 bugs
for remote programming– Firmware version 11
• Remote pgm now works• Fixed bug in multi-edge
bit• Improved timing for DAC
read-back
SERVICES• Patch panels and on-
detector cabling (Johan)– Dense but feasible– LV and HV cover cables
with different lengths– All LV and HV cables
ordered with timed delivery– RJ45 needs careful planning
• How many different lengths?
• Storage behind rack ~1 meter
• Wait for chamber installed in the pit?
• UK company ready to produce batches of different lengths
SERVICES• Patch panels LV and HV
– HV ordered at CERN• Modification with copper GND plate instead od aluminium
– LV tested completely by Johan• DCS control in advanced state• Still open
– External temperature sensors– Humidity measurement ?
– LV production tight• Organized by TE-MPE group• Fast PCB production• Components for assembly prepared • Total time ~6 weeks• ½ March at CERN• Johan to organize the test
SERVICES• MPOD ordered
– … but order lost– Delivered to ELCOTRON– Missing in Wiener– End of January not possible– Now end of February– HV modules new production
• Not on stock• Will deliver 8-channel HV modules• Swap with final when delivered
• As soon as we receive our MPOD– We have to return mini-MPOD which we have used till now– Test power supply of 1 module/2 views (full chamber?)
• Order the rest 3 MPODs, eventually 1 spare
SRB
• 2 FPGAs ready for schematics– Event manager– Frontend interface– Work is now focusing on vme and trigger
• Changes in connectivity and data flow– Input FPGA FESRB
• Added data/cmd direct links to vme_bm – For control and cover tests– Use of event_mgr unpractical
– Delay of every cover clock line (16 lines) must be adjustable• Trying 2 solutions
– Use FPGA feature– Specialized clock generation chips with 8 outputs
SRB – components
TTC
LEMO
L0 OUT
COVERS
TTCRx
COVER CONTROL,
DATA, SYNCH
EVENT PROCESSOR
2(4)GB DDR3
DATA TO PC FARM
TIME REMAP
L0 PROCESSOR
VME INTFON-LINE
MONITOR
L0 LOOK_UPTABLE
WORK
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