View
247
Download
0
Category
Preview:
Citation preview
Serial Input/Output Interface
• Outline– Serial I/O
– Asynchronous serial I/O
– 6850 ACIA
– 68681 DUART
– Synchronous serial I/OInterface Standards
– 68000 Serial I/O Example
• Goal– Understand serial I/O fundamentals
– Understand ACIA and intro to DUART
• Reading– Microprocessor Systems Design, Clements, Ch. 9
Serial I/O
• Serial data transmission– serial - bit at a time
– cheap, simple, easy to use
– asynchronous or synchronous
– full or half-duplex
– transmission medium - twisted pair, IR, fiber, etc.
• Serial interface– parallel-to-series, series-to-parallel adaptor
– line drivers
– plugs and sockets
• Application– connect CPU to remote peripheral
– examples
» CRT
» temperature sensor
Asynchronous Serial I/O
• Asynchronous - transmitter and receiver do not synchronize timing– clocks at transmitter and receiver not synchronized
– data at each end is synchronized to local clock
• Data format– developed in days of electromechanical hardware
– idle - mark level, logic 1
– start bit - space level, logic 0
– 7 or 8 data bits - usually an ASCII character
– optional even or odd parity bit
– stop bit - logic 1, 1 or 2 bit times in length
– 12 combinations in total
Data Timing
• Bit time = T
• Receiver waits for start bit falling edge– triggers local clock
• Samples next N bits at their centers– using local clock, compute T/2
• Clock precision– < T/2 error in 9-11 bits between transmitter and receiver clocks
– < 5% error - trivial with crystal oscillators
Data Formatting Issues
• Transmitted characters– ASCII 7-bit character set is standard in US
– older IBM EBCDIC still exists in a few places
– ISO character sets for non-English languages
» often 16-bit characters
• Binary data– often must put 8-bit binary data into 7-bit characters
– binhex, uuencode, ZIP, etc.
» tricky to include control information
• Efficiency– 7-bit data, start, 1-bit stop, parity => 70% overall efficiency
6850 ACIA
• 6850 Asynchronous Communications Interface Adaptor (ACIA)– series-parallel data conversion
– asynchronous data formatting
• CPU Side Interface– 6850 looks like byte-wide SRAM
– accesses synchronized to E enable clock
– uses 6800 synchronous bus cycles
– 3 chip enables
– 1 register select pin
» connect to A01 => registers on word boundaries
– IRQ* for autovectored interrupts
ACIA Receiver and Transmitter
• Receiver– RxD - receiver data input - serial data input
– RxCLK - receiver clock
» 1, 16, or 64 times receiving data rate
» the receiving Òbaud rateÓ
» baud = transition/second, from Baudot
– DCD* - data carrier detect
» use with modem, incoming data is valid
• Transmitter– TxD - transmitter data output - serial data output
– TxCLK - transmitter clock
» normally same as RxCLK
– RTS* - request to send output - ACIA is ready to transmit data
» set or cleared by software control
– CTS* - clear to send input - modem is ready, has carrier
» CTS* negated inhibits transmission
6850 ACIA Operation
• 6850 registers– control, status, transmit data, receive data
– accessed by RS and R/~W pins
» transmit and control are write only
– note, if RS = A01, use LDS*, register address is odd
• Transmit data register (TDR)– write data to transmit
• Receive data register (RDR)– read received data
6850 Operation (cont.)
• Control register (CR)– define ACIA operating mode
– CR1-CR0 - ratio between clock and data rate
» 11 = chip reset
– CR4-CR2 - 7/8 bits, even/odd/no parity, 1/2 stop bits
– CR6-CR5 - RTS* state, interrupt enable
» interrupt when TDR empty, unless CTS* high
» 11 - transmit break - logic 0 continuously
» usually causes interrupt at receiver
– CR7 - enable receiver interrupt when RDR full
» also enables interrupt on overrun and DCD* high
6850 Operation (cont.)
• Status register (SR)– transmit and receive status
– SR0 - receiver data register full
» if CR7 set, also set SR7 IRQ bit
» cleared on data read, reset, or DCD* high
– SR1 - transmitter data register empty
» cleared on write, reset, CTS* high
» if CR7 set, also set SR7 IRQ bit
– SR2 - data carrier detect
» set if DCD* high, also set SR7
» remain set if DCD* goes low, clear on SR and data read
– SR3 - clear to send
» value of CTS* input
– SR4 - framing error
» set if missing stop bit, cleared otherwise
» overwritten by each character
6850 Operation (cont.)
• Status register– SR5 - receiver overrun
» set if RDR overwritten by next character before read by CPU, when last bit of next character read
» cleared by RDR read or reset
– SR6 - parity error
» set when parity error in incoming character
» cleared when character read
– SR7 - interrupt request
» set when (SR0 or SR1 or SR2) and CR7 set
» IRQ* asserted
» clared by RDR read, TDR write, reset
Using the 6850 ACIA• Minimal system
– no use of RTS*, CTS*, DCD*, no interrupts
– only look at SR0-SR1
ACIAC EQU $E0001 CR/SR addrACIAD EQU ACIAC+2 TDR/RDR addrRDRF EQU 0 RDR fullTDRE EQU 1 TDR emptyINITIALIZE MOVE.B #$F3,ACIAC Reset ACIA
MOVE.B #$19,ACIAC No IRQ, RTS* low, 8-bit dataeven parity,1 stop bit,16x
ckRTS
INPUT BTST.B #RDRF,ACIAC Test receiver statusBEQ INPUT Poll until has dataMOVE.B ACIAD,D0 Put data in D0RTS
OUTPUT BTST.B #RDRF,ACIAC Test transmitter statusBEQ OUTPUT Poll until read for dataMOVE.B D0,ACIAD Transmit the dataRTS
68681 DUART
• Dual universal async receiver/transmitter (DUART)– like pair of 6850s plus baud rate generator
» 300 to 19,200 baud
– full 68000 bus interface, vectored interrupts
– quadruple buffered input
– double-buffered output
– 6 input, 7 output pins for general-purpose use
• Multiple modes– normal
– automatic echo
– local loopback
» feed transmitted data to receiver input
– remote loopback
» feed receiver data to transmitter
Synchronous Serial I/O
• Synchronous– clocks synchronized over long period of time
– high level data link control (HDLC) standard
» data packet format
• Bit synchronization– where do bits shart?
– encode timing with data - phase/Manchester encoding
• Word synchronization– character oriented
» transmit two SYN ($16) characters to start message
– bit oriented
» start/end data block with %01111110 - open/close flag
» use bit stuffing to avoid spurious flag - put 0 after 5th bit in data word, delete at receiver
Serial Interface Standards
• Need standards for “plug compatibility”
• RS-232C/D– connect data terminal and communications equipment
– electrical and mechanical interface
– usually only a subset of pinouts implemented
– standard interface chips - line drivers
• RS-423– update to RS-232, higher speed, longer cable length
• RS-422– differential wire pairs, higher speed, longer cables
68000 Serial I/O Example
• Dual serial ports– 6850
– baud rate generator
– 1488 line drivers/1489 line receivers
• Transparent mode– use RTS* to connect receive line of port 1 to transmit line of
port 2, and receive line of port 2 to transmit line of port 1
– interface can still monitor incoming data
• Issues– must set baud rate by switches on board
– ACIAs not fully decoded, take $010000 to $01FFFF
– automatically make IRQ4-7 autovectored
Recommended