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Sept. 2005 EE24C Digital Electronics Project
EE24C Digital Electronics Project
Design of a Digital Alarm Clock
Sept. 2005 EE24C Digital Electronics Project
Contents
• Natural Specification• Design Specification• Labs Description• Theory :
– Sequential Logic Design– Counters and Registers
• Design Solution• Material Resources
Sept. 2005 EE24C Digital Electronics Project
Natural Specification(From a Hardware Store Owner)
"I’m proposing a 2-month contract to a second year Electrical and Computer Eng. student. The elected student will have to develop for the local market a digital clock that displays time, i.e. 2:00:00 AM. The device should have features such as time setting, alarm setting, autonomy of 3 hours in case of power failure, and proper time display using 7-segment Leds."
Sept. 2005 EE24C Digital Electronics Project
From the previous specification, a good design approach consists of analyzing the system in terms of its functionality(block diagrams) and electrical properties.
For this design we will use an FPGA board as the target architecture and Xiinx ISE/Modelsim as the software development platform.
We consider the following steps which are crucial for the project completion:
• Modular analysis and implementation of the system.
• Analysis of electrical properties (power consumption, operating frequency, size on chip).
• Implementation and testing of the final design.
• Writing of a small user manual to be included in your project report.
Sept. 2005 EE24C Digital Electronics Project
Design Specification
The system is synchronous and reactive1. It uses a reference clock of 50 MHz in order to generate other useful signals for its internal operations. We can identify four major functions:
• Commands entering via a 4 x 3 keypad which is used for setting purposes.
• Counting module made of four BCD counters which modulo are 2, 12(counting from 1 to 11), 60, and 60 respectively.
• FSM controller that is used for the sequencing of events.
• Time-multiplexing display of the correct time (i.e 2:30:58 am).
Sept. 2005 EE24C Digital Electronics Project
Figure 1: Block diagram of the digital alarm clock
Time-Multiplexing Display decoder module
Counter AM/PM Counters of Hours Counter of Minutes Counter of Seconds
Control Module + ALARM settings
FrequencyDivider
Debounce-free Keypad Encoder 4x3 Keypad
DisplayUnit made of 7-segment Leds and 4 normal Leds, time format: 2:00:10 AM
Reference clock
8 bits (2 BCDs) 8 bits (2 BCDs)8 bits (2 BCDs)
7-bit segment code 7-bit anodeselection
4-bit LEDs for :
MultiplexingClk
1 Hz Clock
2-bit Counter Code
8-bit time value(2 BCDs)
12-bitCode
TcsTcmTch
CE CE CE CE
17-bit AlarmCode
Alarm pulse thatactivates the buzzer
17-bit Count
st_h st_m st_sst_ap
Reset
st_c st_al
al_
clk
ctr_clk
db_clk
ce ce ce ceclr clrclrclrst st st st
cpcpcp
Keycode[16:0]
Din[8:0] Din[8:0] Din[8:0]Din0
Dout Douth[8:0] Doutm[8:0] Douts[8:0]
Seg[6:0] Anode[6:0] Leds[3:0]
Ccode[1:0]ct_clk
mux_
clk al_clk
db_clk
Reset
Mod-60Mod-12 Mod-60Mod-2
cnt_code[1:0] st_cnt st_alr clr_sig Data_alr[15:0]
Disp_ap Disp_h[7:0] Disp_m[7:0] Disp_s[7:0]
Key_
signal[1
1:0
]
ResetResetReset
Resetareset
Sept. 2005 EE24C Digital Electronics Project
Figure 2: Controller and alarm modules
Controller Alarm
st_cnt clr_sig st_alr ctr_clk cnt_code[1:0]
st_ap st_h st_m st_s CE
ld_alarm load
clr
Data_alr[15:0]Pulse to Buzzer
2
ctr_clk
( A
m/P
m,
Ho
ur
& M
n C
od
e)
17 bits
al_clk al_dis
reset
Alarm Code
17 bits
Sept. 2005 EE24C Digital Electronics Project
Figure 3: Alarm module
al_clk (Alarm pulse)
ctr_clk
load
clr
Data_alr
Data_out
17-bit count (Am/Pm, Hours & Minutes)17-bit Alarm
Register
17-bit Comparator
equal
To the Buzzer
17 bits
17 bits
A[16:0] B[16:0]
60 s
al_dis
Alarm Code
17 bits
Sept. 2005 EE24C Digital Electronics Project
- Lab 1: Design of Modulo counters
- Lab 2: Debounce-free Keypad Encoder and Time-multiplexing Display Decoder
- Lab 3 Frequency Divider and Alarm Module
- Lab 4: Buzzer module and Power Failure Detection
- Lab 5: FSM Controller Module
- Project Realization: Integration and Testing
Sept. 2005 EE24C Digital Electronics Project
Lab 1: Design of Modulo Counters
Sept. 2005 EE24C Digital Electronics Project
Basic element to be used
Sept. 2005 EE24C Digital Electronics Project
Sept. 2005 EE24C Digital Electronics Project
Sept. 2005 EE24C Digital Electronics Project
clrCEst_ap st_h st_mst_h st_s
Dout Douth[7:0] Doutm[7:0] Douts[7:0]
` ct-clk
8 bits 8 bits 8 bits
Counting Module (Am/Pm, Hours, Minutes, and Seconds)
Figure 7: Counting Module’s Block Diagram
Sept. 2005 EE24C Digital Electronics Project
Lab 2: Keypad Encoder and Time-multiplexing Display Decoder
Debounce-free Keypad Encoder
Sept. 2005 EE24C Digital Electronics Project
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