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Leveraging Test Data to Enhance Quality and Yield to Ensure Cost
Effective Execution for 2.5D/3D (3D-IC) Manufacturing
Yaacov De Russo, Director of Business Development, Optimal+
3D-IC Cost, Quality & Yield on Multiple Fronts
Process Technology
• Improve TSV
process
• Improve bonding
• Improve wafer
thinning
• Reduce process
costs
Design & Testability
• EDA for 3D-IC
• DFT / DFR
• BIST
• KGD/I/S
• Repair &
Redundancy
ATE
• Increase utilization
• Test time reduction
• Higher site count
• Reduce CapEx per
site
Test Data
• New test insertions
• Tight quality grade
• Screening & Pairing
• Cross supply-chain
correlation
• Internal & External
suppliers
• Traceability
• Online action
Source: IMEC 2013
Infrastructure For Leveraging 3D-IC Test Data
Wafers Test SLT RMA
E-Test S1 S2 FT1 FT2 SLT
Parametric Data
Test “Metadata”
Virtual Test Data
Facility/Area
Test Operation
Au
gm
en
ted
Data
Data integration
Correlate, Predict, Improve
A comprehensive & integrated data infrastructure is needed to
enhance 3D-IC yield, quality and cost performance
Is “Good Die” Good Enough For 3D-IC ?
• Yield of each Die/Component has critical impact on 3D-IC compound yield
• However, it is not fully maximized because important data is not leveraged!
Missing attributed data Augmented data
• Parametric data is not enough!
• Test “metadata”: Wafer geography, tester variation, repair, re-test, setup configuration..
• Virtual Test (non native tests)
Limited integration of data Limits the ability to correlate between operations
• Different operations => test tools, data structure
• Distinct facilities/areas => data transfer
• Different/External suppliers => raw data visibility, formats, structure, availability
Traditional pass/fail binning fails to reflect the underlying “grey” of die quality
• Distribution of parametric and metadata values
• Quality Index to grade good die: based on cross-operation, cross-data correlation
Multiple “Good” Dice can create problematic combinations: Stack Failure
and/or Performance
• Bin-1 Dice may not be good enough! Bin-1 on a Grayscale is needed.
• Dice incompatibility within specific Parameter
• Dice incompatibility between Parameters and Augmented test data
• Dice interdependencies correlation
• Dice pairing not fully Optimal
Repair rate
X+Y+Z
Tool variations
Tester
Var
Geography
GDBN
Leakage
Power
Speed
Good Dice Good 3D-IC Stack ?
Para
metr
ic T
est
Data
Test
Meta
data
Vir
tual Test
Data
Advanced Analysis & Execution
• Comprehensive:
• Cross-Area / Operation
• Die / Component
• Parameters / Augmented data
• Adaptive algorithms for
Screening and Pairing
• Real-Time / Online action
• Bin Grade
• Bin Switch
Repair rate
X+Y+Z
Tool variations
Tester
Var
Geography
GDBN
Leakage
Power
Speed
Good Dice Good 3D-IC Stack ? (cont.)
Para
metr
ic T
est
Data
Test
Meta
data
Vir
tual Test
Data
Optimal+ 3D-IC Example
A three way correlation analysis between die performance, package and die
wafer history (DNA), so we can predict the package performance prior to stacking
based on the dice DNA
Correlate C
orr
ela
te
Die
3D-IC Package
3D-IC Quality Management Challenge
Requires traceability of every component
– ID and process history
• Not every component has ID
– External supplier (heterogeneous) traceability is a challenge
Requires end-to-end data integration
– Closed loop for root cause analysis, operational monitoring and actions
– RMA and Recall management to the die level
– Quality accountability
Requires integration platform
– Test data infrastructure
– Business processes allowing necessary visibility between 3D-IC supply-chain parties
– A neutral party facilitating 3D-IC test data integration and execution
Summary
Augmented Test Data and Cross-Area/Operation infrastructure are
being leveraged to maximize Quality and Yield for 3D-IC manufacturing
• Enhanced Screening of “good” Die
• Enhanced Pairing of “good” Dice
• Quality management: RMA, Recall, Accountability
A supply-chain Integration Platform is necessary to comprehend and
leverage 3D-IC test data
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