Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction based on STG...

Resolution of Encoding Conflicts by Signal Insertion and Concurrency

Reduction based on STG Unfoldings

V. Khomenko, A. Madalinski and A. YakovlevUniversity of Newcastle upon Tyne

2

Signal Transition Graph (STG)

Dev

ice

VME BusController

ldsldtack

d

Data TransceiverBus

dsrdsw

dtack

dtack- dsr+ lds+

d-lds- ldtack- ldtack+

d+dtack+dsr-

3

Encoding conflicts

pairs of semantically different states with the same binary encoding

not distinguishable at the circuit level encoding conflicts have to be resolved before we

can proceed with synthesisTransformations: signal insertion: introduces additional internal

signal (‘memory’) helping to trace the current state

concurrency reduction: introduces additional ordering constraints making some of the conflicting states unreachable

both are needed to explore a larger design space!

4

dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

M’’ M’

dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

Example: CSC conflict

5

M’’ M’

CSC resolution: signal insertiondtack- dsr+

dtack- dsr+

dtack- dsr+

010000

ldtack- ldtack- ldtack-

000000 100000

lds- lds- lds-

010100 000100 100100

lds+

ldtack+

d+

dtack+dsr-

d-

011100 001100 101100

011111 111111 101111

101101

101001

011110

csc+

csc-

100001

6

M’’ M’

dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

CSC resolution: concurrency reduction

dtack- dsr+

lds- lds-

00110 10110

7

Framework for visualisation & interactive resolution of encoding conflicts

manual vs. automatic resolution of coding conflicts automatic can produce sub-optimal

solutions manual crucial for finding good (low-latency,

compact & elegant) synthesis solutions interactivity is good!

visualisation concepts: emphasise essential information avoid information overload

8

STG unfolding

partial order model infinite acyclic net, simple structure finite complete prefix

finite initial part of unfolding contains all the reachable states alleviates state space explosion problem more visual then state graphs proven efficient for model checking

9

core

State Graphs vs. Unfoldings

lds-

e1

e2

e3

e4

e5

e6

e7

e9

e11

e12

e10

e8

dsr+

ldtack+

dsr-

ldtack-

lds+

d+

dtack+

d-dtack-

dsr+lds+

M’M’’

M’

M’’

dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

10

Visualisation of conflicts: Height map

Core1

Core2

cores often overlap high-density areas are good candidates

for signal insertion analogy with topographic maps

A1A2A3

Core3

11

Highestpeak

Height map: an example

Core map Height map

csc+

12

Resolution of encoding conflicts

Core

t+

t-Signal insertion: insert t+ in a core t- must be added

outside the core preserving consistency

inserted transitions must not trigger an input signal

13

Concurrency reduction

addition of causal constraint, i.e. a new place

u1

t (non-input)

u2

Add a token if needed

14

Resolution of encoding conflicts

Forward concurrency reduction: bringing forward the ending point of concurrency ‘dragging’ f into the core

15

Resolution of encoding conflicts

Backward concurrency reduction: delaying starting point of concurrency ‘dragging’ f into the core

16

Resolution of encoding conflicts

Concurrency reduction: an examplep’

inputs: b,c,f; outputs: a,d,e inputs: a,b; outputs: c,d,e

forward

backward

backward

17

Overview of the resolution process

concurrency reduction

signal insertion

phase 1

phase 2

18

Cost function

cost = α1· + α2·logic – α3·core

: estimated delay caused by transformation

logic: estimated increase in complexity of logic

core: number of eliminated cores,

αi: parameters chosen by the designer

Calculated on the original unfolding prefix

19

Validity

signal insertion: well-developed, e.g. weak bisimulation

concurrency reduction: more challenging, e.g.: not even language-equivalent events can become dead introduction/disappearance of deadlocks

20

Validity aspects

I/O interface preservation the interface between circuit and its environment should be preserved

conformation no “wrong” behaviour should be introduced

liveness no “interesting” behaviour should be completely eliminated

technical restrictions boundedness, speed-independence, etc.

21

Validity notion

natural to use partial order framework when speaking about concurrency reduction!

plan: define a “valid realisation” relation on

partial order analog of traces (processes) define “valid realisation” relation on

systems

22

Validity notion: processes

can easily eliminate silent actions (e.g. internal signals) preserving causality – abstraction

a b

c d

a b

c d

23

Validity notion: processes

step 1: increasing concurrency of inputs step 2: decreasing concurrency of outputs

24

step 1: increasing concurrency of inputs

Validity notion: processes

step 2: decreasing concurrency of outputs

i1 i2 o

i1

i2

o

o1 o2 i

o1

o2

i

25

Validity notion: processes

i1 i2 o

i1

i2

o

o1 o2 i

o1

o2

i

i1 i2 o

o1

o2

i

i1 i2

o1

o2

i1

i2

o1

o2

i1

i2 o1 o2

26

Validity notion: systems

valid realisation:

e E

E’(transformed)

(original)

E

e’ E’(transformed)

(original)

27

Validity notion: systems

i2i1i1

i2

i2

i1-1

o2o1

o1

o2

o2

o1-1

o

o

o

o… …

oo -1

28

Case study: AD converter controller

signal insertion

# phase 1 phase 2 cost

6 || Laf+ to Lr-

->ready- -1

7 Laf+ -> ->ready- 0

8 ->Ar- ->ready- 0

9 -> Lr- ->ready- 1

10 Laf+ -> start- -> 1

11 Laf+ -> || ready+ to ready-

1

concurrency reduction

# causal constraint

cost

1 -3

2 -3

3 -2

4 1

Lrstart Lrready Arready Arstart

Core map

29

Conclusions

combined framework for resolution of encoding conflicts based on cores in the STG unfolding

larger design space – exploit the area/delay trade-off

novel validity condition

Future work more automation improving cost function performing transformation directly on the

unfolding prefix rather than the STG