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Reconfigurable, High Density, High Speed, Low Power, Radiation Hardened FPGA Technology
MAPLD2008S.Ramaswamy1, Leonard Rockett1,, Dinu Patel1, Steven Danziger1
Rajit Manohar2, Clinton W. Kelly, IV2, John Lofton Holt2, V. Ekanayake2, Dan Elftmann2
Ken LaBel, Melanie Berg etc. NASA3
1BAE SYSTEMS, 9300 Wellington Road, Manassas, VA, 20110, USA2Achronix Semiconductor Corporation, 333 W. San Carlos Street, San Jose, CA, 95110, USA
3NASA Goddard
2
Agenda
• RHFPGA Roadmap• RHFPGA Product Features• Achronix Technology Overview• BAE Radiation Hardened Process Technology Overview• Program Status / Summary
3
Radiation Hardened FPGA Roadmap
• Heritage: Actel ONO RH1280 and RH1020• Anti-fuse technology, non-volatile• 0.8µm RH CMOS, 5V Supply• In production since 1996, over 25,000 shipped
• M2M Anti-fuse Technology:• 250K-gate (RHAX250-S)• RH15 CMOS, 1.5V Core / 3.3V I/O• Flight Orders in 2009
• ≥3M-gate, re-configurable, non-volatile• Radiation Hardened, high speed • RH15 CMOS, 1.5V Core / 3.3V I/O• Projected qualification starts in 2009
Rad Hard FPGA Product
Past
Present
Future
Re-install in progress
Entry Vehicle
4
RHFPGA Product Features• TID tolerance of > 1Mrad Si
• SEU immunity < 10-11errors/bit-day
• System speeds > 300MHz
• Support of RADHARD IOs and RAMs for integration into Systems
• Reconfigurable/Reprogrammable
• Low Power
• Extreme Temperature Operation
• Non Volatile
• EMP Protected
• Full Compatibility with Existing EDA Tools
• Product Name -> Radrunner
5
• Privately held fabless semiconductor company founded in New York in 2004
• Achronix has received $34.4M Series A funding
• Founders developed technology in 1998 at Cornell University
• Headquartered in San Jose, CA
• Working 90 and 180 nm prototype silicon
• Partnerships with the world leading foundry TSMC, BAE Systems and numerous IP & EDA vendors
• 65 nm commercial FPGA silicon has been received from TSMC; currently shipping
• All Key IP’s protected by patents
Achronix Company Overview
6
Reconfigurable RHFPGA Proof of ConceptKey Roles to support Reconfigurable RHFPGA Proof of Concept:
Achronix:•• Product Design
• Architecture Definition• Reprogrammable Fabric, S-Frame
• Incorporate BAE RHSRAM• Final Design & Simulation
•• Product Testing Support
BAE:• Design Custom Blocks
• Physical Design/Integration• Wafer Processing/Characterization
• Wafer Sort and Packaging Tests• Packaging
• Radiation Testing
POC ReadyOption for QML Qualification
Commence Enhancement of the FPGA
ACX RHFPGA Product Development…. A collaborative effort
Product definition
• Sales and Marketing
7
Achronix RHFPGA Technology
8
Achronix Core Technology
• Core contains ‘picoPIPE’ technology used for both logic and routing
– You do not need to know the details in order to benefit from this
• Fully synchronous I/O ‘frame’ surrounds the core
• picoPIPE technology is used to implement synchronous hardware
– A design is input using a HDL such as RTL– The RTL does not need to be targeted to
picoPIPE technology
Achronix FPGA
Globally-clocked
logic ‘frame’
picoPIPElogic core
Looks like a regular FPGA, but has approx 4x throughput
9
Data 0
Data 1
Acknowledge
picoPIPE pipeline stage
TxRx TxRx
Data Tokens
• In globally-clocked logic, a data value at a clock edge can be considered as a “Data Token”
– Only valid data (data at a clock edge) is propagated
– Hence each register output’s a new Data Token (value) at every clock edge
picoPIPE logic also contains Data Tokens
– Each data token uses 2 signals instead of 1
– Data validation (clock-like functionality) is performed using acknowledge instead of a global clock
D Q
clk
D Q
Globally clocked pipeline stage
Traditional FPGA
Achronix FPGA
10
More on Throughput
Traditional FPGA• Globally Clocked Logic is not balanced• The clock rate must allow for the slowest path in
the entire clock domain• Any combinatorial logic faster than the slowest
path (by definition, all remaining logic) waits for the slowest one to finish
Globally-clocked Logic
1.5
GH
z37
5 M
Hz
Achronix FPGA Achronix technology allows fine-grained
pipelining Allows data rate to be much faster Pipelining also allows more data values in
flight Equates to faster throughput
Trad
ition
al
Ach
roni
x picoPIPE Logic
0ps .67ns 1.3ns 2.0ns 2.7ns 3.3ns 4ns 4.7ns 5.3ns 6ns 6.7ns 7.3ns 8ns 8.7ns 9.3ns 10ns 10.7ns
D Q D QD Q
clk
1234
12345678910111213141516
11
Interconnect
RLB RLB RLB
RLB RLB RLB
RLB RLB RLB
Fam
iliar
Sili
con
4-inputLUT
4-inputLUT
4-inputLUT
4-inputLUT
4-inputLUT
4-inputLUT
4-inputLUT
4-inputLUT
Familiar Silicon & Familiar Tools
• Traditional 4-input LUT architecture
– With GHz performance• SRAM-based reprogrammable
FPGA– Uses BAE’s Radiation
Hardened SRAM cell
Synplify-Pro and Mentor Precision Synthesis Flows
Full compatibility with existing third party simulation, debug, and verification toolsFa
mili
ar T
ools
12
Trading off Speed for Power Dissipation: V2f
0.00
500.00
1000.00
1500.00
2000.00
2500.00
0.00%
20.00%
40.00%
60.00%
80.00%
100.00%
120.00%
0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20
Spee
d (M
Hz)
Ope
ratin
g Po
wer
(% o
f M
ax)
Supply Voltage
Speed & Power Scaling
Operating Power
Speed
Nominal 1.2V 2 GHz78% less @ 0.8V 1 GHz97% less @ 0.6V 250 MHz
90nm Test Silicon
The robustness properties of the Achronix picoPIPE technology allow it to operate reliably over both a wide Voltage and Temperature range!
13
Copy 1
Copy 2
Loca
l Vot
ing
Distance avoids both being affected
by same event
Achronix Patented SEE Mitigation Methodology: Redundancy Voting Circuits (RVC)
• Local voting waits until both copies agree– no SEE, values will agree at the voter,
tokens propagate– When SEE occurs values won’t agree at voter,
local voter blocks token propagation – After event energy dissipates the upset circuit
value is resolved to the correct value and tokens propagate
• Redundancy Voting Circuits (RVC)– Two copies of all circuits are implemented– Copies are non-adjacent to avoid the risk of a
single upset affecting both– Every stage (combinatorial and state) has local
voting mechanism
14
• Radiation Hardened By Design (RHBD) circuit techniques portable to any foundry to enable extremely low SEU and SET rates (< 10-11 upsets/bit day)– Circuit technique proven thru SEE testing at 150 nm applicable to any
process node
RVC Proof of Concept Test Chip
150 nm BAE Systems test chips
Where
Who
Result No observed SET or SEU events in SEE testing up to a LET threshold of 55 MeV-cm²/mg
Proof of Concept Vehicle
15
Rad-Hard FPGA Test Chip & Patterns
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
0,0 1,0 2,0 3,0
0,1 1,1 2,1 3,1
0,2 1,2 2,2 3,2
0,3 1,3 2,3 3,3
0 1
0
1 0
1
0 1
0
1
0101
0
1
Defined goal of initial radiation test was to prove that tokens continue to propagate in the event of heavy ion impact
Test Chip contained a 4x4 array of FPGA Tiles implemented with RVC picoPIPE elements
One dedicated tile had an 8 bit counter (implemented in RVC) on output acknowledge to observe the functioning of the various FPGA configurations at a reasonable frequency with standard I/O
Five different FPGA patterns utilized during testing
16
Summary: Heavy Ion SEE Test of BAE-Achronix Rad-Hard FPGA Test Chip
Testing completed by NASA at Texas A&M University Cyclotron Single Event Effects Test Facility (SEETF) – Test Date: August 14th, 2007 – Sample size: Three devices tested including one control not
exposed to the radiation source– Flux: 1 x103 to 1 x104 particles/cm2/s – Fluence: 5x106 particles/cm2
– Test Angles: Normal, 45 degree SEL Analysis
– No SEL observed through tests with temperatures up to 74 °C and LET of 55 MeV*cm2/mg
SEE Data and Analysis– No SEFI observed for all tests run– Tokens continued to propagate throughout testing
17
BAE RHFPGA Process Technology
18
RHFPGA Technology (RH15F) Features
Radiation Hardness Assurance LevelsEnvironmentTotal Dose (rad(Si)) 1MSEU (errors/bit-day) 1E-11SEL (MeV-cm2/mg) 120Neutron Fluence (n/cm2) 1E13Prompt Dose Upset (rad(Si)/s) 1E9Prompt Dose Survival (rad(Si)/s) 1E12
Key FeaturesFeatures: RH15Isolation STIThin Oxide / DGO Devices 26 Å / 70 ÅVdd Options 1.5 V / 1.8 V / 3.3 VMetal Levels 7Capacitors YesResistors YesC4 / Wirebond Y/Y
19
16M SRAM – Next-Generation Strategic RH SRAM
RH15F Process Maturity - Memory
15-20 ns
0.15 µm CMOS
16 mm by 16 mm
1.5 V + / - 10% core2.5 or 3.3 V + / - 10% I/O
10 mW/MHz at 1.5V (per die)100 mW standby
-55oC to +125oC
23.2 mm by 26.2 mm by 6.0 mm100 pin Flat Pack (5-high stack)
Total Ionizing Dose > 1Mrad(Si)Prompt Dose > 1E9 rad(Si)/secSEU < 1E-12 errors / bit-day (W.C. 90% GEO)Latchup: Immune
TBD
Prototype and Flight flows
2Mx8 die – single chip package2Mx32 4-high package2Mx40 5-high package512Kx32 die – single chip package
Access Time
Process Technology
Die Size
Power Supply
Power Dissipation
Temperature Range
Packaging
Radiation Hardness
ESD
Screening level
Organization
Transistors 113,070,511HVT NFETS 74,422,289HVT PFETS 38,645,756DGO NFETS 1,630DGO PFETS 836R2 Resistors 36,410,528
Q2 Capacitors 18,205,264
Total ILCs 1,063,783,005CA 298,967,451CT 226,146,395V1 212,067,749V2 242,233,858V3 82,209,612V4 1,011,258V5 506,746V6 639,936
Configuration Memory Cell for RHFPGA uses the 16M SRAM Cell
20
16 Meg SRAM SEU Response SN 4Fail Mode: Single Cell Upset
1.E-15
1.E-14
1.E-13
1.E-12
1.E-11
0 20 40 60 80 100 120LET (MeV/mg/cm^2)
StaticStatic - limiting cross sectionDynamic - none observedDynamic - limiting cross section
Cro
ss-s
ectio
n
J Rodgers / J ross 12/4/2007
16M SRAM Heavy Ion Test Results Memory Cell Upset
Standby mode– periodic reads
Background 6e-16 u/b-d; Solar Flare 4e-13 u/b-d
No Proton UpsetsNo Latchup
SEU for Memory Cell Exceeds RHFPGA SEU Targets
21
RH15F Qualification Vehicle (16MSRAM)
Parameter Requirement Goal Achieved Outlook
Operating Speed - worst case 125C and post radiation ≤ 20 ns ≤ 15 ns ≤ 15 ns G
Operating Temperature RangeFull PerformanceFunctionality
0 to 80C -55C to 125C
-55C to 125CSame
-55C to 125C G
Standby Current - worst case 125C and post radiation ≤ 60 mA ≤ 40 mA ≤ 40 mA G
SEU (upsets/bit-day) < 1E-10 < 1E-11 << 1E-12 G
Total Ionizing Dose - Gamma ≥ 0.5 Mrad ≥ 1Mrad ≥ 1Mrad G
Prompt Dose Upset (rad/sec) ≥ 1E9 ≥ 1E9Planned on
5-high stacks
G
Survivability (rad/sec) 1E12 1E12 G
Characterization completeQualification in progress, Prototypes Samples Available
22
RHFPGA Package Definition
• Substrate– ceramic 32 mm x 32 mm
• 32 mm x 32 mm Column Grid Array
– 1.27 mm pitch
– 624 Total I/O
• Capacitors
–Sizing suggests 16 Low Inductance Flip Chip Capacitor Sites
–Can be used to support several different voltages
• Hermetic Seam Weld Sealing
23
RHFPGA Preliminary Engineering Estimate of Part Resources
Dev
ice
Res
ourc
esP
acka
ge
286CQ340
Radrunner Family (150 nm)
Device Name RDR500 RDR1000
LUT 4,320 8,640
Number of 18 Kbit Block RAM 5 10
Block RAM (Kbit) 90 180
Number of PLL 4 4
SpaceWire Interfaces 4 7
User Programmable I/O 336 384
CCGA624 (32 mm x 32 mm) 384
Design under optimization to maximize RHFPGA Resources
24
SUMMARY
Program Outlook Overall Positive for Initial POC Device 2Q09
• Program Fulfills Critical Need for Reconfigurable RH FPGAs for Strategic Applications
• Excellent Partnership between BAE Systems and Achronix Ongoing
• Initial Achronix Commercial Chip First Pass Success
• Test Chip Functionality Demonstrated, Radiation Testing Successful
• Design Activities Continuing with No Technical Concerns
• Plans In Place for Further Device Enhancements
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