Prof. Z Ghassemlooy ICEE2006, Iran Investigation of Header Extraction Based on Symmetrical...

Prof. Z Ghassemlooy ICEE2006, Iran

Investigation of Header Extraction Based on Symmetrical Mach-Zehnder Switch and Pulse Position Modulation for All-Optical

Packet-Switched Nnetworks

Z. Ghassemlooy, H. Le Minh,and Wai Pang Ng

Optical Communications Research Group

Northumbria University, UKhttp://soe.unn.ac.uk/ocr/

Contents

Overview of header processing in optical networks

Header processing based on pulse-position modulation (PPM) and the proposed node architecture

Header extraction module (HEM)

Simulation results: HEM, Node and Network Performances

Summary

Optical Communication Network (OCN)

Solution: All-optical processing & switching Photonic network

1P

100T

10T

1T

100G

10G

1G

100M1995 2000 2005 2010

Year

Demand traffic[bit/s]

Voice

Data

Total

NEC-2001

- Future OCNs: faster signal processing and switching to cope with the increase of the demanding network traffic

- Existing OCNs: depends on electronic devices for processing the packet address to obtain the routing path. However, the limitation of electronic response will cause the speed bottleneck

Future OCNs

Optical transparent path

- Future OCN will have the processing and switching data packets entirely in optical domain, i.e. generate optical transparent path for routing data packets

Require: compact and scalable processing scheme

Current All-optical Processing Scheme

All-optical logic gates All-optical correlators

Addresspatterns

Decimalvalue

Output ports

0 0 0 0 0 Port 2

0 0 0 1 1 Port 1

0 0 1 0 2 Port 3

0 0 1 1 3 Port 1

0 1 0 0 4 Port 3

0 1 0 1 5 Port 2

0 1 1 0 6 Port 2

0 1 1 1 7 Port 1

1 0 0 0 8 Port 3

1 0 0 1 9 Port 2

1 0 1 0 10 Port 2

1 0 1 1 11 Port 3

1 1 0 0 12 Port 1

1 1 0 1 13 Port 1

1 1 1 0 14 Port 2

1 1 1 1 15 Port 1

Routing table (RT)Example: N = 4, node with M = 3

?Port 1

Port 2

Port 3

N-bit

Problems:

• Large size routing table increased processing time• Optical device complexity poor scalability

Solution:

• Reduce the size of the routing table

Proposed Node with PPM Processing

Clock extraction: synchronize the arrival of data packet and the node processing S-P converter: convert the serial address bits to parallel bits PPM-ACM: (PPM address conversion module): convert binary address to the PPM-converted address PPRT: store M entries (M PPM frames) Switch synchronisation: synchronise SW with data packet All-optical switch: controlled by matching signals to open the correct SW

Clock extraction

S-PConverter

PPM-ACM

&MM

SW1

SW2

SWM

Header processing unit

1

2

M

All-optical switch

...

...

...

...

Data H C lk

PPRT

Entry 1

Entry 2

Entry M ...

&11

&22

Sw

itch

Sy

nc.

Sw

itch

Sy

nc.

Data H C lk

H

PPM – Concept/Operation

a0 a1 a2 a3payload

Header

(packet address)

Clk

Data packet

Addressextraction

PPM(a) (b)

PPM-HEM

No of slots = 2M

PPRT Generation

Is self-initialised with the extracted clock pulse. The M entries are filled by:

– Single optical pulse + Array of 2N optical delay lines; Or,

– M pattern generators + M optical modulators.

PPM Based Routing Table

Grouping address patterns having the same output ports

Each new pulse-position routing table (PPRT) entry has optical pulses at the positions corresponding to the decimal values of group’s patterns

Pulse-position routing table (N = 4, M = 3)

Header Correlation

Single AND operation is required for matching PPM-address and multiple address patterns (PPRT entry)

Processing-time gain:

Matched

SMZ Based AND Gate

A/B 0 1

0 0 0

1 0 1

Implementation:

Using optical interferometer configuration + optical nonlinear devices

A

BA×B

SOA1

SOA2

Symmetric Mach-Zehnder Interferometer (SMZI)

HEM: Serial-to-parallel Conversion (SPC)

a1 a2 a3a0

a3

a2

a1

a0SMZ0

SPC

Clk

SMZ3

SMZ2

SMZ1

1- SPC diagram

2- SMZ interferometer

Problems:

1-Residual power due

to large TSW

2-Low extinction ratio

~ 10 to 15 dB

SOA1

SOA2

(Extracted)

TSW

HEM: PPM-ACM

1- N-bit address-codeword:

A = [ai {0,1}], i = 0, …, N–1

2- PPM-format address:

y(t) = x(t + iai2iTs)

SPC

Problem:

Multiple pulse at the PCM-ACM output instead of only y(t)

due to low switching extinction ratio of SW

HEM: PPM-ACM

SWSW

Achieved high switching extinction ratio for SW (>30 dB)

Solution: Combine 2 SMZs in their complement switching modes

by single control pulse

1- SMZ1 in ON state SMZ2 in OFF state

2- SMZ1 in OFF state SMZ2 in ON state

Hall-Optical Switch

1 MSMZ-1

SMZ-2

SMZ-M

…

CP1

CP2

CPM

1

2

M

Simulation Results – HEM Performance

Parameters Values Parameters Values

SOA length – LSOA 500 10-6 m Carrier density transparency

1.4 1024 m-3

SOA width 3 10-6 m Recombined Const. A 1.43 108 s-1

SOA height 80 10-9 m Recombined Const. B 1 10-16 m3s-1

Linewidth enhancement 4 Recombined Const. C 3 10-41 m6s-1

Confinement factor 0.15 Initial carrier density 3 1024 m-3

Differential gain 2.78 10-20 m2

Injected current 150 mA

Internal losses 40 102 m-1 Group velocity – Vg 3 108 / 3.5 ms-

1

SOA parameters

Packet parameters

Parameters Values Parameters Values

Number of bits in the header N 4 Bit rate of the data packet 80 Gb/s

Data pulse width FWHM 1 ps PPM slot duration Ts 6.25 ps

Simulation Results – HEM Performance

1 2 3 4 5 6 7 80

10

20

30

40

50

60

TSW

(ps)

Ext

inct

ion

rat

io r

e-y

(d

B)

Best re-y

(among 16 patterns)

Worst re-y

(among 16 patterns)

SPC

The PPM-ACM extinction ratio between y(t) power and undesired multiple-pulse at PPM-ACM output against Tsw for the best and worst cases (among 2N)

This ratio ~ 30 dB for TSW = 1ps

Simulation Results – Node Performance

Simulation parametersSimulation parameters ValuesValues

Address length N 5

Number of outputs M 3

Bit rate 50 Gb/s

Payload 16 bits

Packet gap 2 ns

Pulse width FWHM 1 ps

Pulse’s power peak 2 mW

Wavelength 1554 nm

PPM slot duration Ts 5 ps

For an all-optical core network up to 25 = 32 nodes

... 32 node network

0

1

17

29

8

15 00000

0001

10001

01000

11101

01111

Simulation Results – Node Performance

Demonstrate the PPM processing and Tx modes

PPRT with 3 entries:

Simulation Results – Node Performance

Input

Output 1

Output 2

Output 3

Port 1

Port 2

Port 3

Input

Simulation Results – Node Performance

0 1 1 1 0Packet with address 01110

PPM-converted address

PPRT entry 1

Synchronized matching pulse

Simulation Results – Network Performance

OS

HP

…

# Source

Source Edge-node

Target Edge-node

OS

HP

0,

0

ase

in

P

PG

attn.

attn.

# Target

OSNR0 OSNR1 OSNR2 OSNRH

Optical fiber

Optical pre-amplifier

attn. Attenuator

inP

0,aseP

OS

HP

attn. 0G 01 L 1G

1,aseP 2G

2,aseP 11 L

HL1 11 HL

HG HaseP ,

0,0

00

1 ase

in

PL

PLG

1,0,01

010

asease

in

PPLG

PLGG

1,10,101

1010

1 asease

in

PLPLLG

PLLGG

2,1,120,1021

10210

aseasease

in

PPLGPLLGG

PLLGGG

…

1- Multiple-hop OSNR

2- Predicted & simulated OSNRs

0 1 2 3 4 510

15

20

25

30

35

40

45

Number of hops

OS

NR

(d

B)

Theoretical, OSNR0 = 28dB

Theoretical, OSNR0 = 34dB

Theoretical, OSNR0 = 40dB

Simulation, OSNR0 = 28dB

Simulation, OSNR0 = 34dB

Simulation, OSNR0 = 40dB

Conclusions

PPM processing scheme– Reduces the required processing time– Provides the scalability: adding/dropping network nodes

and node outputs

Applications: – All-optical core/backbone networks (N > M ~ 3-6)– Optical bypass router (electrical router + optical bypass

router)

Challenges: – Optical switch with long and variable switching window– Timing jitter and received pulse dispersion

Acknowledgements

Northumbria University for sponsoring the research work

Thank You!

Node with Multicast Tx Mode

Clock extraction

S-PConverter

PPM-ACM

&MM

SW1

SW2

SWM

Header processing unit

1

2

M

All-optical switch

...

...

...

...

Data H C lk

PPRT

Entry 1

Entry 2

Entry M ...

&11

&22

Sw

itch

Sy

nc.

Data H C lk

H

Data H C lk