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PLL Phase Noise Figures of Merit TI Precision Labs โ Clocks and Timing
Presented by Dean Banerjee
Prepared by Liam Keese
1
Phase lock loop (PLL) overview
2
R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
Z(s)s
KVCO
+KPD
-
Phase lock loop (PLL) transfer functions
3
fVCO
1/N
1/RZ(s)
sKVCO
+KPD
-
Block Transfer Function
OSC 1
๐ โ
๐บ(๐ )
1 + ๐บ(๐ ) โ ๐ป
R/N
Dividers
๐บ(๐ )
1 + ๐บ(๐ ) โ ๐ป
Phase
Detector
1
๐พ๐๐ทโ
๐บ(๐ )
1 + ๐บ(๐ ) โ ๐ป
VCO 1
1 + ๐บ(๐ ) โ ๐ป
๐ฏ ๐ = ๐ฏ = ๐/๐ต
๐ฎ ๐ = ๐ฒ๐ท๐ซ ร ๐(๐) ร ๐ฒ๐ฝ๐ช๐ถ
๐
๐ = ๐ โ ๐๐ ๐
Reference oscillator noise transfer function
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Block Transfer
Function
Response Low Frequency
Response
High Frequency
Response
OSC 1
๐ โ
๐บ(๐ )
1 + ๐บ(๐ ) โ ๐ป
Low Pass 20 โ log (๐/๐ ) 20 โ log (๐บ(๐ )/๐ )
BW
20 x log(N/R)G
ain
(d
B)
Offset Frequency (Hz)
| G(s) |
1 R โ
G(s)1 + G(s) โ H
1 R โ
Feedback N divider noise transfer function
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Block Transfer
Function
Response Low Frequency
Response
High Frequency
Response
N (or R)
Divider
๐บ(๐ )
1 + ๐บ(๐ ) โ ๐ป
Low Pass 20 โ log (๐) 20 โ log (๐บ(๐ ))
BW
20 x log(N)G
ain
(d
B)
Offset Frequency (Hz)
| G(s) |
G(s)1 + G(s) โ H
Phase det./charge pump noise transfer function
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Block Transfer
Function
Response Low Frequency
Response
High Frequency
Response
Phase Det./
CP gain
1
๐พ๐๐ทโ
๐บ(๐ )
1 + ๐บ(๐ ) โ ๐ป
Low Pass 20 โ log (๐/๐พ๐๐ท) 20 โ log (๐บ(๐ )/๐พ๐๐ท)
BW
20 x log(N/KPD)G
ain
(d
B)
Offset Frequency (Hz)
| G(s) |
1 KPD
โ
G(s)1 + G(s) โ H
1 KPD
โ
VCO noise transfer function
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Block Transfer
Function
Response Low Frequency
Response
High Frequency
Response
VCO 1
1 + ๐บ(๐ ) โ ๐ป
High Pass โ20 โ log (๐บ(๐ )) 1
BW
1G
ain
(d
B)
Offset Frequency (Hz)
1
1 + G(s) โ H
1
G(s)
N โ
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
0.1 1 10 100 1000 10000 100000
Ph
ase N
ois
e (
dB
c/H
z)
Offset (kHz)
PLL VCO Reference Total
PLL closed loop noise sources
The size of these regions will change depending on loop bandwidth
Ref OSC PLL VCO
PLL normalized phase noise
9
Log(Frequency)
BW
Everything Except VCO
VCO
Ga
in (
dB
)
0
20โlog(N)
โข PLL flat noise FOM (PN1Hz)
โ PLL noise floor normalized to1 Hz
โ N-counter added noise = 20 log (N)
โข PLL flicker noise (PN10kHz)
โ Usually dominates at offset below 1 kHz
โ PLL 1/f normalized to 1 GHz output and 10kHz offset
PLL noise simulation
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โข PLL FOM
โ PN1Hz = PN โ 20 โ log(N) โ 10 โ log(fPD)
โข PLL Flicker
โ PN10kHz = PN(ฮf) -20 โ log(fout/1GHz)
-10 โ log(10kHz/ ฮf)
PLL phase noise shaping levers
PLL Functional Block To minimize Noise
contributionโฆ
Why?
Phase Detector/Charge
Pump
Maximize charge pump gain
(KPD) (up to a certain point)
The phase detector noise
contribution is proportional to
1/(KPD)2
R-counter and N-counter
divide ratios
Maximize phase detector
compare frequency this
minimizes N
The noise contribution of the
R and N dividers is
proportional to N2.
Reference oscillator Use highest frequency practical
and use R > 1 if possible. If
deciding between maximizing R
and minimizing N, minimize N.
The noise contribution from
the reference oscillator is
proportional to (N/R)2
To find more technical resources and search products, visit ti.com/clocks
12
Quiz
โข True or false: Reducing N-divider value will decrease PLL noise by 20log(N)
โข True or false: The reference oscillator does not contribute to PLL in band noise
โข True or false: Increasing the charge pump current setting will reduce PLL noise
โข True or false: The VCO tuning constant KVCO only has an effect on noise
outside of the PLL loop bandwidth
13
Quiz
โข True or false: Reducing N-divider value will decrease PLL noise by 20log(N)
โข True or false: The reference oscillator does not contribute to PLL in band noise
โข True or false: Increasing the charge pump current setting will reduce PLL noise
โข True or false: The VCO tuning constant KVCO only has an effect on noise
outside of the PLL loop bandwidth
14
PLL Transient Response Quiz TI Precision Labs โ Clocks and Timing
Presented by Dean Banerjee
Prepared by Vibhu Vanjari
1
Quiz
โข True or False: The phase margin is the phase of the open loop transfer function
when the gain of the PLL is equal to 0 dB.
โข True or False: Phase margins under 30ยบ should be avoided to enhance the
stability of the PLL and minimize ringing.
โข True or False: Larger bandwidths lead to shorter lock times.
2
Quiz
โข True or False: The phase margin is the phase of the open loop transfer function
when the gain of the PLL is equal to 0 dB.
โ The phase margin is the distance of the phase from -180 degrees when the gain of
the PLL is equal to 0 dB.
โข True or False: Phase margins under 30ยบ should be avoided to enhance the
stability of the PLL, and minimize ringing.
โ Phase margins under 30ยบ can lead to instability, peaking in the closed loop filter
response, and ringing in the transient response.
โข True or False: Larger bandwidths lead to shorter lock times.
โ Wider loop bandwidths allow the PLL to track changes in frequency faster.
3
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