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Michael LebbyProfessor, Glyndwr University
CEO, OneChip Photonics
Director Corp Relations, USC
PIC: the next generation IC…
Within photonics we should
focus on 3 takeaways…
• Will photonics enables many things and will be part of our lifestyle?
• Will photonics will be integrated – just like ICs 50years ago and will it drive new product designs?
• Is integrated photonics a paradigm shift for the tech community?
Now let’s look at the details…
Agenda
• Introduction to photonics
• Global markets for photonics
– Lighting, solar, communications, displays
• Integrated photonics applications
– Datacenters, medical, consumer
• Is photonics the next generation IC?
– InP, SiP, PP platforms
• Summary
The impact of
photonics on our
lifestyle…
A decade ago what were
we thinking at OIDA?
Is photonics our lifestyle? Everything has happened…
A decade ago: a truly green vehicle
with solar/LEDs/battery…
High tech in 2005…Sources: Philips Lumileds
Today photonics enables a
future lifestyle (Japanese view)
Through the visualization of unseen things…Sources: OIDA research, IOA
• Atmosphere
• Hidden objects
• Bacteria
• Viruses
• Safety
• Health
• Comms
• Internet
In a decade: driverless cars…
photonics everywhere
From sensors, displays, fiber, LEDs, lasers…
In a decade: Utilizing solar
energy will be more important…
• CPV produces
more electricity in
areas of high direct
normal irradiation
(DNI) than
conventional PV
systems
• CPV advantages:
– High insolation
– Low diffuse to
direct ratio
– Annual average
DNR 6.9kW/m2
per day (High)
Sources: Solar Systems
Will solar CPV (concentrated PV) accelerate?
In a decade: Photonics in
renewables…burst through barriers
• Barrier: Scaling up renewable GW in our infrastructure– Cost of renewable electricity
– Performance and reliability
– Infrastructure robustness and capacity
– Simplfying dispatchable energy (wind)
• Barrier: Obsoleting petroleum (fossil) based fuels– Cellulosic ethanol cost (wood, grass, non-edible plants)
– Life cycle sustainability of biofuels
– Fuels infrastructure, standards, metrics
– Demand, utilization and intermediate blends
• Barrier: Shrinking energy demand of buildings, automotives, etc– Coordinated implementation of model building codes
– Market does not value efficiency
– Cost of energy efficient technologies
– Performance and reliability of new technologies
Sources: NREL, Dan Arvizu
We need decade programs: attitude cultural
Global markets
for photonics
Photonics categories:
broad and varied
Photonics
Industry
OE/photonic
components- HBLED, LED module
- CCD, Image sensor
- Solar cell
Flat panel displays- LCD (TFT, TN, STN)
- PDP, VFD, OLED
- Microdisplay, LTPS TFT
Optical I/O devices- DSC, copier, fax
- Laser printer, bar code
- Scanner
Optical storage- CD, DVD, Bluray
- Optical disk player for PC
- RW disk
Optical fiber comms- Optical cable, passives
- Optical comms equip
- Optical actives, modules
Precision optics- Lasers, optical lens
- Precision optical lens
- Laser app equip
Solid state lighting- In-organic LED. module
- Organic LED, module
Large opportunity for integrationSources: OIDA research, IOA
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Re
ven
ue
($B
illio
n) Photonic lighting
Precision optical lens and laser
Optical fiber comm
Optical storage
Optical I/O devices
Flat panel displays
Optical components
Global photonics market
(USA perspective)
• Growing from $353B in 2009 to $516B in 2021
– FPD big driver 3.9% CAGR; SSL still best growth at 29% CAGR
Sources: OIDA research, IOA
Outlook is strong for photonics…
$516B
2021
Global photonics market
(Taiwan perspective)
• Growing from $551B in 2012 to $649B in 2015 (~$850B in 2021)
– FPD remains big segment at $196B; lighting growing to $43B by 2015
After 2009; steady increase towards $1T mktSource: IOA
$430B
$649B$551B
Photonics in Japan
• Domestic production in Japan ~$100B
• Solar and lighting strong growth
Rise of Asia in photonics affecting JapanSource: IOA, OITDA
2008
PV
GDP
Domestic photonics production
Global solar markets
(Taiwan perspective)
Solar corrected, but now in growth again
• Market growing quickly to 50GW in 2015
• Production corrected in 2011; now at $148B
Source: IOA
CorrectionGW $B
Lighting market growing steadily…
(Taiwan view)
Solid state lighting is not going away…Source: IOA
• By 2020 lighting market is 65%!
– LED 54% and OLED 11%
• By 2015 LED/OLED combine for $43B
$B
$B
2020
What are the
drivers for the
next generation
communications?
Network as a catalyst for
change in lifestyle
• Social lifestyle personal lifestyle
Before
Computer centric
Experts level
Data exchange
Exchange
Today
Network centric
Trained level
Archival access
Datacenter
Future
User centric
Pedestrian level
Cloud access
Large datacenter
Source: M IC Japan, Fujitsu, NTT; OIDA Research
Lifestyle evolves through heavy use of data and traffic
Social networking user growth is
driving bandwidth, datacenters, infrastructure
Trend is not slowing: its accelerating…Source: dreamgrow.com
>1Billion
from Exa to Zetta-bytes…
Source: Cisco, pcmag.com
Driven by consumer internet…
Kilo = 103
Mega = 106
Giga = 109
Tera = 1012
Peta = 1015
Exa = 1018
Zetta = 1021
Yotta = 1024
Only 60+ Exabytes/month in 2014 and growing…
Internet traffic to reach 1.3Zettabytes by 2016…
107Exabytes
2016
VNI = Visual networking index
Now we have the
emergence of
new traffic
patterns…
Evolution of a new
datacenter fabric
Cloud era data
center fabric3.Modern spine/leaf
data center2.Legacy multi-tier
data center1.
5% of traffic EW Up to 75% of traffic EW
Source: Cisco and Juniper
N-S flow – legacy
Low connections
E-W flow – virtualization
Many connectionsOmni-flow fabric
Enormous connections
78% CAGR of internet bandwidth growth to 2016
Which means we
have to upgrade
the hubs…
It was telephone exchanges
in the 60s…
Telephone exchanges: large buildings to aggregate traffic…Source: GPO
Noisy: 1000s of crickets…”strowger” switch
• ~100kbps ‘board/rack’ aggregate
• ~X10,000,000 slower than…
Today everything is
going datacenter…
Google today…ubiquitous tomorrowSource: Google
Sound of fans whirring – the comm’s hub of the future
• ~1Tbps board aggregate
We have to
address
datacenter pain
points…
DC: engineering headaches
with pain points
LARGER
FASTER
GREENER
DENSER
Single Mode
Fiber
400G plus
< 2W/port
Smallest footprint
(QSFP, microQ)
photonics is the
ideal platform to
achieve these
specs
Photonics is going to
another level by adding
electronics (OEIC)
Advanced technology will win datacenter…
DC = Datacenter
Datacenter
Single mode fiber wins
in the datacenter
500m 2km 10km
100m
Modern data center requires 500m ~ 2km
STOP
Multi Mode Fiber (SR)
Single Mode Fiber (LR)
100G
100/400G becomes more ubiquitous using SM fiber
100G
VCSEL laser
DFB laser
Standards at
400Gbps for
datacenters
Company Method Gbit/s # Demonstrated Comments
JDSU/Fujitsu DMT 100 4 TOSA with integrated four
DML TOSA with multiplexer
(EML and MZM options)
BER ok but marginal and uses
expensive Fujitsu DAC
Huawei PAM4
DMT
NRZ
56 8 NRZ with four EML TOSA Prefer 56 Gbaud to 112 Gbaud for
reasons of limited bit error rate
Oclaro NRZ
PAM4
50
100
8
4
No 8 laser TOSA needs 24% more
power than 4 laser TOSA
Mitsubishi /
Oclaro
NRZ 50 8 EML TOSA single channel Preferred – best link budget
Cisco PAM4 56 8 Lithium niobate single
channel
NeoPhotonics PAM4 112 4 Single components LiNbO3 Limited by DAC bandwidth
NeoPhotonics PAM4 56 8 Single Components EAM
NEC PAM4
NRZ
56 8 No
NEC PAM4
DMT
112 4 No
Hitachi PAM4 100 4 EML and LiNbO3 comparison EML version preferred solution
Standards activity
for 400Gbps
50Gbps is a common theme…
Photonics integration
drives miniaturization
(and higher traffic
capacity)
The quest for smaller boxes
(and 100Tbps)
2012 2013 20142011 2015
Switch Density Tbps
400G
800G
1T
10T
CFP
CFP/2
CFP/4
QSFP LR4 200Gbps (4x50)
CFP
CFP/2
CFP/4
QSFP
Source: Molex (modified to fit in the context)
OneChip
OEIC engine
Industry
Miniaturization enables the roadmap: PIC drives it…
Ultra-small, ultra-fast
OEIC engine for
Micro QSFP
Line rate 50Gbps
Initially 4 channels (4x50) = 200Gbps
Later 8 channels(8x50) = 400Gbps
100T
14 © 2013 Ethernet Alliance
Why do we integrate?
! Density!
SX1016 – 640 Gb/s: 64 Port 10 GE Switch
SX6036 – 2 Tb/s: 36 Port QSFP+ Switch
Many Terabit Switch
SFP and QSFP pluggable transceivers provide excellent front panel density, but they do have limits
QSFP 400Gbps (8x50)
Micro QSFP 800Gbps (16x50)
2016
PIC OSA engine(Photonic Integrated Circuit,
Optical sub-assembly)
Standard
Tx/Rx Modules
Solving the “compactness”
problem
144 mm2
PLC
Discrete
solution10.2 mm2
SEI InP PIC
(Oct 2013)6.75 mm2
(1.5x4.5)
OCP solution
Integrated photonics drives higher traffic capacitySource: Optoplex, SEI
Traffic is not the
only application
for integrated
photonics…
Medical applications:
Optical coherence tomography
Integration enables miniaturization SiP PIC (visible λ)?Source: USDHHS, Topcon, Envisonoptical , Wikiepedia, Photonics.com, GE, Intel
Sarcoma
Eye
Integrated chip
Mid infra-red applications:
Spectroscopy
Integration enables miniaturization III-V PIC?
FTIR (Fourier transform infrared spectroscopy)
Source: Nature, Wikiepedia, Agilent, Ocean Optics, Robertsbiology
Integrated chip
Medical applications:
Cytometry and detection
• Measurement & characterization of cells
Integration enables miniaturization SiP PIC?
Flow cytometer
SpectrophotometerHybridization arrays
Source: Becton-Dickinson, Affymetrix, ATI, Wikiepedia
Integrated chip
Capsule endoscopy
using photonics
Source: NIH-NCI, www.givenimaging.com
Integration enables miniaturization PIC intelligence?
Military applicationsfor biophotonics
• Battle space
• CB agent detection
• Biowarfare defense (BWD)
• Food safety
• Field intelligence
• Explosives & landmine detection
• Intrusion detection
• Water quality
• Biomonitoring
• Medical
• Diagnostics
• Forensics
• Infectious disease detection
• Therapeutics
• Drug & vaccine development
• Homeland Defense
• CB agent detection
• Intrusion sensors
• Littoral & border protection
• Explosives detection
• Building & structural monitoring
• Water supply monitoring
• Immune Buildings
• Law enforcement
Source: M CH Engineering
Broad opportunities for PICs in defense…
Is photonics
integration the
‘next generation’
IC?
Why do we integrate?
• Like any
semiconductor IC:
to achieve key
goals…
– Size, weight, power,
performance, and
cost
– Classic CMOS IC
allows higher
functionality
Integration enables innovative products…Source: Wikiepedia
2.6B transistors
2011
What options do we
have for PICs
today?
3 technology platforms
• Incumbent: –InP (Indium Phosphide)
• New challenger: –SiP (Silicon Photonics)
• Another new challenger: –Polymer Photonics (PP)
Who will win? Will all solutions win?
✔
?
?
✔
Incumbent:
Indium Phosphide
(InP)
Photonic Integrated Circuit (PIC)
Laser
Monitor
MonitorTAP
1:4 Splitter
EAMOD
Waveguide
100G transmitter chip using InPcompound semiconductor with epitaxy
PIC is a circuit with no electronic circuitry
Compound semiconductor
platform - outsourced
• Indium Phosphide (InP)
• Foundry epitaxial growth
• Foundry fabrication
Photonics devices are all
integrated together
• Waveguides, optical routing
4x25G PSM4
Transmitter
100G Coherent
Receiver
(a.k.a. 2x4 90°
Hybrid Rx)
(TIA at back)
100G Coherent
Receiver
(a.k.a. 2x4 90°
Hybrid Rx)
(TIA on side)
OneChip approach to InP PICs
• Fully monolithic InP PIC
– Core strengths
• Waveguide design
– Dilute waveguide for package
connection
– Passive guide for routing
• Integration of electrical components
– Resistors/capacitors
• Edge detector for high speeds
• Laser emitter and modulators (DC/AC)
• Fabrication of complex InP devices in a
fabless model
8yrs of PIC development at OneChip
InP PIC building
blocks developed…
distributed feedback laser
electro-absorption modulator
semiconductor optical amplifier
waveguide photodetector
P
I
P
V
P
I
I
P
ACTIVE COMPONENTS
laterally-tapered spot-size converter
Directional coupler – mode converter
vertical wavelength splitter
planar wavelength division (de)multiplexer
PASSIVE COMPONENTS
OneChip Photonics Component Library
Comprehensive library of components for integration
What’s next for
InP?
OEIC?
A PIC with integrated
electronics…
The game changer –
Integrated electronics to save real estate
• Indium Phosphide transistors are faster than Silicon
• Ft to 400+ GHz allows for future signaling speeds well over 100 Gbps per channel
• Electronics integration enables miniaturization
• No I2C, no pads fan-out
• Electronics integration enables lower power
• Opto-Electronic Integrated Circuit (OEIC)
Pre
-
Am
p
LA
/AG
C
Outp
ut
Buffer
RSSI
I2C Control
Pre
-
Am
p
LA
AG
C
Outp
ut
Buffer
RSSI
I2C Control
Commercial TIA
Customized
Design, no
function
loss
OneC
hip
OE
IC
Integrated electronics keeps all functionality!
PIC Rx chip
OCP WDM
PIC receiver
e.g.Mindspeed
4x25G TIAIntegrated TIA
300% TIA
footprint
reduction
@ 15%
OEIC real
estate
increase
OneC
hip
OE
IC
OEIC enables tiny footprint and lower cost solution
OEIC integrates electronics
onto the PIC…
Source: M indspeed/M ACOM
WDM PIC
receiver with
integrated
TIA = OEIC
The quest for smaller boxes...
with OEICs
2012 2013 20142011 2015
Switch Density Tbps
400G
800G
1T
10T
CFP
CFP/2
CFP/4
QSFP LR4 200Gbps (4x50)
CFP
CFP/2
CFP/4
QSFP
Source: Molex (modified to fit in the context)
OEIC engine
Industry
OEIC enables even smaller chip solutions…
Ultra-small, ultra-fast
OEIC engine for
Sub-Micro QSFP
100T
QSFP 400Gbps (8x50)
Micro QSFP 800Gbps
(16x50 or 8x100)
2016
PIC OSA engine(Photonic Integrated Circuit,
Optical sub-assembly)
Standard
Tx/Rx Modules
New challenger:
Silicon Photonics
(SiP)
Use of $B fabs for
photonics…
What is silicon photonics?
It’s the buzz of today…
• Use the economies of scale of a $B CMOS fab as platform
– Heterogeneous with III-V, oxide, nitride, SiGe for innovative applications
• Issues
– Volume? <1% of the business of a silicon fab: attention?
– Lasers? InP best option (impractical for silicon)
– Packaging: bump/bond InP lasers; I/O with electronics and optics
Many merits; many questions (lots of investment)
?
?
Source: Intel
Will SiP achieve the
cost/performance
metrics???
SiP is complex, however,
innovation with PP helps…
• Silicon photonics needs very high volumes
• Silicon photonics is becoming more complex than
‘simply silicon’
– Detectors, TIA/drivers are requiring SiGe
• SiGe means epitaxial growth $$
– Lasers are InP and require flip-chip bumping/bonding etc
• Integration of CMOS and photonics not easy $$
– Luxtera now packaging 3 silicon chips (CMOS, Laser and Photonics chip) as its
easier than pure monolithic integration…
• SiP integration with polymer photonics (PP)
– Low cost, high performance, less complex fab
Yes – SiP will win in time although mkts may evolve…
✔
✔ ✔
✔✔
New challenger:
Polymer
Photonics (PP)
Blends New Material
• LWLG Multi-Chromophore Process• Increased loading of
chromophore
• Increased EO activity
• Does not sacrifice thermal stability
• Increased durability
• Low voltage
Source: Lightwave Logic (LWLG)
Chemistry of polymer photonics
Polymers offer ‘scalability’ in volume and cost
Polymer photonics: Fiber to slot waveguide
Grating Coupler
Taper CouplerSlot Mode
Grating Coupler
Optical 38GBd
• Reduced size
• Integration advantage
• Improved insertion lossLight in
Taper
Coupler
Initial results promising: polymer and silicon photonicsSource: Lightwave Logic (LWLG)
Flexible OLED displays
enable many new applications
Source: Prof. Changhee Lee, SNU, Korea
Future display
concepts
Applications drive different solutions to photonics
Trade-offs between
the technologies
Monolithic Integration (one
chip)
Polymer photonics with SiP
Opto-Eletronic IC (OEIC) made
possible in single chip
Simpler packaging
Small size
Indium
Phosphide
Low power CMOS
Silicon fab for processing
Economies of scale ???
Silicon
Photonics
Winner has to achieve the clear priorities in their market
All 3 want to do
integrated photonics…
InP incumbent however SiP and PP are attractive… Source: Lightwave Logic (LWLG)
Silicon poor laser…
Polymer photonics with InP
InP laser
SiP and PP photonics
Si driver/TIA
Si Semi-custom ASIC
Technology choice:
Scale shows practicality…
Silicon photonics is not simply a silicon solution…
All InP combinations of technology All SiP/PP
InP laser
InP photonics
InP driver/TIA
InP Semi-custom ASIC
Silicon photonics
✔✔✔
✔✔✔
InP compound semiconductorChallenger
Incumbent
?
Polymer photonics
Challenger
USA Integrated
photonics
competition and
update (2015)
USA competition in 2015
•IMI (Institute for Manufacturing Innovation)–$1B investment for 15 manufacturing hubs
–Integrated photonics one of the hubs
–$110M over 5years
–End to end innovation ‘ecosystem’• Domestic integrated photonics chip fabrication foundry access,
seamlessly integrated and standardized design tools, automated packaging, assembly and test, and workforce development
Driven to strengthen manufacturing in USA
Integrated photonics competition finalists
• Florida (led by UCF) called PRISM– Vertically integrated foundry play with 68 industrial partner
– Universities: Georgia Tech, Clemson, Illinois, Alabama
– Cited expertise: Flexible glass, specialty fiber, high power diode lasers
• New York (led by SUNY) called AIM photonics– Vertically integrated foundry play with total funding ~$650M
– 21 industrial partners with 5:1 match (PR April 2015)
– Universities: Rochester, Arizona, UCSB, MIT
– Cited expertise: Silicon photonics, large 300mm fab that is IMEC-like
• California (led by USC) called IPI-CDMS– Horizontally integrated foundry play with total funding ~$500M
– >60 industrial partners
– Universities: ASU, Ohio state, UCSD, UC Berkeley, UCLA
✔
✗
✗NY vertical integration model won…
DoD guidelinesfor funding
DoD wanted focus in design, test, A&Pkg, education, training
Low-Volume
Circuit
Designers-- Startup, SMEs, IDMs,
Defense, University, etc.
Since 1981
ITAR – USA Vendors
DMEA Accredited/Trusted
• Design Kits, Doc
• Design Check
• Technical Q’s
• Prototypes/Small Prod.
• Flexibility on Die Size
Dicing + Packaging• Flip-Chip, Plastic, …
Process
Monitoring• In situ circuits
Circuit Designs
User Support
Cost-Effective Prototype
and Small-Volume
Chips
>60,000
Completed
Projects
Wafer + Device Testing• Parametric, Functional
Leading Foundry Access• Small Lots, Multi-Project Runs
• TSMC, IBM, Global Foundries, …
• CMOS, RF, III-V, MEMS, Photonics
MOSIS horizontalbusiness model
MOSIS service to IC and fab end-to-end (+ photonics)
Your
Chip Is
Here
Multi-project reticule
~ 50 different designs
Many designs on single die; cost to
customer is approximately in direct
proportion to area used
Shared Costs: mask, wafer, and foundry and packager interface
Typical 28nm CMOS cost: single run: >$4M; MPW user: <$150K
MOSIS MPWstructure (ICs)
Shared costs can be very competitive
Technology
roadmaps
Actual industry needs are complex (will simplify next few slides)
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
Purple Brick Wall = Technology cost barrier
Slanted Font: Major industry efforts are required for commercialization
40Gbps 100Gbps 400Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick Wall DSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
74
Technology cost barriers
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Institute plan
Typical link reach
Ind wish (@400Gbps)
Institute plan
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 400Gbps 1000Gbps
<10km <10km <2km <2km
<2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps
<$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick Wall
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick Wall50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Purple Brick Wall
= Technology cost barrier
Silicon world…Red brick wall (ITRS) technology barrier
SiP and III-V new world…Purple brick wall (IPI-CDMS) technology cost barrier
Sometimes we have the technology but not at the costfor industry to implement…
These are pain points the industry wants solved
Filling the gaps fordatacenter interconnects
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Accelerating customer goals by at least 1year or more is an attractive proposition…
Example: for HPC short distance (10-100m) interconnects; industry wishes
$0.25/Gbps @400Gbps in 2019, and folks need to plan on ‘scalable’ technologies
to support $0.25/Gbps @400Gbps by 2018 (1 full year earlier)
Feeding the gapswith technology
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Technology
And the technology will be integrated photonics…
Scalable projects: low cost, low volume
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 400Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Optimizing
technology and
creating scalable
solutions to achieve
roadmap goals
Achieve industry metrics:cost barriers
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 400Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Optimizing todays
technology and
creating scalable
solutions to achieve
roadmap goals
Driving through
technology cost
barriers for
industry
The hard to reachchallenges
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 400Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Driving through
technology cost
barriers for
industry
Optimizing todays
technology and
creating scalable
solutions to achieve
roadmap goals
Hard to reach
performance
challenges
A continually evolvingroadmap
2015 2018 2020 2022
Modules/TxRxData rate density
Form factor
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
Typical link reach
Ind wish (@400Gbps)
Photonics foundry
S/C chip line rateLevel of integration
Energy/bit
Modulation formatPackaging platform
Generic pkg design
Perf/real estateBumping design
Perf/channel
Channels/real estate
TSV processesChip interconnect
Fiber technology
AC/DC wafer testConnector design
R&QA
25G PIC/OEIC M/Ch 100Gbps OEIC
NH 25GHz PIC OSA NH100Gbps OEIC OSA (SiP or C/S)
SiP PIC stk 10-25GHz TSV+3D stk 50GHz OEIC (SiP or C/S) 3D-baseline 3D 25GHz PIC 3D 50GHz PIC
40Gbps 100Gbps 400Gbps 1000Gbps
<10km <10km <2km <2km <2km
10 Tbps/1U 25Tbps/1U 50Tbps/1U 100Tbps/1U 400Tbps/1U
$5/Gbps $2/Gbps <S0.5/Gbps
<$5/Gbps $0.5/Gbps$1/Gbps>$10/Gbps (<2km)
10-100m 5-50m 1-25m
<$1/Gbps <$0.5/Gbps <$0.25/Gbps <$0.05/Gbps
$1/Gbps $0.25/Gbps <$0.15/Gbps
10-25Gbps 50Gbps 100Gbps >1000Gbps Disc Driver/TIA OEIC 100Gbps int Driver/TIAInt TIA OEIC int Driver/TIA 50Gbps
CFP4 QSFP DSFP SFP+ (new)
20pJ/b 10pJ/b 4pJ/b 2pJ/b 0.5-1pJ/b
25GHz FlipChip; 50GHz FlipChip 100GHz Flip Chip
25Gbps/Ch 50Gbps/Ch 100Gbps/Ch
CFP4/1D array QSFP and 2D array SFP & 2D array
100/mm2 500/mm2 1000/mm2 10,000/mm2
10Gb/mm2 40Gb/mm2 (inc driver/TIA) 80Gb/mm2 120Gb/mm2
300m 10G (1D array) 100m 25G (2D array/MCF)
NRZ NRZ/PAM4 NRZ/PAM4/8 NRZ/PAM4-16
10-25G 50G 100G
Std Bellcore Adv R&QA process R&QA C/S & SiP manf product
$1/Gbps
Purple Brick Wall
>100G
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Micro-SFP
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall Coherent?
3D 50GHz OEIC Purple Brick Wall 3D 100GHz OEICPurple Brick WallTSV+3D stk PIC 25GHz
Purple Brick WallNH 50Gbps OEIC OSA (SiP or C/S)
10Gbps PIC Purple Brick WallM/Ch 50G OEIC50G PIC/OEIC
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall
Purple Brick Wall 50m 50G (1D/MCF) 100m 25G (1D/MCF)
Purple Brick Wall
Purple Brick WallDSFP and 2D array
Purple Brick WallR&QA C/S and SiP for prototype
Update metrics,
technologies, timing
as needed by
industry: living
document
Even the venture
capitalists are
smelling
opportunity…
Pertinent transactions in
communications for PIC related technologies
? <30M$,
2012
271 M$, 2012
400 M$, 2013
82 M$, 2013
47 M$, 2013
Technology sale;
40G/100G discrete
components
Technology sale;
40/100G silicon
photonics
$200M rev (2X) to
access InP discrete
40/100G
Technology sale:
Silicon Photonics
solution 40/100G
CMOS VCSEL Driver
and TIA 40/100G with
~$20-30M rev (2X)
Ma230 M$, 2014 InP Laser componentsMACOMBin Optics
High interest (~$1B) in photonics for datacenterSource: Pacific Core Partners
Summary
Let’s review…
• Global markets for photonics are huge and growing ($500B+)
– Lighting, solar, strong growth (especially Asia)
– Communications growth area (Europe/North America)
• Internet is still growing quickly
– Our appetite for data is still growing
– New applications are being enabled through miniaturization
• Integrated photonics is the next generation IC
– PICs will be key chips for datacenters as they grow to 400, 800, 1Tbps
– Trend to integrate electronics with photonics for smaller real estate
– III-V InP, silicon photonics, and polymer photonics all will become
PICs
Integrated photonics is a central theme…
In a decade:
the 3 technology platforms…
• Incumbent: – InP (Indium Phosphide)
• New challenger: – SiP (Silicon Photonics)
• Heterogeneous, oxide, nitride, SiGe
• Another new challenger: – Polymer Photonics (PP), OLED
All will be symbiotic with each other
✔
✔
✔
Remember the 3 takeaways
from the beginning…
• Photonics enables many things and is part of our lifestyle…from medical to consumer
• Photonics will be integrated – just like ICs 50years ago and drive new product designs…absolutely…and the next generation IC…
• Is integrated photonics a paradigm shift for the tech community…no question…
Our thirst for smaller, lighter, faster will enable PICs…
Thank you for
listening:drmlebby@gmail.com
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