Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital...

Penn ESE370 Fall2014 -- DeHon1

ESE370:Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 23: October 24, 2014Pass Transistor Logic: part 2(Cascading without Buffers)

Previously

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Two XOR Gates

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Today

• Pass Transistor Circuit– Output levels– Cascading

• Series pass transistors?• Delay

• Start on Distributed RC– Analyzing delay for pass-tr designs

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Cascading Pass Transistors

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Chain without Inverters• What if we did this?

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Extract key path

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t=0 (after Vin transition 10)

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t=4 (after Vin transition 10)

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t=∞ (after Vin transition 10)

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Focus on Pass tr

• Vgs?• Operation mode?• Current flow?

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Voltage of Chain

• What is voltage at output?

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How compare

• Compare

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DC Analysis

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DC Analysis – chain of 6

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Conclude

• Can chain any number of pass transistors and only drop a single Vth

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Transient

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Closeup

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Inverter Sense

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Capacitance

• What is Capacitance per stage (@y)?

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Delay Setup

• What does RC circuit look like?

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Pass TR Tree• What if we did this?

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Path• What’s different about this?

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Gate Cascade?

• What are voltages?

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Demonstration Circuit

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SPICE

• TODO show spice results of voltages

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Demonstration Chain

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Spice

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Transient Response

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Conclude

• Cannot cascade degraded inputs into gates.

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Distribute RC (setup)

Time Permitting

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What is response?

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What is response?

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What is response?

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SPICE Response

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Intuition

• Look at series of R’s on path– Must move Q=V(C) across each R

• Not as much as if both R’s precede C’s

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Idea

• There are other circuit disciplines• Can use pass transistors for logic

– Even chains of pass transistors– Sometimes gives area or delay win

• Do not cascade as easily as CMOS

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Admin

• Project– Milestone 1 in– Will try to get feedback Friday evening/Sat.– Should be working hard on project– Rewarding experience

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