Page Replacement Implementation Issues Text: –Tanenbaum ch. 4.7

Page Replacement Implementation Issues

• Text:– Tanenbaum ch. 4.7

Instruction Backup• Page handling involves restarting the instruction

that causes the trap• Need to determine the first byte of instruction -

difficult for some CPUs• CPU uses an internal hidden register to copy the

PC before executing the instruction

If page fault occurs here,where does the instruction begin?

Locking Page in Memory• Virtual memory and I/O occasionally interact• A process issues call for read from device into

buffer– while waiting for I/O, another process starts up– has a page fault– buffer for the first process may be paged out– data from I/O may get loaded on the new page

• Need to specify some pages locked (pinning in memory)– exempted from removal from memory

Backing Store

(a) Paging to static swap area- problem with process that increases in size after starting

(b) Backing up pages dynamically- allocate disk space when the page is swapped out and deallocate it when it is swapped

back in

Proc size

Proc size

Separation of Policy and Mechanism

• Where is the page replacement algorithm?

Growing Tables• One dimensional address space with growing

tables, one table may bump into another• Consider a compiler table example:

Segmentation• Divide the address space into segments and each segment can

grow independent of each other• segments have large address space to prevent bumping into each

other• two part address- a segment number and address within the

segment

Advantages of Segmentation

• Modification and compilation of one segment’s procedure will not affect any other procedures in other segments (no starting address has been modified)

• Better sharing of procedures or data between processes (put shared libraries in a special segment)

• Different protection for different segments

Comparison of Paging and Segmentation

Implementation of Pure Segmentation• Segments are of various sizes (different from paging)• Evicting and loading segments cause checkerboarding

x86 Segmentation with Paging• x86 has 16K segments each holding 4GB of data• To access a segment, x86 first loads a selector

into one of CPU’s six segment registers (cs, ds, ss, es, fs, gs).

• The corresponding LDT or GDT is fetched and stored in microprogram registers.

(Requestor’s)

Segment Descriptor• Each program uses a Local Descriptor Table (LDT) to

describe the code, data, stack etc.• A single Global Descriptor Table(GDT) shared among

all programs describes OS etc.• Code segment descriptor:

(descriptor)

Conversion to Linear Address• Segment translation- logical address (what the applications

see) to linear address (address for each segment)• Page translation- linear address to physical address

16-bit 32-bitLogical address

Mapping of a linear address onto a physical address

Protection on x86• Both Linux and Win32, only 0 and 3 are used• Access to segments done by evaluating:

– CPL: internal register stores current privilege level– DPL: descriptor privilege level– RPL: requestor’s privilege level

Level