optimazation of standard cell layout

OPTIMIZATION OF STANDARD CELL LAYOUT

Prepared by: Yash Nagaria(16MECV15)Ocean Godre(16MECV15)

Guided by : Dr. Amisha Naik

Index

Abstract Standard Cell Design List of Standard Cells Layout Standard Cell Library Library Design Flow Standard Cell Cell Design Flow Layout Condition Introduction about research

Hammer Head Removal

Move the Gate Contact over Active Area

Source/Drain Capacitances Reduction

INTERNAL POWER AND AREA GAIN

Summary Conclusion

Abstract Here we have presented several layout optimizations in order to decrease both,

the internal power and the area of digital standard cells.

A new D flip-flop (Dff) is designed using advanced design rules and lower

active widths.

Post-layout simulations are performed and the internal power of a new Dff is

reduced by 20% while clock-to-Q delay remains unchanged.

The saturation current (IDSAT) is improved by 15% and 50% for NMOS

and PMOS transistors, respectively. Moreover, the area of the new Dff is

reduced by 20% by using lower active widths and new optimized design rules.

Standard Cell Design

Design Using Standard Cell, pre-design by professionals. Cells includes Verilog, Circuit, Layout Information for NAND,

NOR, D-FF Logic Design and Layout Design done by CAD.

Logic Design --- by use of Cells with specified delays Layout Design – by use of Cells

Generated Data is mainly interconnection wires.

Standard Cell DesignLogic gates, latches, flip-flops, or larger logic

Routingchannels

List of Standard Cells Inverter Inverting Buffer Non-inverting Buffer Tri-state Non-inverting Buffer AND 2, 3, 4 inputs NAND 2,3,4 inputs OR 2, 3, 4 inputs NOR 2,3,4 inputs XNOR 2,3 inputs AND-OR AND-OR-Inverter OR-AND OR-AND-Inverter Multiplexer 2 to 1 Multiplexer 4 to 1

Decoder 2 to 4 Half Adder 1bit Full Adder 1bit

Pos Edge DFF Neg Edge DFF Scan Pos Edge DFF Scan Neg Edge DFF RS NAND Latch High-Active Clock Gating Latch Non-inverting Delay line Pass Gate Bidirectional Switch Hold 0/1 Isolation Cell

Layout

Standard Cell Library Circuit description at RTL level Layout description in GDSII format TLF Format Data

Logical information Transistor and interconnect parastics Spice netlist Power information Process, temperature and supply voltage

Library Design Flow I

Layout DesignMask Data

GDSII

Abstract Generator

Extraction

Analog Environment

Library DataLEF

Circuit DataNetlist

Circuit DataTLF

I/O delay pathsTiming check valuesInterconnect delays

Cell InformationTechnology information

Library Design Flow IIPhysical Layout (gdsII, Virtuoso Layout Editor)Should follow specific design standards eg. constant height, offsets etc.

Logical View (verilog description or TLF)Verilog is required for dynamic simulation. Place and route tools usually can use TLF. Verilog description should preferably support back annotation of timing information.

Abstract View (Cadence Abstract Generator, LEF)LEF: Contains information about each cell as well as technology information

Timing, power and parasitics (TLF)Transistor and interconnect parasitics are extracted using Cadence or other extraction tools (SPACE). Spice or Spectre netlist is generated and detailed timing simulations are performed. Power information can also be generated during these simulations. Data is formatted into a TLF file including process, temperature and supply voltage variations.

Standard Cell I

Standard Cell II

Cell Design Flow

Synopsys Design Compiler

Cadence Design Planner

Cadence Silicon Ensemble

Cadence ICFB

Modelsim

VHDL Model

Verilog Model

DEF File

DEF File

Verilog Model

VHDL -> VerilogConversion

Standard Cell Placement

Standard Cell Routing

Export to Other Formats,SPICE Verification

Verilog Verification

Layout Condition

parameter Symbol value figureCell height H 36λ 900 nmPower rail width

W1 2λ 50 nm

Vertical grid W2 4λ 100 nmHorizontal gird W3 4λ 100 nmNwell height W4 20λ+α 525 nm45 nm Process (λ=25nm, Minimum wire width=2λ)

Introduction about research Nowadays, many applications based on microcontrollers require more

processing speed and less dynamic and static consumption to increase battery lifetime of mobile applications such as tablets, smartphones, and laptops .

Our main aim is to study the possibility to reduce both, the internal power and the area in digital standard cells by remaining on same technological node.

In order to decrease the internal power consumed by the standard cells, the MOSFETs have to be designed using the lowest width as far as possible, especially when high performances are not necessary.

However, by using the conventional 80 nm design rules, designers have to insert an active Hammer Head (HH) in order to place the source and drain (S/D) contacts.

Continue….&Hammer Head Removal

As presented in Fig. 1, this solution increases the transistor length (noted ‘X’) by 28% due to the poly-to-active (po2act) distance.

As shown in Fig, this solution increases the transistor length (noted ‘X’) by 28% due to the poly-to-active (po2act) distance .

Hammer Head Removal Now , we will see the possibility to remove the active HH while

maintaining a high level of process robustness. A chain resistance of more than 12,000 contacts in series is measured on several devices designed with different active widths (WACT) is shown in fig.

Continue…. In device 1, the active HH is not needed to contact the S/D regions

because WACT = 2WMIN. However, the active HH has to be added in devices 2, 3 and 4 designed using lower WACT. Device 4 is the most aggressive layout designed without the contact enclosure in W and L directions .

As presented in fig, the contact resistance increases when WACT is reduced due to the increase of the active finger resistance.

As presented in Fig. 4, the contact resistance increases when WACT is reduced due to the increase of the active finger resistance.

Moreover, no effect of the distance LACT is observed comparing device 3 and device 4 designed without the contact enclosure.

Continue….. In order to estimate the intrinsic change induced by the modifications, the

threshold voltage (VT), the saturation (IDSAT), linear (IDLIN) and drain leakage (IOFF) currents have been measured. The poly HH is also removed as shown in Fig..

Then, CMOS inverters Ring Oscillators (ROs) are used to confirm the dynamic behaviour of different layouts presented in Fig..

Move the Gate Contact over Active Area

The layout using the gate contact over active area is presented in Fig.. and let us significantly reduce the transistor height (Y) by 25%. This, could be interesting in particular standard cells layout.

Source/Drain Capacitances Reduction In order to decrease the dynamic current, all capacitances need to be

scaled down. When CLOAD is mainly due to intrinsic MOSFET capacitances, a

slight reduction of the S/D capacitances let us decrease the dynamic current without impacting the ring oscillator speed.

he other benefit of this technique is to take advantage of STI-induced mechanical stress to enhance holes mobility , even if, electrons mobility will be reduced.

INTERNAL POWER AND AREA GAIN From our previous work, a new process has been developed in order to

improve MOSFETs saturation current.

IDSAT is improved by 15% and 50% for NMOS and PMOS transistors, respectively, while IOFF remains unchanged.

Summary

Conclusion With the use of different mobility boosters,

MOSFET active widths could be reduced to decrease internal power and area of standard cells without impacting the propagation delays.